TimeQuest Timing Analyzer report for SUSKA-III-C
Tue Dec 07 11:46:47 2021
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow Model Fmax Summary
  7. Slow Model Setup Summary
  8. Slow Model Hold Summary
  9. Slow Model Recovery Summary
 10. Slow Model Removal Summary
 11. Slow Model Minimum Pulse Width Summary
 12. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 13. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 14. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 15. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 16. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 17. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 18. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 19. Slow Model Setup: 'CODEC_SCLK'
 20. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 21. Slow Model Setup: 'CLK_PLL1'
 22. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 23. Slow Model Hold: 'CODEC_SCLK'
 24. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 25. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 26. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 27. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 28. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 29. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 30. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 31. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 32. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 33. Slow Model Hold: 'CLK_PLL1'
 34. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 35. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 36. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 37. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 38. Slow Model Recovery: 'CODEC_SCLK'
 39. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 40. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 41. Slow Model Removal: 'CODEC_SCLK'
 42. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 43. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 44. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 45. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 46. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 47. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 48. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 49. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 50. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 51. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 52. Slow Model Minimum Pulse Width: 'CLK_PLL1'
 53. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 54. Slow Model Minimum Pulse Width: 'CLK_PLL2'
 55. Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
 56. Slow Model Minimum Pulse Width: 'CODEC_SCLK'
 57. Setup Times
 58. Hold Times
 59. Clock to Output Times
 60. Minimum Clock to Output Times
 61. Propagation Delay
 62. Minimum Propagation Delay
 63. Output Enable Times
 64. Minimum Output Enable Times
 65. Output Disable Times
 66. Minimum Output Disable Times
 67. Fast Model Setup Summary
 68. Fast Model Hold Summary
 69. Fast Model Recovery Summary
 70. Fast Model Removal Summary
 71. Fast Model Minimum Pulse Width Summary
 72. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 73. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 74. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 75. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 76. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 77. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 78. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 79. Fast Model Setup: 'CODEC_SCLK'
 80. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 81. Fast Model Setup: 'CLK_PLL1'
 82. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 83. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 84. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 85. Fast Model Hold: 'CODEC_SCLK'
 86. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 87. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 88. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
 89. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
 90. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 91. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 92. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 93. Fast Model Hold: 'CLK_PLL1'
 94. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 95. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 96. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 97. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 98. Fast Model Recovery: 'CODEC_SCLK'
 99. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
100. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
101. Fast Model Removal: 'CODEC_SCLK'
102. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
103. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
104. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'
105. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'
106. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
107. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
108. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
109. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
110. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
111. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
112. Fast Model Minimum Pulse Width: 'CLK_PLL1'
113. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
114. Fast Model Minimum Pulse Width: 'CLK_PLL2'
115. Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
116. Fast Model Minimum Pulse Width: 'CODEC_SCLK'
117. Setup Times
118. Hold Times
119. Clock to Output Times
120. Minimum Clock to Output Times
121. Propagation Delay
122. Minimum Propagation Delay
123. Output Enable Times
124. Minimum Output Enable Times
125. Output Disable Times
126. Minimum Output Disable Times
127. Multicorner Timing Analysis Summary
128. Setup Times
129. Hold Times
130. Clock to Output Times
131. Minimum Clock to Output Times
132. Progagation Delay
133. Minimum Progagation Delay
134. Setup Transfers
135. Hold Transfers
136. Recovery Transfers
137. Removal Transfers
138. Report TCCS
139. Report RSKM
140. Unconstrained Paths
141. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; SUSKA-III-C                                                     ;
; Device Family      ; Cyclone II                                                      ;
; Device Name        ; EP2C35F484C7                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Unavailable                                                     ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------+
; SDC File List                                                                                  ;
+------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                              ; Status ; Read at                  ;
+------------------------------------------------------------+--------+--------------------------+
; ../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc ; OK     ; Tue Dec 07 11:46:21 2021 ;
+------------------------------------------------------------+--------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; Clock Name                                                 ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master        ; Source                                    ; Targets                                     ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; CLK_PLL1                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL1 }                                ;
; CLK_PLL2                                                   ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL2 }                                ;
; CODEC_SCLK                                                 ; Base      ; 81.400 ; 12.29 MHz ; 0.000 ; 40.700 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CODEC_SCLK }                              ;
; CRT_PIN4_CLK1                                              ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CRT_PIN4_CLK1 }                           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Generated ; 20.833 ; 48.0 MHz  ; 0.000 ; 10.416 ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[2] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 39.062 ; 25.6 MHz  ; 0.000 ; 19.531 ; 50.00      ; 5         ; 8           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 25.390 ; 39.39 MHz ; 0.000 ; 12.695 ; 50.00      ; 13        ; 32          ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[2] } ;
+------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary                                                                                                                            ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                 ; Note                                                  ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
; 13.88 MHz   ; 13.88 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;                                                       ;
; 13.88 MHz   ; 13.88 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;                                                       ;
; 38.25 MHz   ; 38.25 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;                                                       ;
; 38.25 MHz   ; 38.25 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;                                                       ;
; 49.48 MHz   ; 49.48 MHz       ; CODEC_SCLK                                                 ;                                                       ;
; 58.51 MHz   ; 58.51 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 58.51 MHz   ; 58.51 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;                                                       ;
; 150.15 MHz  ; 150.15 MHz      ; CLK_PLL1                                                   ;                                                       ;
; 420.88 MHz  ; 420.88 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ;                                                       ;
; 519.21 MHz  ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; limit due to high minimum pulse width violation (tch) ;
; 1164.14 MHz ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; limit due to high minimum pulse width violation (tch) ;
+-------------+-----------------+------------------------------------------------------------+-------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------+
; Slow Model Setup Summary                                                             ;
+------------------------------------------------------------+---------+---------------+
; Clock                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------+---------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -18.401 ; -7932.130     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -18.401 ; -7932.130     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -15.544 ; -2130.320     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -15.544 ; -2130.320     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -13.239 ; -397.650      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -13.239 ; -397.650      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 23.014  ; 0.000         ;
; CODEC_SCLK                                                 ; 30.595  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.203  ; 0.000         ;
; CLK_PLL1                                                   ; 55.840  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.574  ; 0.000         ;
+------------------------------------------------------------+---------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Hold Summary                                                            ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; CODEC_SCLK                                                 ; 0.278 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.445 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.445 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.445 ; 0.000         ;
; CLK_PLL1                                                   ; 0.620 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 21.278 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 21.278 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 21.278 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 21.278 ; 0.000         ;
; CODEC_SCLK                                                 ; 78.638 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 2.274 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 2.274 ; 0.000         ;
; CODEC_SCLK                                                 ; 2.472 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 2.858 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 2.858 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 7.852  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 7.852  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.584 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.061 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.061 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.420 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 28.943 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 28.943 ; 0.000         ;
; CLK_PLL1                                                   ; 30.139 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.139 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.136 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                     ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -18.401 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.015      ; 28.871     ;
; -18.401 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.015      ; 28.871     ;
; -18.361 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 28.830     ;
; -18.361 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 28.830     ;
; -18.317 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.015      ; 28.787     ;
; -18.317 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.015      ; 28.787     ;
; -18.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 28.746     ;
; -18.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 28.746     ;
; -18.043 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 28.527     ;
; -18.043 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 28.527     ;
; -18.005 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.488     ;
; -18.005 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.488     ;
; -18.003 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.486     ;
; -18.003 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.486     ;
; -17.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.475     ;
; -17.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.475     ;
; -17.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.447     ;
; -17.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.447     ;
; -17.952 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.434     ;
; -17.952 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.434     ;
; -17.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.427     ;
; -17.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.427     ;
; -17.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.386     ;
; -17.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.386     ;
; -17.896 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.379     ;
; -17.896 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.379     ;
; -17.856 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.338     ;
; -17.856 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.027      ; 28.338     ;
; -17.829 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 28.313     ;
; -17.829 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 28.313     ;
; -17.789 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.272     ;
; -17.789 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.028      ; 28.272     ;
; -17.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 28.122     ;
; -17.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 28.122     ;
; -17.608 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 28.079     ;
; -17.608 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 28.079     ;
; -17.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 28.038     ;
; -17.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 28.038     ;
; -17.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 28.002     ;
; -17.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 28.002     ;
; -17.524 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 27.995     ;
; -17.524 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 27.995     ;
; -17.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 27.972     ;
; -17.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 27.972     ;
; -17.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.918     ;
; -17.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.918     ;
; -17.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.895     ;
; -17.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.895     ;
; -17.428 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 27.888     ;
; -17.428 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.005      ; 27.888     ;
; -17.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 27.827     ;
; -17.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 27.827     ;
; -17.350 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.811     ;
; -17.350 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.811     ;
; -17.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.782     ;
; -17.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.782     ;
; -17.299 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 27.778     ;
; -17.299 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 27.778     ;
; -17.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 27.743     ;
; -17.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.010      ; 27.743     ;
; -17.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.731     ;
; -17.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.731     ;
; -17.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.739     ;
; -17.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.739     ;
; -17.254 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 27.726     ;
; -17.254 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 27.726     ;
; -17.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.030      ; 27.735     ;
; -17.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.030      ; 27.735     ;
; -17.248 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.726     ;
; -17.248 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.726     ;
; -17.237 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.698     ;
; -17.237 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.698     ;
; -17.219 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 27.688     ;
; -17.219 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 27.688     ;
; -17.212 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.696     ;
; -17.212 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.696     ;
; -17.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.678     ;
; -17.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.678     ;
; -17.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.683     ;
; -17.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.683     ;
; -17.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.647     ;
; -17.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.006      ; 27.647     ;
; -17.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 27.658     ;
; -17.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 27.658     ;
; -17.170 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 27.642     ;
; -17.170 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 27.642     ;
; -17.154 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.628     ;
; -17.154 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.628     ;
; -17.152 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.630     ;
; -17.152 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 27.630     ;
; -17.151 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.635     ;
; -17.151 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.029      ; 27.635     ;
; -17.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.619     ;
; -17.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.619     ;
; -17.135 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 27.604     ;
; -17.135 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 27.604     ;
; -17.132 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.606     ;
; -17.132 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.019      ; 27.606     ;
; -17.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 27.589     ;
; -17.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.018      ; 27.589     ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                     ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -18.401 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.015      ; 28.871     ;
; -18.401 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.015      ; 28.871     ;
; -18.361 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 28.830     ;
; -18.361 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 28.830     ;
; -18.317 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.015      ; 28.787     ;
; -18.317 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.015      ; 28.787     ;
; -18.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 28.746     ;
; -18.277 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 28.746     ;
; -18.043 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 28.527     ;
; -18.043 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 28.527     ;
; -18.005 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.488     ;
; -18.005 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.488     ;
; -18.003 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.486     ;
; -18.003 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.486     ;
; -17.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.475     ;
; -17.992 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.475     ;
; -17.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.447     ;
; -17.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.447     ;
; -17.952 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.434     ;
; -17.952 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.434     ;
; -17.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.427     ;
; -17.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.427     ;
; -17.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.386     ;
; -17.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.386     ;
; -17.896 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.379     ;
; -17.896 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.379     ;
; -17.856 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.338     ;
; -17.856 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.027      ; 28.338     ;
; -17.829 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 28.313     ;
; -17.829 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 28.313     ;
; -17.789 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.272     ;
; -17.789 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.028      ; 28.272     ;
; -17.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 28.122     ;
; -17.657 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 28.122     ;
; -17.608 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 28.079     ;
; -17.608 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 28.079     ;
; -17.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 28.038     ;
; -17.573 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 28.038     ;
; -17.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 28.002     ;
; -17.541 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 28.002     ;
; -17.524 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 27.995     ;
; -17.524 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 27.995     ;
; -17.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 27.972     ;
; -17.512 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 27.972     ;
; -17.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.918     ;
; -17.457 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.918     ;
; -17.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.895     ;
; -17.434 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.895     ;
; -17.428 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 27.888     ;
; -17.428 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.005      ; 27.888     ;
; -17.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 27.827     ;
; -17.362 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 27.827     ;
; -17.350 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.811     ;
; -17.350 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.811     ;
; -17.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.782     ;
; -17.321 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.782     ;
; -17.299 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 27.778     ;
; -17.299 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 27.778     ;
; -17.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 27.743     ;
; -17.278 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.010      ; 27.743     ;
; -17.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.731     ;
; -17.270 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.731     ;
; -17.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.739     ;
; -17.261 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.739     ;
; -17.254 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 27.726     ;
; -17.254 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 27.726     ;
; -17.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.030      ; 27.735     ;
; -17.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.030      ; 27.735     ;
; -17.248 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.726     ;
; -17.248 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.726     ;
; -17.237 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.698     ;
; -17.237 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.698     ;
; -17.219 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 27.688     ;
; -17.219 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 27.688     ;
; -17.212 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.696     ;
; -17.212 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.696     ;
; -17.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.678     ;
; -17.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.678     ;
; -17.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.683     ;
; -17.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.683     ;
; -17.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.647     ;
; -17.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.006      ; 27.647     ;
; -17.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 27.658     ;
; -17.183 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 27.658     ;
; -17.170 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 27.642     ;
; -17.170 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 27.642     ;
; -17.154 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.628     ;
; -17.154 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.628     ;
; -17.152 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.630     ;
; -17.152 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 27.630     ;
; -17.151 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.635     ;
; -17.151 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.029      ; 27.635     ;
; -17.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.619     ;
; -17.145 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.619     ;
; -17.135 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 27.604     ;
; -17.135 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 27.604     ;
; -17.132 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.606     ;
; -17.132 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.019      ; 27.606     ;
; -17.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 27.589     ;
; -17.116 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.018      ; 27.589     ;
+---------+---------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                            ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -15.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 26.001     ;
; -15.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 26.001     ;
; -15.537 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 26.006     ;
; -15.537 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 26.006     ;
; -15.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.948     ;
; -15.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.948     ;
; -15.460 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.917     ;
; -15.460 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.917     ;
; -15.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.922     ;
; -15.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.922     ;
; -15.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.871     ;
; -15.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.871     ;
; -15.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.868     ;
; -15.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.868     ;
; -15.414 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.864     ;
; -15.414 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.864     ;
; -15.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.851     ;
; -15.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.851     ;
; -15.368 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.837     ;
; -15.368 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.837     ;
; -15.366 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.834     ;
; -15.366 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.834     ;
; -15.357 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 25.824     ;
; -15.357 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 25.824     ;
; -15.335 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.787     ;
; -15.335 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.787     ;
; -15.334 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.784     ;
; -15.334 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.784     ;
; -15.332 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.784     ;
; -15.332 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.784     ;
; -15.331 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.788     ;
; -15.331 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.788     ;
; -15.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.786     ;
; -15.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.786     ;
; -15.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.773     ;
; -15.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.773     ;
; -15.311 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 25.767     ;
; -15.311 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 25.767     ;
; -15.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.759     ;
; -15.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.759     ;
; -15.301 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.767     ;
; -15.301 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.767     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.015      ; 25.754     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.753     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.015      ; 25.754     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.753     ;
; -15.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.750     ;
; -15.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.750     ;
; -15.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.749     ;
; -15.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.749     ;
; -15.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 25.740     ;
; -15.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 25.740     ;
; -15.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 25.722     ;
; -15.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 25.722     ;
; -15.260 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.729     ;
; -15.260 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.729     ;
; -15.259 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.717     ;
; -15.259 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.717     ;
; -15.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.700     ;
; -15.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.005     ; 25.700     ;
; -15.247 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.704     ;
; -15.247 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.704     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.711     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.702     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.711     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.702     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.683     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.689     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 25.683     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 25.689     ;
; -15.227 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 25.683     ;
; -15.227 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 25.683     ;
; -15.223 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.691     ;
; -15.223 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.691     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.689     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.688     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.689     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 25.688     ;
; -15.218 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.675     ;
; -15.218 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.675     ;
; -15.207 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.673     ;
; -15.207 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 25.673     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.657     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.015      ; 25.670     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.657     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.015      ; 25.670     ;
; -15.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.656     ;
; -15.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 25.656     ;
; -15.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.665     ;
; -15.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.665     ;
; -15.189 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.008      ; 25.652     ;
; -15.189 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.008      ; 25.652     ;
; -15.187 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 25.638     ;
; -15.187 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 25.638     ;
; -15.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.016      ; 25.657     ;
; -15.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.016      ; 25.657     ;
; -15.179 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 25.662     ;
; -15.179 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.028      ; 25.662     ;
; -15.176 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.645     ;
; -15.176 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.014      ; 25.645     ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                            ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -15.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 26.001     ;
; -15.544 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 26.001     ;
; -15.537 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 26.006     ;
; -15.537 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 26.006     ;
; -15.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.948     ;
; -15.498 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.948     ;
; -15.460 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.917     ;
; -15.460 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.917     ;
; -15.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.922     ;
; -15.453 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.922     ;
; -15.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.871     ;
; -15.419 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.871     ;
; -15.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.868     ;
; -15.416 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.868     ;
; -15.414 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.864     ;
; -15.414 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.864     ;
; -15.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.851     ;
; -15.385 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.851     ;
; -15.368 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.837     ;
; -15.368 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.837     ;
; -15.366 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.834     ;
; -15.366 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.834     ;
; -15.357 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 25.824     ;
; -15.357 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 25.824     ;
; -15.335 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.787     ;
; -15.335 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.787     ;
; -15.334 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.784     ;
; -15.334 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.784     ;
; -15.332 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.784     ;
; -15.332 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.784     ;
; -15.331 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.788     ;
; -15.331 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.788     ;
; -15.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.786     ;
; -15.329 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.786     ;
; -15.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.773     ;
; -15.315 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.773     ;
; -15.311 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 25.767     ;
; -15.311 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 25.767     ;
; -15.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.759     ;
; -15.302 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.759     ;
; -15.301 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.767     ;
; -15.301 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.767     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.015      ; 25.754     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.753     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.015      ; 25.754     ;
; -15.284 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.753     ;
; -15.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.750     ;
; -15.282 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.750     ;
; -15.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.749     ;
; -15.280 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.749     ;
; -15.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 25.740     ;
; -15.273 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 25.740     ;
; -15.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 25.722     ;
; -15.271 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 25.722     ;
; -15.260 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.729     ;
; -15.260 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.729     ;
; -15.259 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.717     ;
; -15.259 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.717     ;
; -15.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.700     ;
; -15.250 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.005     ; 25.700     ;
; -15.247 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.704     ;
; -15.247 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.704     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.711     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.702     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.711     ;
; -15.245 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.702     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.683     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.689     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 25.683     ;
; -15.231 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 25.689     ;
; -15.227 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 25.683     ;
; -15.227 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 25.683     ;
; -15.223 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.691     ;
; -15.223 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.691     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.689     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.688     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.689     ;
; -15.220 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 25.688     ;
; -15.218 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.675     ;
; -15.218 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.675     ;
; -15.207 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.673     ;
; -15.207 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 25.673     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.657     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.015      ; 25.670     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.657     ;
; -15.200 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.015      ; 25.670     ;
; -15.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.656     ;
; -15.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 25.656     ;
; -15.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.665     ;
; -15.196 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.665     ;
; -15.189 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.008      ; 25.652     ;
; -15.189 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.008      ; 25.652     ;
; -15.187 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 25.638     ;
; -15.187 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 25.638     ;
; -15.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.016      ; 25.657     ;
; -15.186 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.016      ; 25.657     ;
; -15.179 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 25.662     ;
; -15.179 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.028      ; 25.662     ;
; -15.176 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.645     ;
; -15.176 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.014      ; 25.645     ;
+---------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                               ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                   ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -13.239 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 34.077     ;
; -13.239 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 34.077     ;
; -13.166 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.993     ;
; -13.166 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.993     ;
; -13.063 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.901     ;
; -13.063 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.901     ;
; -12.990 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.817     ;
; -12.990 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.817     ;
; -12.930 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.768     ;
; -12.930 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.768     ;
; -12.884 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.736     ;
; -12.884 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.736     ;
; -12.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.684     ;
; -12.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.684     ;
; -12.849 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.718     ;
; -12.849 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.718     ;
; -12.816 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.654     ;
; -12.816 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.654     ;
; -12.752 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.590     ;
; -12.752 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.590     ;
; -12.743 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.570     ;
; -12.743 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.570     ;
; -12.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.556     ;
; -12.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.556     ;
; -12.708 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.560     ;
; -12.708 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.560     ;
; -12.701 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.539     ;
; -12.701 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.539     ;
; -12.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.506     ;
; -12.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.506     ;
; -12.673 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.542     ;
; -12.673 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.542     ;
; -12.672 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.510     ;
; -12.672 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.510     ;
; -12.630 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.482     ;
; -12.630 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.482     ;
; -12.623 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.461     ;
; -12.623 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.461     ;
; -12.599 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.426     ;
; -12.599 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.426     ;
; -12.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.427     ;
; -12.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.427     ;
; -12.554 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.392     ;
; -12.554 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.392     ;
; -12.550 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.377     ;
; -12.550 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.377     ;
; -12.542 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.380     ;
; -12.542 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.380     ;
; -12.540 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.409     ;
; -12.540 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.409     ;
; -12.536 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.374     ;
; -12.536 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.374     ;
; -12.525 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.363     ;
; -12.525 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.363     ;
; -12.481 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.308     ;
; -12.481 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.308     ;
; -12.461 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.313     ;
; -12.461 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.313     ;
; -12.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.306     ;
; -12.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.306     ;
; -12.433 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.271     ;
; -12.433 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.271     ;
; -12.428 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.266     ;
; -12.428 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.266     ;
; -12.426 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.295     ;
; -12.426 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.295     ;
; -12.409 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.247     ;
; -12.409 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.247     ;
; -12.397 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.249     ;
; -12.397 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.249     ;
; -12.392 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.230     ;
; -12.392 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.230     ;
; -12.362 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.231     ;
; -12.362 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.231     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.187     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.198     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.187     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.198     ;
; -12.355 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.182     ;
; -12.355 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.044     ; 33.182     ;
; -12.351 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.203     ;
; -12.351 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.203     ;
; -12.321 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.173     ;
; -12.321 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.173     ;
; -12.320 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.020     ; 33.171     ;
; -12.320 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.020     ; 33.171     ;
; -12.317 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.169     ;
; -12.317 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.169     ;
; -12.295 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.133     ;
; -12.295 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.133     ;
; -12.282 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.151     ;
; -12.282 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.151     ;
; -12.278 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.116     ;
; -12.278 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.116     ;
; -12.268 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.120     ;
; -12.268 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.019     ; 33.120     ;
; -12.257 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.095     ;
; -12.257 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.033     ; 33.095     ;
; -12.233 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.102     ;
; -12.233 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 20.833       ; -0.002     ; 33.102     ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                               ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                   ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -13.239 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 34.077     ;
; -13.239 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 34.077     ;
; -13.166 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.993     ;
; -13.166 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.993     ;
; -13.063 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.901     ;
; -13.063 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.901     ;
; -12.990 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.817     ;
; -12.990 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.817     ;
; -12.930 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.768     ;
; -12.930 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.768     ;
; -12.884 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.736     ;
; -12.884 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.736     ;
; -12.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.684     ;
; -12.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.684     ;
; -12.849 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.718     ;
; -12.849 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.718     ;
; -12.816 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.654     ;
; -12.816 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.654     ;
; -12.752 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.590     ;
; -12.752 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.590     ;
; -12.743 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.570     ;
; -12.743 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.570     ;
; -12.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.556     ;
; -12.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.556     ;
; -12.708 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.560     ;
; -12.708 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.560     ;
; -12.701 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.539     ;
; -12.701 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.539     ;
; -12.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.506     ;
; -12.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.506     ;
; -12.673 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.542     ;
; -12.673 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.542     ;
; -12.672 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.510     ;
; -12.672 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.510     ;
; -12.630 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.482     ;
; -12.630 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.482     ;
; -12.623 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.461     ;
; -12.623 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.461     ;
; -12.599 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.426     ;
; -12.599 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.426     ;
; -12.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.427     ;
; -12.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.427     ;
; -12.554 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.392     ;
; -12.554 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.392     ;
; -12.550 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.377     ;
; -12.550 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.377     ;
; -12.542 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.380     ;
; -12.542 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.380     ;
; -12.540 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.409     ;
; -12.540 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.409     ;
; -12.536 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.374     ;
; -12.536 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.374     ;
; -12.525 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.363     ;
; -12.525 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.363     ;
; -12.481 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.308     ;
; -12.481 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.308     ;
; -12.461 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.313     ;
; -12.461 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.313     ;
; -12.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.306     ;
; -12.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.306     ;
; -12.433 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.271     ;
; -12.433 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.271     ;
; -12.428 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.266     ;
; -12.428 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.266     ;
; -12.426 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.295     ;
; -12.426 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.295     ;
; -12.409 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.247     ;
; -12.409 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.247     ;
; -12.397 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.249     ;
; -12.397 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.249     ;
; -12.392 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.230     ;
; -12.392 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.230     ;
; -12.362 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.231     ;
; -12.362 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.231     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.187     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.198     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.187     ;
; -12.360 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.198     ;
; -12.355 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.182     ;
; -12.355 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.044     ; 33.182     ;
; -12.351 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.203     ;
; -12.351 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.203     ;
; -12.321 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.173     ;
; -12.321 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.173     ;
; -12.320 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.020     ; 33.171     ;
; -12.320 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.020     ; 33.171     ;
; -12.317 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.169     ;
; -12.317 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.169     ;
; -12.295 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.133     ;
; -12.295 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.133     ;
; -12.282 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.151     ;
; -12.282 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.151     ;
; -12.278 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.116     ;
; -12.278 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.116     ;
; -12.268 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.120     ;
; -12.268 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.019     ; 33.120     ;
; -12.257 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.095     ;
; -12.257 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.033     ; 33.095     ;
; -12.233 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.102     ;
; -12.233 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 20.833       ; -0.002     ; 33.102     ;
+---------+-----------------------------------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 23.014 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.414      ;
; 23.154 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.274      ;
; 23.197 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 2.231      ;
; 23.703 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.725      ;
; 23.746 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.682      ;
; 23.916 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.512      ;
; 24.046 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.382      ;
; 24.134 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.294      ;
; 24.178 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 1.250      ;
; 24.697 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.731      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[23]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[20]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.595 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.187      ; 10.330     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[179] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[178] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[177] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[176] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[175] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[174] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[173] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.724 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[172] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 10.196     ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[67]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.988 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[63]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.182      ; 9.932      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[86]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[85]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[84]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[81]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[78]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[77]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[76]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 30.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.926      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[167] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.016 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.891      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[102] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[97]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[96]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.018 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[87]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.893      ;
; 31.096 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[215] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.173      ; 9.815      ;
; 31.166 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[207] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.169      ; 9.741      ;
; 31.188 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[234] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.183      ; 9.733      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[171] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[170] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[169] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[168] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[62]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[61]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[60]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[15]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.215 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.179      ; 9.702      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[152] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[151] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[145] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[144] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
; 31.279 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[143] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.166      ; 9.625      ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.203 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.897      ;
; 38.369 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
; 38.369 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.731      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 55.840 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.037     ; 6.661      ;
; 55.987 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.037     ; 6.514      ;
; 56.506 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.037     ; 5.995      ;
; 56.737 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.037     ; 5.764      ;
; 56.839 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.037     ; 5.662      ;
; 59.677 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.861      ;
; 59.677 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.861      ;
; 59.677 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.861      ;
; 59.677 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.861      ;
; 59.677 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.861      ;
; 59.824 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.714      ;
; 59.824 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.714      ;
; 59.824 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.714      ;
; 59.824 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.714      ;
; 59.824 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.714      ;
; 59.985 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.553      ;
; 60.132 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.406      ;
; 60.343 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.195      ;
; 60.343 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.195      ;
; 60.343 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.195      ;
; 60.343 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.195      ;
; 60.343 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.195      ;
; 60.574 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.964      ;
; 60.574 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.964      ;
; 60.574 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.964      ;
; 60.574 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.964      ;
; 60.574 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.964      ;
; 60.651 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.887      ;
; 60.676 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.862      ;
; 60.676 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.862      ;
; 60.676 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.862      ;
; 60.676 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.862      ;
; 60.676 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.862      ;
; 60.882 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.656      ;
; 60.984 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.554      ;
; 61.486 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.052      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 60.574 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.965      ;
; 60.578 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.961      ;
; 60.771 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.768      ;
; 60.903 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.001      ; 1.636      ;
; 60.988 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.550      ;
; 61.256 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.282      ;
; 61.259 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.279      ;
; 61.285 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.253      ;
; 61.611 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.927      ;
; 61.611 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.927      ;
; 61.614 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.924      ;
; 61.614 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.924      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                              ; To Node                                                                                                                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.278 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[179]                                                                          ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.346      ; 0.910      ;
; 0.280 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[180]                                                                          ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.346      ; 0.912      ;
; 0.365 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                          ; A4299:I_4299|BUFFER_IN[219]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.264      ; 0.915      ;
; 0.445 ; A4299:I_4299|INT                                                                                                       ; A4299:I_4299|INT                                                                                                                                          ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; A4299:I_4299|SYNC                                                                                                      ; A4299:I_4299|SYNC                                                                                                                                         ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.731      ;
; 0.456 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[178]                                                                          ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.314      ; 1.056      ;
; 0.461 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]                                                                          ; A4299:I_4299|BUFFER_IN[230]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.306      ; 1.053      ;
; 0.465 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]                                                                          ; A4299:I_4299|BUFFER_IN[231]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.306      ; 1.057      ;
; 0.518 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|BUFFER_IN[222]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.264      ; 1.068      ;
; 0.535 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[161]                                                                          ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.094      ; 0.915      ;
; 0.536 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|BUFFER_IN[244]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.094      ; 0.916      ;
; 0.537 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                          ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.094      ; 0.917      ;
; 0.539 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[162]                                                                          ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.094      ; 0.919      ;
; 0.541 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[171]                                                                          ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.272      ; 1.099      ;
; 0.544 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.165      ;
; 0.544 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.165      ;
; 0.546 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.167      ;
; 0.552 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.173      ;
; 0.560 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.275      ; 1.121      ;
; 0.560 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.181      ;
; 0.561 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]                                                                          ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.630      ; 1.477      ;
; 0.561 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.182      ;
; 0.561 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.371      ; 1.182      ;
; 0.580 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.165      ;
; 0.580 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.165      ;
; 0.582 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.167      ;
; 0.588 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.173      ;
; 0.596 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.181      ;
; 0.597 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.182      ;
; 0.597 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.335      ; 1.182      ;
; 0.615 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[105]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[106]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.901      ;
; 0.616 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[24]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.902      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[35]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.617 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.903      ;
; 0.619 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.619 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[193]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.905      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[214]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[215]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.906      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                                                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[167]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.621 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[33]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.907      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[175]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.908      ;
; 0.622 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[205]                                                                          ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.001      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[34]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[35]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.623 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.909      ;
; 0.624 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[161]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[162]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.910      ;
; 0.624 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]                                                                          ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.002     ; 0.908      ;
; 0.625 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[245]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[246]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.625 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[228]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.911      ;
; 0.626 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[252]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[253]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.912      ;
; 0.626 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.912      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.002     ; 0.911      ;
; 0.627 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[170]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.913      ;
; 0.628 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[188]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.914      ;
; 0.628 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[179]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[180]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.914      ;
; 0.629 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[231]                                                                          ; A4299:I_4299|BUFFER_IN[232]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.001      ; 0.916      ;
; 0.629 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[244]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.915      ;
; 0.629 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.915      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[236]                                                                          ; A4299:I_4299|BUFFER_IN[237]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.002     ; 0.914      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[240]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[241]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
; 0.630 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.916      ;
; 0.631 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.917      ;
; 0.631 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.917      ;
; 0.632 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.918      ;
; 0.632 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.918      ;
; 0.632 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[219]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.918      ;
; 0.632 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.918      ;
; 0.632 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.918      ;
; 0.633 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[253]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[254]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.919      ;
; 0.634 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[217]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.920      ;
; 0.635 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[196]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.921      ;
; 0.636 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[223]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.922      ;
; 0.643 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[201]                                                                          ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; -0.001     ; 0.928      ;
; 0.646 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[198]                                                                          ; A4299:I_4299|BUFFER_IN[199]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.314      ; 1.246      ;
; 0.654 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.628      ; 1.568      ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                        ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                           ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                    ; \SLOW_CPU:TMP[1]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                    ; \SLOW_CPU:TMP[0]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                    ; \SLOW_CPU:TMP[2]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; SYNCn                                                                               ; SYNCn                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; VMA_68K30Ln                                                                         ; VMA_68K30Ln                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                        ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                           ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[1]                                                                    ; \SLOW_CPU:TMP[1]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[0]                                                                    ; \SLOW_CPU:TMP[0]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \SLOW_CPU:TMP[2]                                                                    ; \SLOW_CPU:TMP[2]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; SYNCn                                                                               ; SYNCn                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; VMA_68K30Ln                                                                         ; VMA_68K30Ln                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_1           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_RD_SRC_2           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2           ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_SRC_2           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.593 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.034      ; 0.915      ;
; 0.594 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.034      ; 0.916      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][6]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][6]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][10]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.906      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.593 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.034      ; 0.915      ;
; 0.594 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.034      ; 0.916      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.616 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.902      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.618 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.904      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][6]                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][6]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[2][10]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_REG[1][10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
; 0.620 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[2]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.906      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.731      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.731      ;
; 0.611 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.897      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.964 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.250      ;
; 1.008 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.294      ;
; 1.096 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.382      ;
; 1.226 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.512      ;
; 1.396 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.682      ;
; 1.439 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 1.725      ;
; 1.945 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.231      ;
; 1.988 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.274      ;
; 2.128 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 2.414      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.638 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.924      ;
; 0.638 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.924      ;
; 0.641 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.927      ;
; 0.641 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.927      ;
; 0.967 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.253      ;
; 0.993 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.279      ;
; 0.996 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.282      ;
; 1.264 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.550      ;
; 1.349 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.636      ;
; 1.481 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.768      ;
; 1.674 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.961      ;
; 1.678 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.001      ; 1.965      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.620 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.906      ;
; 0.766 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.052      ;
; 0.980 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.266      ;
; 0.980 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.266      ;
; 0.985 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.271      ;
; 0.986 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.272      ;
; 1.268 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.554      ;
; 1.370 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.656      ;
; 1.412 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.698      ;
; 1.412 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.698      ;
; 1.447 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.733      ;
; 1.448 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.734      ;
; 1.492 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.778      ;
; 1.492 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.778      ;
; 1.527 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.813      ;
; 1.572 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.858      ;
; 1.576 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.862      ;
; 1.576 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.862      ;
; 1.601 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.887      ;
; 1.607 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.893      ;
; 1.652 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.938      ;
; 1.678 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.964      ;
; 1.678 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.964      ;
; 1.678 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.964      ;
; 1.909 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.195      ;
; 1.909 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.195      ;
; 1.909 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.195      ;
; 1.909 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.195      ;
; 2.120 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.406      ;
; 2.267 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.553      ;
; 2.575 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.861      ;
; 5.413 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.037     ; 5.662      ;
; 5.515 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.037     ; 5.764      ;
; 5.746 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.037     ; 5.995      ;
; 6.265 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.037     ; 6.514      ;
; 6.412 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.037     ; 6.661      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                              ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 10.006     ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                              ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.016      ; 10.025     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.001     ; 10.008     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.006      ; 10.015     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.008      ; 10.017     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 10.004     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.013      ; 10.022     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 10.005     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
; 21.279 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 10.006     ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[14]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.021      ; 10.028     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.016      ; 10.023     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[8]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[8]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.021      ; 10.028     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][5]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][9]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.024      ; 10.031     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 10.033     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.036      ; 10.043     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][9]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.024      ; 10.031     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 10.035     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 10.030     ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                               ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.278 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.007      ; 10.017     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][12]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][13]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.280 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[15]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[14]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[4]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[5]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.021      ; 10.028     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][15]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.016      ; 10.023     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[9]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[8]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[8]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[7]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[6]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.021      ; 10.028     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[1][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[0][14]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[3]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][5]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[2]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[1]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[11]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][9]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.024      ; 10.031     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 10.024     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 10.018     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 10.033     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.036      ; 10.043     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][9]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.018      ; 10.025     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.024      ; 10.031     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 10.034     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][4]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 10.035     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 10.030     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 10.039     ;
; 21.281 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 10.030     ;
+--------+------------------------------------------------+------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 78.638 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.501      ; 3.223      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                      ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 2.574      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.041      ; 5.409      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.033      ; 5.401      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.041      ; 5.409      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.033      ; 5.401      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.034      ; 5.402      ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                      ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.274 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.004      ; 2.564      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 2.275 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 2.574      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.041      ; 5.409      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.033      ; 5.401      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.040      ; 5.408      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.041      ; 5.409      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.037      ; 5.405      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.038      ; 5.406      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.032      ; 5.400      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.033      ; 5.401      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.036      ; 5.404      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
; 5.082 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.034      ; 5.402      ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 2.472 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.501      ; 3.223      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 3.154      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.002      ; 3.398      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.676      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 3.682      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 3.737      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.009      ; 4.028      ;
; 3.736 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 4.032      ;
; 3.736 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 4.032      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 4.050      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 2.858 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 3.154      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.110 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.002      ; 3.398      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.676      ;
; 3.389 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.676      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.397 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 3.682      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.434 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 3.737      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.733 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.009      ; 4.028      ;
; 3.736 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 4.032      ;
; 3.736 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 4.032      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
; 3.747 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 4.050      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 7.852 ; 10.416       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.584 ; 12.695       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.584 ; 12.695       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.136 ; 40.700       ; 2.564          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.136 ; 40.700       ; 2.564          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.589 ; 40.700       ; 1.111          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.939  ; 0.939  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 10.048 ; 10.048 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.390  ; 0.390  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 12.086 ; 12.086 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 30.620 ; 30.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.191  ; 7.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 12.705 ; 12.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.081  ; 7.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 9.111  ; 9.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.487  ; 9.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 9.338  ; 9.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.447  ; 9.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 10.385 ; 10.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.943 ; 18.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.597 ; 19.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 21.774 ; 21.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 22.256 ; 22.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 23.796 ; 23.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 17.388 ; 17.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 16.751 ; 16.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.250 ; 16.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.606 ; 16.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 18.119 ; 18.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.555 ; 15.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.643 ; 16.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 17.139 ; 17.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.408 ; 17.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 17.985 ; 17.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.930 ; 17.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 18.277 ; 18.277 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 17.774 ; 17.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 16.764 ; 16.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 12.427 ; 12.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 11.607 ; 11.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.757  ; 8.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 29.746 ; 29.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 30.045 ; 30.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.736 ; 13.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 11.292 ; 11.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 16.983 ; 16.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 10.193 ; 10.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 21.471 ; 21.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 21.910 ; 21.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 28.679 ; 28.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 21.129 ; 21.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.922 ; 16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.657 ; 17.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.929 ; 17.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 18.294 ; 18.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.178 ; 18.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 19.713 ; 19.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.145 ; 19.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 6.244  ; 6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 4.992  ; 4.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 5.116  ; 5.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 4.954  ; 4.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 4.497  ; 4.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.861 ; 18.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.677 ; 19.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.667 ; 18.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 19.300 ; 19.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 20.176 ; 20.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 20.904 ; 20.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 20.980 ; 20.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 20.113 ; 20.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 20.357 ; 20.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 20.842 ; 20.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 19.523 ; 19.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.977 ; 20.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 29.173 ; 29.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.664  ; 8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 9.557  ; 9.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.262  ; 9.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.062  ; 9.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.542  ; 9.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.091  ; 9.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 9.406  ; 9.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.470 ; 11.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 11.599 ; 11.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 11.714 ; 11.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.685  ; 9.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.850 ; 14.850 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 6.940  ; 6.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 14.006 ; 14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 27.043 ; 27.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 7.696  ; 7.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 10.163 ; 10.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.921  ; 8.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.611  ; 8.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 10.680 ; 10.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 9.526  ; 9.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 29.405 ; 29.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 9.688  ; 9.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.618  ; 8.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 28.121 ; 28.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 8.832  ; 8.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.627  ; 8.627  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 6.855  ; 6.855  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.539 ; 18.539 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.139 ; 19.139 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 19.239 ; 19.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 20.574 ; 20.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 20.676 ; 20.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 23.545 ; 23.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 15.808 ; 15.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 15.171 ; 15.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.241 ; 15.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.610 ; 16.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 18.011 ; 18.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.323 ; 16.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 14.915 ; 14.915 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.335 ; 16.335 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.783 ; 16.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 16.206 ; 16.206 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.433 ; 16.433 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.526 ; 17.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.451 ; 17.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.534 ; 16.534 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.286 ; 15.286 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 9.892  ; 9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 9.382  ; 9.382  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 16.277 ; 16.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 3.026  ; 3.026  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 4.113  ; 4.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 3.520  ; 3.520  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 27.494 ; 27.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 27.793 ; 27.793 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.593  ; 7.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.993 ; 19.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.398  ; 8.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 26.180 ; 26.180 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 19.927 ; 19.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 15.720 ; 15.720 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.199 ; 17.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.525 ; 17.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.699 ; 17.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.700 ; 16.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.683 ; 17.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.108 ; 18.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 17.852 ; 17.852 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 20.804 ; 20.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.569 ; 19.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.265 ; 18.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.660 ; 18.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 20.548 ; 20.548 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.778 ; 19.778 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.561 ; 18.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 19.953 ; 19.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 20.016 ; 20.016 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 18.283 ; 18.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 19.079 ; 19.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 18.442 ; 18.442 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 19.256 ; 19.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 26.921 ; 26.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 7.502  ; 7.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 7.412  ; 7.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 26.906 ; 26.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 30.620 ; 30.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.191  ; 7.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 12.705 ; 12.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.081  ; 7.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.111  ; 9.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.487  ; 9.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 9.338  ; 9.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.447  ; 9.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 10.385 ; 10.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.943 ; 18.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.597 ; 19.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 21.774 ; 21.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 22.256 ; 22.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 23.796 ; 23.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 17.388 ; 17.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 16.751 ; 16.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.250 ; 16.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.606 ; 16.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 18.119 ; 18.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.555 ; 15.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.643 ; 16.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.139 ; 17.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.408 ; 17.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 17.985 ; 17.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.930 ; 17.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 18.277 ; 18.277 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.774 ; 17.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.764 ; 16.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 12.427 ; 12.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 11.607 ; 11.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.757  ; 8.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 29.746 ; 29.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 30.045 ; 30.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.736 ; 13.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 11.292 ; 11.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 16.983 ; 16.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 10.193 ; 10.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 21.471 ; 21.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 21.910 ; 21.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 28.679 ; 28.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 21.129 ; 21.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.922 ; 16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.657 ; 17.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.929 ; 17.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 18.294 ; 18.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.178 ; 18.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 19.713 ; 19.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.145 ; 19.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 6.244  ; 6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.992  ; 4.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 5.116  ; 5.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 4.497  ; 4.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.861 ; 18.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.677 ; 19.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.667 ; 18.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 19.300 ; 19.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 20.176 ; 20.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.904 ; 20.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 20.980 ; 20.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 20.113 ; 20.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 20.357 ; 20.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 20.842 ; 20.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 19.523 ; 19.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.977 ; 20.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 29.173 ; 29.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.664  ; 8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 9.557  ; 9.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.262  ; 9.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.062  ; 9.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.542  ; 9.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.091  ; 9.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 9.406  ; 9.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.470 ; 11.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 11.599 ; 11.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 11.714 ; 11.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.685  ; 9.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.850 ; 14.850 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 6.940  ; 6.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 14.006 ; 14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 27.043 ; 27.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 7.696  ; 7.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 10.163 ; 10.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.921  ; 8.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.611  ; 8.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 10.680 ; 10.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 9.526  ; 9.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 29.405 ; 29.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 9.688  ; 9.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.618  ; 8.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 28.121 ; 28.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 8.832  ; 8.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.627  ; 8.627  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 6.855  ; 6.855  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.539 ; 18.539 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.139 ; 19.139 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 19.239 ; 19.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 20.574 ; 20.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 20.676 ; 20.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 23.545 ; 23.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 15.808 ; 15.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 15.171 ; 15.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.241 ; 15.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.610 ; 16.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 18.011 ; 18.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.323 ; 16.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.915 ; 14.915 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.335 ; 16.335 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.783 ; 16.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.206 ; 16.206 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.433 ; 16.433 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.526 ; 17.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.451 ; 17.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.534 ; 16.534 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.286 ; 15.286 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.892  ; 9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 9.382  ; 9.382  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 16.277 ; 16.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 3.026  ; 3.026  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 4.113  ; 4.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 3.520  ; 3.520  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 27.494 ; 27.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 27.793 ; 27.793 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.593  ; 7.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.993 ; 19.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.398  ; 8.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.180 ; 26.180 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 19.927 ; 19.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 15.720 ; 15.720 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.199 ; 17.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.525 ; 17.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.699 ; 17.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.700 ; 16.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.683 ; 17.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.108 ; 18.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 17.852 ; 17.852 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 20.804 ; 20.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.569 ; 19.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.265 ; 18.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.660 ; 18.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.778 ; 19.778 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.561 ; 18.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 19.953 ; 19.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 20.016 ; 20.016 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 18.283 ; 18.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 19.079 ; 19.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 18.442 ; 18.442 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 19.256 ; 19.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.921 ; 26.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 7.502  ; 7.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 7.412  ; 7.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 26.906 ; 26.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 26.078 ; 26.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 16.281 ; 16.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 17.464 ; 17.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 15.897 ; 15.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.531 ; 18.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.633 ; 18.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 12.126 ; 12.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 21.357 ; 21.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.765 ; 13.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.128 ; 13.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 14.235 ; 14.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 14.464 ; 14.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 15.663 ; 15.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 14.886 ; 14.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 13.101 ; 13.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 14.740 ; 14.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 14.531 ; 14.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 9.383  ; 9.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 25.677 ; 25.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 25.976 ; 25.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 17.627 ; 17.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.066 ; 18.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 24.137 ; 24.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 14.045 ; 14.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.524 ; 15.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.266 ; 15.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.351 ; 15.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 13.720 ; 13.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.505 ; 15.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.065 ; 16.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.129 ; 19.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.221 ; 17.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.828 ; 16.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.690 ; 17.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 18.505 ; 18.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.103 ; 18.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 14.260 ; 14.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.165 ; 14.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.307 ; 15.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 15.706 ; 15.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.063 ; 15.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 22.920 ; 22.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.863 ; 24.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 15.245 ; 15.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 14.651 ; 14.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 14.677 ; 14.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 13.067 ; 13.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.796 ; 14.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 26.078 ; 26.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.281 ; 16.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 17.464 ; 17.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.897 ; 15.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.531 ; 18.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.633 ; 18.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 21.357 ; 21.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.765 ; 13.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.128 ; 13.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.235 ; 14.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.464 ; 14.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.663 ; 15.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.886 ; 14.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.101 ; 13.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.740 ; 14.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 14.531 ; 14.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 9.383  ; 9.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.677 ; 25.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.976 ; 25.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 17.627 ; 17.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.066 ; 18.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.137 ; 24.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 14.045 ; 14.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.524 ; 15.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.266 ; 15.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.351 ; 15.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 13.720 ; 13.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.505 ; 15.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.065 ; 16.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.129 ; 19.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.221 ; 17.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.828 ; 16.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.690 ; 17.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 18.505 ; 18.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.103 ; 18.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 14.260 ; 14.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.165 ; 14.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.307 ; 15.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 15.706 ; 15.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.063 ; 15.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.920 ; 22.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.863 ; 24.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 15.245 ; 15.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.651 ; 14.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.677 ; 14.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.067 ; 13.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.796 ; 14.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 26.646 ; 26.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 16.547 ; 16.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 17.647 ; 17.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 17.800 ; 17.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 21.540 ; 21.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.843 ; 13.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.206 ; 13.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 14.075 ; 14.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 14.730 ; 14.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 15.589 ; 15.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 13.207 ; 13.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 13.778 ; 13.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 14.951 ; 14.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 14.560 ; 14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.453  ; 8.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 25.860 ; 25.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 26.159 ; 26.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 18.700 ; 18.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 19.139 ; 19.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 24.705 ; 24.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 17.740 ; 17.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.707 ; 15.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 16.076 ; 16.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.300 ; 16.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 16.240 ; 16.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.027 ; 16.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.686 ; 16.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.312 ; 19.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.147 ; 17.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 14.872 ; 14.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.952 ; 16.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.534 ; 17.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 18.467 ; 18.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.350 ; 17.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.079 ; 17.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.114 ; 17.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 17.125 ; 17.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 16.585 ; 16.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.003 ; 17.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 17.936 ; 17.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 25.287 ; 25.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 23.069 ; 23.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 25.431 ; 25.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 26.646 ; 26.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.547 ; 16.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 17.647 ; 17.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.800 ; 17.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 21.540 ; 21.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.843 ; 13.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.206 ; 13.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.075 ; 14.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.730 ; 14.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.589 ; 15.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.207 ; 13.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 13.778 ; 13.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.951 ; 14.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.560 ; 14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.453  ; 8.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.860 ; 25.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.159 ; 26.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.700 ; 18.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 19.139 ; 19.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.705 ; 24.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.740 ; 17.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.707 ; 15.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 16.076 ; 16.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.300 ; 16.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 16.240 ; 16.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.027 ; 16.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.686 ; 16.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.312 ; 19.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.147 ; 17.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 14.872 ; 14.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.952 ; 16.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.534 ; 17.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 18.467 ; 18.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.350 ; 17.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.079 ; 17.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.114 ; 17.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 17.125 ; 17.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 16.585 ; 16.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.003 ; 17.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 17.936 ; 17.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.287 ; 25.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.069 ; 23.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 25.431 ; 25.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                   ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.560  ; -0.560  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -8.906  ; -8.906  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; -0.142  ; -0.142  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -10.478 ; -10.478 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -6.672  ; -6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -6.943  ; -6.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -6.191  ; -6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -6.833  ; -6.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -6.222  ; -6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.635  ; -6.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.308  ; -6.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -6.428  ; -6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.294  ; -6.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.362  ; -6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -6.222  ; -6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -6.968  ; -6.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -6.786  ; -6.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.771  ; -6.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.831  ; -6.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -6.387  ; -6.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -8.293  ; -8.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -9.784  ; -9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -9.784  ; -9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -10.501 ; -10.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -16.252 ; -16.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -10.168 ; -10.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -5.633  ; -5.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.996  ; -4.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -9.153  ; -9.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -9.266  ; -9.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -8.591  ; -8.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -7.578  ; -7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -9.762  ; -9.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -9.576  ; -9.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -8.514  ; -8.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -8.163  ; -8.163  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -8.878  ; -8.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -7.942  ; -7.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -8.378  ; -8.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -7.964  ; -7.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -7.845  ; -7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -7.968  ; -7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -7.723  ; -7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -8.509  ; -8.509  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -6.888  ; -6.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -9.390  ; -9.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -9.846  ; -9.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -9.390  ; -9.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -9.689  ; -9.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -7.784  ; -7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -2.620  ; -2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -8.562  ; -8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -9.115  ; -9.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -6.816  ; -6.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -7.345  ; -7.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -10.133 ; -10.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -7.786  ; -7.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -10.572 ; -10.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -7.381  ; -7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -6.841  ; -6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.910  ; -7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.686 ; -12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -12.686 ; -12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.895 ; -13.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -14.341 ; -14.341 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.135 ; -14.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -16.661 ; -16.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -13.108 ; -13.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -15.009 ; -15.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.466 ; -14.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -5.996  ; -5.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -3.738  ; -3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -3.226  ; -3.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -3.862  ; -3.862  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -3.700  ; -3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -3.358  ; -3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -7.226  ; -7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -8.683  ; -8.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.226  ; -7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.435  ; -8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.735  ; -7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.924  ; -7.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.990  ; -7.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -9.771  ; -9.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.608  ; -7.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -8.031  ; -8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -8.727  ; -8.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -8.005  ; -8.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.719  ; -7.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -8.119  ; -8.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -8.246  ; -8.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.289  ; -7.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.541  ; -7.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -3.643  ; -3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -8.149  ; -8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -8.421  ; -8.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -6.838  ; -6.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -6.128  ; -6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -6.261  ; -6.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -6.132  ; -6.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -6.128  ; -6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -6.151  ; -6.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -6.499  ; -6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -6.476  ; -6.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -6.736  ; -6.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -6.505  ; -6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -6.912  ; -6.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -6.545  ; -6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -6.862  ; -6.862  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -7.337  ; -7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -6.902  ; -6.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -8.126  ; -8.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -6.686  ; -6.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -8.474  ; -8.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -8.212  ; -8.212  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -9.910  ; -9.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -7.114  ; -7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -7.114  ; -7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -7.196  ; -7.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -7.270  ; -7.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -7.373  ; -7.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -7.802  ; -7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -10.427 ; -10.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -9.226  ; -9.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -7.009  ; -7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -9.440  ; -9.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -7.494  ; -7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -11.514 ; -11.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -6.555  ; -6.555  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -8.584  ; -8.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -8.379  ; -8.379  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -6.607  ; -6.607  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -15.612 ; -15.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -15.284 ; -15.284 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -16.552 ; -16.552 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -9.834  ; -9.834  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -17.109 ; -17.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -17.211 ; -17.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -17.225 ; -17.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -9.834  ; -9.834  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -12.343 ; -12.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -11.706 ; -11.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -7.177  ; -7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -10.067 ; -10.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -8.312  ; -8.312  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -7.710  ; -7.710  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -8.418  ; -8.418  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -10.618 ; -10.618 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -10.546 ; -10.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -9.644  ; -9.644  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -9.210  ; -9.210  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -9.335  ; -9.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -7.787  ; -7.787  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -8.596  ; -8.596  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -8.169  ; -8.169  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -8.283  ; -8.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -7.864  ; -7.864  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -8.313  ; -8.313  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -7.177  ; -7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -7.273  ; -7.273  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -2.775  ; -2.775  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -3.036  ; -3.036  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -3.076  ; -3.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -11.052 ; -11.052 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -11.052 ; -11.052 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -11.078 ; -11.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -11.383 ; -11.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -7.764  ; -7.764  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -7.345  ; -7.345  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -17.985 ; -17.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -8.150  ; -8.150  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -18.424 ; -18.424 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -9.803  ; -9.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -17.466 ; -17.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -13.600 ; -13.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -13.600 ; -13.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.740 ; -13.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -14.597 ; -14.597 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.848 ; -14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -17.382 ; -17.382 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -14.078 ; -14.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -15.599 ; -15.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.643 ; -14.643 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -16.357 ; -16.357 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -16.412 ; -16.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -18.340 ; -18.340 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -18.847 ; -18.847 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -17.106 ; -17.106 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -16.606 ; -16.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -17.204 ; -17.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -18.345 ; -18.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -17.083 ; -17.083 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -17.861 ; -17.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -16.543 ; -16.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -17.618 ; -17.618 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -17.396 ; -17.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -16.357 ; -16.357 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -17.215 ; -17.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -16.863 ; -16.863 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -17.051 ; -17.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -7.848  ; -7.848  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -12.430 ; -12.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -7.254  ; -7.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -7.164  ; -7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -12.091 ; -12.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -6.672  ; -6.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -6.943  ; -6.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -6.191  ; -6.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -6.833  ; -6.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -6.222  ; -6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.635  ; -6.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.308  ; -6.308  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.428  ; -6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.294  ; -6.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.362  ; -6.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -6.222  ; -6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -6.968  ; -6.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -6.786  ; -6.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.771  ; -6.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.831  ; -6.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.387  ; -6.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -8.293  ; -8.293  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -9.784  ; -9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -9.784  ; -9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -10.501 ; -10.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -16.252 ; -16.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -10.168 ; -10.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -5.633  ; -5.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.996  ; -4.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -9.153  ; -9.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.266  ; -9.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -8.591  ; -8.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -7.578  ; -7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -9.762  ; -9.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.576  ; -9.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -8.514  ; -8.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.163  ; -8.163  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -8.878  ; -8.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -7.942  ; -7.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -8.378  ; -8.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -7.964  ; -7.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -7.845  ; -7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -7.968  ; -7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.723  ; -7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -8.509  ; -8.509  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -6.888  ; -6.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -9.390  ; -9.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -9.846  ; -9.846  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.390  ; -9.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -9.689  ; -9.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -7.784  ; -7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -2.620  ; -2.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -8.562  ; -8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -9.115  ; -9.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -6.816  ; -6.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -7.345  ; -7.345  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -10.133 ; -10.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -7.786  ; -7.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -10.572 ; -10.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -7.381  ; -7.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -6.841  ; -6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.910  ; -7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.686 ; -12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -12.686 ; -12.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.895 ; -13.895 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -14.341 ; -14.341 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.135 ; -14.135 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -16.661 ; -16.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -13.108 ; -13.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -15.009 ; -15.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.466 ; -14.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -5.996  ; -5.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -3.738  ; -3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -3.226  ; -3.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -3.862  ; -3.862  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -3.700  ; -3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -3.358  ; -3.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -7.226  ; -7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -8.683  ; -8.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.226  ; -7.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.435  ; -8.435  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.735  ; -7.735  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.924  ; -7.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.990  ; -7.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -9.771  ; -9.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.608  ; -7.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -8.031  ; -8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -8.727  ; -8.727  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -8.005  ; -8.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.719  ; -7.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -8.119  ; -8.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -8.246  ; -8.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.289  ; -7.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.541  ; -7.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -3.643  ; -3.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -8.149  ; -8.149  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -6.928  ; -6.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -8.421  ; -8.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -6.838  ; -6.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -6.128  ; -6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -6.261  ; -6.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -6.132  ; -6.132  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -6.128  ; -6.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -6.151  ; -6.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -6.499  ; -6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -6.476  ; -6.476  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -6.736  ; -6.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -6.505  ; -6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -6.912  ; -6.912  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -6.545  ; -6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -6.862  ; -6.862  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -7.337  ; -7.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -6.902  ; -6.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -8.126  ; -8.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -6.686  ; -6.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -8.474  ; -8.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -8.212  ; -8.212  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -7.444  ; -7.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -9.910  ; -9.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -7.114  ; -7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -7.114  ; -7.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -7.196  ; -7.196  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -7.270  ; -7.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -7.373  ; -7.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -7.802  ; -7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -10.427 ; -10.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -9.226  ; -9.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -7.009  ; -7.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -9.440  ; -9.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -7.494  ; -7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -11.514 ; -11.514 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -6.555  ; -6.555  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -8.584  ; -8.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -8.379  ; -8.379  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -6.607  ; -6.607  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -15.612 ; -15.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -15.284 ; -15.284 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -16.552 ; -16.552 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -9.834  ; -9.834  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -17.109 ; -17.109 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -17.211 ; -17.211 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -17.225 ; -17.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -9.834  ; -9.834  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -12.343 ; -12.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -11.706 ; -11.706 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.177  ; -7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -10.067 ; -10.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -8.312  ; -8.312  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -7.710  ; -7.710  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.418  ; -8.418  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -10.618 ; -10.618 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -10.546 ; -10.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.644  ; -9.644  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -9.210  ; -9.210  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.335  ; -9.335  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -7.787  ; -7.787  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -8.596  ; -8.596  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -8.169  ; -8.169  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -8.283  ; -8.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -7.864  ; -7.864  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -8.313  ; -8.313  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -7.177  ; -7.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -7.273  ; -7.273  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -2.775  ; -2.775  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -3.036  ; -3.036  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -3.076  ; -3.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -11.052 ; -11.052 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -11.052 ; -11.052 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -11.078 ; -11.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -11.383 ; -11.383 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -7.764  ; -7.764  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -7.345  ; -7.345  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -17.985 ; -17.985 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -8.150  ; -8.150  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -18.424 ; -18.424 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -9.803  ; -9.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -17.466 ; -17.466 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -13.600 ; -13.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -13.600 ; -13.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.740 ; -13.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -14.597 ; -14.597 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.848 ; -14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -17.382 ; -17.382 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -14.078 ; -14.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -15.599 ; -15.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.643 ; -14.643 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -16.357 ; -16.357 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -16.412 ; -16.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -18.340 ; -18.340 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -18.847 ; -18.847 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -17.106 ; -17.106 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -16.606 ; -16.606 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -17.204 ; -17.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -18.345 ; -18.345 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -17.083 ; -17.083 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -17.861 ; -17.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -16.543 ; -16.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -17.618 ; -17.618 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -17.396 ; -17.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -16.357 ; -16.357 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -17.215 ; -17.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -16.863 ; -16.863 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -17.051 ; -17.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -7.848  ; -7.848  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -12.430 ; -12.430 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -7.254  ; -7.254  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -7.164  ; -7.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -12.091 ; -12.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -7.654  ; -7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -14.882 ; -14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -15.644 ; -15.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -14.973 ; -14.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -9.485  ; -9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -9.485  ; -9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -10.139 ; -10.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -10.321 ; -10.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -12.769 ; -12.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -9.800  ; -9.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -6.784  ; -6.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -6.146  ; -6.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -7.041  ; -7.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -9.037  ; -9.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -8.202  ; -8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -8.117  ; -8.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -7.577  ; -7.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -9.252  ; -9.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -8.490  ; -8.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -8.065  ; -8.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -7.041  ; -7.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -9.329  ; -9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -8.355  ; -8.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -9.911  ; -9.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -10.364 ; -10.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -9.911  ; -9.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -10.209 ; -10.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -15.929 ; -15.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -16.368 ; -16.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -8.828  ; -8.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -16.436 ; -16.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.022 ; -12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -12.570 ; -12.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.704 ; -13.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.867 ; -13.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.134 ; -14.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -16.151 ; -16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -12.022 ; -12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -14.581 ; -14.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.217 ; -14.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.876  ; -6.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.443  ; -7.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -6.876  ; -6.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.339  ; -7.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.219  ; -7.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.804  ; -7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.980  ; -7.980  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.434  ; -7.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.323  ; -7.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.614  ; -7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.016  ; -7.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.295  ; -7.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.183  ; -7.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.404  ; -7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.090  ; -7.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -6.963  ; -6.963  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -6.418  ; -6.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -11.444 ; -11.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -11.018 ; -11.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -10.147 ; -10.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -17.074 ; -17.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -17.074 ; -17.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -12.759 ; -12.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -12.759 ; -12.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -12.785 ; -12.785 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -13.090 ; -13.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -10.153 ; -10.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -11.366 ; -11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -7.654  ; -7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -14.882 ; -14.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -15.644 ; -15.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -14.973 ; -14.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -9.485  ; -9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -9.485  ; -9.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -10.139 ; -10.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -10.321 ; -10.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -12.769 ; -12.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -9.800  ; -9.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -6.784  ; -6.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -6.146  ; -6.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.041  ; -7.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -9.037  ; -9.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -8.202  ; -8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -8.117  ; -8.117  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -7.577  ; -7.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -9.252  ; -9.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -8.490  ; -8.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -8.065  ; -8.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -7.041  ; -7.041  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -9.329  ; -9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -8.355  ; -8.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -9.911  ; -9.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -10.364 ; -10.364 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.911  ; -9.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -10.209 ; -10.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -15.929 ; -15.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -16.368 ; -16.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -8.828  ; -8.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -16.436 ; -16.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.022 ; -12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -12.570 ; -12.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.704 ; -13.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.867 ; -13.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.134 ; -14.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -16.151 ; -16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -12.022 ; -12.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -14.581 ; -14.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.217 ; -14.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.876  ; -6.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.443  ; -7.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -6.876  ; -6.876  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.339  ; -7.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.219  ; -7.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.804  ; -7.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.980  ; -7.980  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.434  ; -7.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.323  ; -7.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.614  ; -7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.016  ; -7.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.295  ; -7.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.183  ; -7.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.404  ; -7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.090  ; -7.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -6.963  ; -6.963  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -6.418  ; -6.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.444 ; -11.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -11.018 ; -11.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -10.147 ; -10.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -17.074 ; -17.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -17.074 ; -17.074 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -12.759 ; -12.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -12.759 ; -12.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -12.785 ; -12.785 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -13.090 ; -13.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -10.153 ; -10.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.366 ; -11.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -7.152  ; -7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -14.943 ; -14.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -14.352 ; -14.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -15.493 ; -15.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -15.166 ; -15.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.820 ; -16.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -16.922 ; -16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -16.409 ; -16.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -15.166 ; -15.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -12.054 ; -12.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -11.417 ; -11.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -6.273  ; -6.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -10.093 ; -10.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -9.957  ; -9.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -9.534  ; -9.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -8.472  ; -8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -8.636  ; -8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -10.046 ; -10.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -8.585  ; -8.585  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -8.603  ; -8.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -7.986  ; -7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -6.855  ; -6.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -7.335  ; -7.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -7.066  ; -7.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -6.698  ; -6.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -6.584  ; -6.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -7.062  ; -7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -6.273  ; -6.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -10.863 ; -10.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -11.252 ; -11.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -10.863 ; -10.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -11.831 ; -11.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -16.849 ; -16.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -17.288 ; -17.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -11.053 ; -11.053 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -16.661 ; -16.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -7.376  ; -7.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -12.454 ; -12.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -12.808 ; -12.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.929 ; -13.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -7.720  ; -7.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.376  ; -7.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -7.491  ; -7.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.382  ; -7.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -13.811 ; -13.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -14.624 ; -14.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -16.438 ; -16.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -19.064 ; -19.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -19.534 ; -19.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -16.899 ; -16.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -14.624 ; -14.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -16.704 ; -16.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -17.286 ; -17.286 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -18.219 ; -18.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -16.512 ; -16.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -15.611 ; -15.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -16.357 ; -16.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -16.293 ; -16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -14.772 ; -14.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -15.935 ; -15.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -15.612 ; -15.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -16.147 ; -16.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -7.029  ; -7.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -11.683 ; -11.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -11.187 ; -11.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -7.152  ; -7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -14.943 ; -14.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -14.352 ; -14.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -15.493 ; -15.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -15.166 ; -15.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.820 ; -16.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -16.922 ; -16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -16.409 ; -16.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -15.166 ; -15.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -12.054 ; -12.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -11.417 ; -11.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -6.273  ; -6.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -10.093 ; -10.093 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.957  ; -9.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.534  ; -9.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.472  ; -8.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -8.636  ; -8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -10.046 ; -10.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -8.585  ; -8.585  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.603  ; -8.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -7.986  ; -7.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -6.855  ; -6.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -7.335  ; -7.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -7.066  ; -7.066  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -6.698  ; -6.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -6.584  ; -6.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.062  ; -7.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -6.273  ; -6.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.863 ; -10.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -11.252 ; -11.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -10.863 ; -10.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -11.831 ; -11.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -16.849 ; -16.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -17.288 ; -17.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -11.053 ; -11.053 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -16.661 ; -16.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -7.376  ; -7.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -12.454 ; -12.454 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -12.808 ; -12.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.929 ; -13.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -7.720  ; -7.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.376  ; -7.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -7.491  ; -7.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.382  ; -7.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -13.811 ; -13.811 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -14.624 ; -14.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -16.438 ; -16.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -19.064 ; -19.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -19.534 ; -19.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -16.899 ; -16.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -14.624 ; -14.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -16.704 ; -16.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -17.286 ; -17.286 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -18.219 ; -18.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -16.512 ; -16.512 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -15.611 ; -15.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -16.357 ; -16.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -16.293 ; -16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -14.772 ; -14.772 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -15.935 ; -15.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -15.612 ; -15.612 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -16.147 ; -16.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -7.029  ; -7.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.683 ; -11.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -11.187 ; -11.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 17.960 ; 17.960 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 19.332 ; 19.332 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 17.245 ; 17.245 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 28.915 ; 28.915 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 26.517 ; 26.517 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 26.851 ; 26.851 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 22.159 ; 22.159 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 26.602 ; 26.602 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 28.818 ; 28.818 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 28.915 ; 28.915 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 28.599 ; 28.599 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 21.778 ; 21.778 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 26.541 ; 26.541 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 24.161 ; 24.161 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 24.398 ; 24.398 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 22.966 ; 22.966 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 23.681 ; 23.681 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 23.422 ; 23.422 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 23.275 ; 23.275 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 23.027 ; 23.027 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 23.632 ; 23.632 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 25.957 ; 25.957 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 25.386 ; 25.386 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 25.569 ; 25.569 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 25.144 ; 25.144 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 24.382 ; 24.382 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 24.379 ; 24.379 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 26.541 ; 26.541 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 25.907 ; 25.907 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 7.237  ; 7.237  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 28.185 ; 28.185 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 26.248 ; 26.248 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 25.831 ; 25.831 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.549 ; 25.549 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 25.635 ; 25.635 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.315 ; 26.315 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.291 ; 25.291 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 26.613 ; 26.613 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 27.350 ; 27.350 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 28.185 ; 28.185 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 27.173 ; 27.173 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 25.916 ; 25.916 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.970 ; 25.970 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 25.794 ; 25.794 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.093 ; 25.093 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 26.548 ; 26.548 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.160 ; 26.160 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.209 ; 13.209 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.234  ; 7.234  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.374  ; 7.374  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.837 ; 22.837 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.234 ; 20.234 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 22.837 ; 22.837 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 23.952 ; 23.952 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 23.952 ; 23.952 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 23.090 ; 23.090 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 21.559 ; 21.559 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 18.837 ; 18.837 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 20.763 ; 20.763 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 19.000 ; 19.000 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 19.117 ; 19.117 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 18.080 ; 18.080 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 19.146 ; 19.146 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 17.941 ; 17.941 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 18.746 ; 18.746 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 20.179 ; 20.179 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 20.498 ; 20.498 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 20.351 ; 20.351 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 20.178 ; 20.178 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 21.473 ; 21.473 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 21.559 ; 21.559 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 21.522 ; 21.522 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 21.363 ; 21.363 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 22.885 ; 22.885 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 20.924 ; 20.924 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 22.196 ; 22.196 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 21.583 ; 21.583 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.071 ; 21.071 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 20.973 ; 20.973 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 21.162 ; 21.162 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 21.527 ; 21.527 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.464 ; 22.464 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 22.407 ; 22.407 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 22.285 ; 22.285 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 20.698 ; 20.698 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 21.004 ; 21.004 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 22.885 ; 22.885 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 22.273 ; 22.273 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 21.529 ; 21.529 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 21.616 ; 21.616 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.031 ; 13.031 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.460 ; 20.460 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.031 ; 13.031 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.460 ; 20.460 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 35.030 ; 35.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 36.402 ; 36.402 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 19.599 ; 19.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.151 ; 19.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 19.321 ; 19.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 21.575 ; 21.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.986 ; 19.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 19.875 ; 19.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 19.625 ; 19.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 18.840 ; 18.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 18.957 ; 18.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 19.675 ; 19.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 18.709 ; 18.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 20.276 ; 20.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 20.690 ; 20.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 21.103 ; 21.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 21.165 ; 21.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 20.964 ; 20.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 20.749 ; 20.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 20.436 ; 20.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 21.613 ; 21.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 21.758 ; 21.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 21.219 ; 21.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 11.448 ; 11.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.109  ; 7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 7.600  ; 7.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 34.315 ; 34.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 43.587 ; 43.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 43.921 ; 43.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 39.229 ; 39.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 43.672 ; 43.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 45.888 ; 45.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 45.669 ; 45.669 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 38.848 ; 38.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 38.659 ; 38.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 39.090 ; 39.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 38.707 ; 38.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 38.618 ; 38.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 37.581 ; 37.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 38.498 ; 38.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 38.503 ; 38.503 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 37.977 ; 37.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 39.989 ; 39.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 39.809 ; 39.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 41.044 ; 41.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 40.130 ; 40.130 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 39.804 ; 39.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 40.376 ; 40.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 40.552 ; 40.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 9.165  ; 9.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 10.616 ; 10.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 21.732 ; 21.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 21.608 ; 21.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 20.873 ; 20.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 27.922 ; 27.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 28.477 ; 28.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 13.877 ; 13.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 28.488 ; 28.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 27.524 ; 27.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 28.153 ; 28.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 27.768 ; 27.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 27.522 ; 27.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 28.949 ; 28.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 30.672 ; 30.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 29.247 ; 29.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 29.399 ; 29.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 30.235 ; 30.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 10.624 ; 10.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.203  ; 9.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 8.717  ; 8.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 18.993 ; 18.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.715  ; 8.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.971  ; 7.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.725  ; 8.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 9.088  ; 9.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 8.053  ; 8.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 23.991 ; 23.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 25.046 ; 25.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 25.899 ; 25.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 27.749 ; 27.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 27.475 ; 27.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.186 ; 25.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 26.054 ; 26.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 23.945 ; 23.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 26.864 ; 26.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 25.107 ; 25.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 25.339 ; 25.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 28.144 ; 28.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 31.748 ; 31.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 30.492 ; 30.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 40.746 ; 40.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 40.523 ; 40.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 41.290 ; 41.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 40.572 ; 40.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 40.474 ; 40.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 40.514 ; 40.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 42.089 ; 42.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 41.695 ; 41.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 41.596 ; 41.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 41.391 ; 41.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 40.956 ; 40.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 41.216 ; 41.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 41.090 ; 41.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 41.315 ; 41.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 40.805 ; 40.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 30.803 ; 30.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 31.059 ; 31.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 31.045 ; 31.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 30.596 ; 30.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 31.780 ; 31.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 31.623 ; 31.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 13.001 ; 13.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 26.327 ; 26.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 26.421 ; 26.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 26.092 ; 26.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 27.267 ; 27.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 25.526 ; 25.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 9.489  ; 9.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.356  ; 8.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.059  ; 7.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.982  ; 7.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 7.586  ; 7.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 8.669  ; 8.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.594  ; 8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.611 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 9.812  ; 9.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 8.073  ; 8.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 8.125  ; 8.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 7.904  ; 7.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 19.298 ; 19.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 15.825 ; 15.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 15.928 ; 15.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 22.138 ; 22.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 23.510 ; 23.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 16.764 ; 16.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 21.423 ; 20.673 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 30.695 ; 30.695 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 31.029 ; 31.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 26.337 ; 26.337 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 30.780 ; 30.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 32.996 ; 32.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 32.777 ; 32.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 25.956 ; 25.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 25.657 ; 25.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 25.815 ; 25.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 25.726 ; 25.726 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 24.738 ; 24.775 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 25.692 ; 25.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 25.611 ; 25.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 24.914 ; 25.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 27.097 ; 27.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 27.003 ; 26.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 28.152 ; 28.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 27.238 ; 27.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 26.912 ; 26.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 27.484 ; 27.484 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 27.740 ; 27.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 14.457 ; 14.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 15.012 ; 15.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 15.596 ; 15.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 14.632 ; 14.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 15.261 ; 15.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 14.876 ; 14.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 14.630 ; 14.626 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 16.057 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 17.780 ; 17.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 16.355 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 15.757 ; 16.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 16.593 ; 17.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 11.518 ; 11.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 17.852 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 12.041 ; 12.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 12.891 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.282 ; 13.282 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.217 ; 13.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 15.025 ; 15.025 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 15.145 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.604 ; 12.604 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.568 ; 12.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 17.852 ; 14.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 14.319 ; 11.441 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.923 ; 15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 13.789 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 28.217 ; 28.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 27.631 ; 27.631 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 28.398 ; 28.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.680 ; 27.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 27.631 ; 27.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 27.708 ; 27.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 29.197 ; 29.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 28.632 ; 28.889 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 28.790 ; 28.649 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 28.064 ; 28.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 28.324 ; 28.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 28.198 ; 28.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.506 ; 28.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 27.993 ; 27.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 16.978 ; 14.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 17.234 ; 14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 14.342 ; 17.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 13.893 ; 16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 17.955 ; 15.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 14.920 ; 17.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 13.338 ; 9.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 12.293 ; 13.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 13.698 ; 14.133 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 12.951 ; 13.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 12.660 ; 12.558 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 13.557 ; 13.027 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 12.057 ; 12.634 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 11.821 ; 11.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 35.030 ; 35.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 36.402 ; 36.402 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 19.599 ; 19.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.151 ; 19.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 19.321 ; 19.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 21.575 ; 21.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.986 ; 19.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 19.875 ; 19.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 19.625 ; 19.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 18.840 ; 18.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 18.957 ; 18.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 19.675 ; 19.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 18.709 ; 18.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 20.276 ; 20.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 20.690 ; 20.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 21.103 ; 21.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 21.165 ; 21.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 20.964 ; 20.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 20.749 ; 20.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 20.436 ; 20.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 21.613 ; 21.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 21.758 ; 21.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 21.219 ; 21.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.448 ; 11.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.109  ; 7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 7.600  ; 7.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 34.315 ; 34.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 43.587 ; 43.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 43.921 ; 43.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 39.229 ; 39.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 43.672 ; 43.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 45.888 ; 45.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 45.669 ; 45.669 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 38.848 ; 38.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 38.659 ; 38.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 39.090 ; 39.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 38.707 ; 38.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 38.618 ; 38.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 37.581 ; 37.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 38.498 ; 38.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 38.503 ; 38.503 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 37.977 ; 37.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 39.989 ; 39.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 39.809 ; 39.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 41.044 ; 41.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 40.130 ; 40.130 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 39.804 ; 39.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 40.376 ; 40.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 40.552 ; 40.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 9.165  ; 9.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 10.616 ; 10.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 21.732 ; 21.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 21.608 ; 21.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 20.873 ; 20.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 27.922 ; 27.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 28.477 ; 28.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 13.877 ; 13.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 28.488 ; 28.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 27.524 ; 27.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 28.153 ; 28.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 27.768 ; 27.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 27.522 ; 27.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 28.949 ; 28.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 30.672 ; 30.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 29.247 ; 29.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 29.399 ; 29.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 30.235 ; 30.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 10.624 ; 10.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.203  ; 9.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 8.717  ; 8.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 18.993 ; 18.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.715  ; 8.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.971  ; 7.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.725  ; 8.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 9.088  ; 9.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 8.053  ; 8.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 23.991 ; 23.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 25.046 ; 25.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 25.899 ; 25.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 27.749 ; 27.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 27.475 ; 27.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.186 ; 25.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 26.054 ; 26.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 23.945 ; 23.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 26.864 ; 26.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 25.107 ; 25.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 25.339 ; 25.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 28.144 ; 28.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 31.748 ; 31.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 30.492 ; 30.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 40.746 ; 40.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 40.523 ; 40.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 41.290 ; 41.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 40.572 ; 40.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 40.474 ; 40.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 40.514 ; 40.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 42.089 ; 42.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 41.695 ; 41.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 41.596 ; 41.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 41.391 ; 41.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 40.956 ; 40.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 41.216 ; 41.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 41.090 ; 41.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 41.315 ; 41.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 40.805 ; 40.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 30.803 ; 30.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 31.059 ; 31.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 31.045 ; 31.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 30.596 ; 30.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 31.780 ; 31.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 31.623 ; 31.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 13.001 ; 13.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 26.327 ; 26.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 26.421 ; 26.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 26.092 ; 26.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 27.267 ; 27.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 25.526 ; 25.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.489  ; 9.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.356  ; 8.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.059  ; 7.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 7.586  ; 7.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 8.669  ; 8.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.594  ; 8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.611 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 9.812  ; 9.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 8.073  ; 8.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 8.125  ; 8.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 7.904  ; 7.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 19.298 ; 19.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 15.825 ; 15.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 15.928 ; 15.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 22.138 ; 22.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 23.510 ; 23.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 16.764 ; 16.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 21.423 ; 20.673 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 30.695 ; 30.695 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 31.029 ; 31.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 26.337 ; 26.337 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 30.780 ; 30.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 32.996 ; 32.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 32.777 ; 32.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 25.956 ; 25.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 25.657 ; 25.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 25.815 ; 25.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 25.726 ; 25.726 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 24.738 ; 24.775 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 25.692 ; 25.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 25.611 ; 25.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 24.914 ; 25.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 27.097 ; 27.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 27.003 ; 26.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 28.152 ; 28.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 27.238 ; 27.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 26.912 ; 26.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 27.484 ; 27.484 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 27.740 ; 27.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 14.457 ; 14.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 15.012 ; 15.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 15.596 ; 15.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 14.632 ; 14.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 15.261 ; 15.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 14.876 ; 14.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 14.630 ; 14.626 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 16.057 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 17.780 ; 17.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 16.355 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 15.757 ; 16.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 16.593 ; 17.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.518 ; 11.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 17.852 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 12.041 ; 12.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 12.891 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.282 ; 13.282 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.217 ; 13.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 15.025 ; 15.025 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 15.145 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.604 ; 12.604 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.568 ; 12.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 17.852 ; 14.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 14.319 ; 11.441 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.923 ; 15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 13.789 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 28.217 ; 28.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 27.631 ; 27.631 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 28.398 ; 28.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 27.680 ; 27.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 27.631 ; 27.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 27.708 ; 27.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 29.197 ; 29.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 28.632 ; 28.889 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 28.790 ; 28.649 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 28.064 ; 28.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 28.324 ; 28.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 28.198 ; 28.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 28.506 ; 28.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 27.993 ; 27.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 16.978 ; 14.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 17.234 ; 14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 14.342 ; 17.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 13.893 ; 16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 17.955 ; 15.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 14.920 ; 17.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 13.338 ; 9.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 12.293 ; 13.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 13.698 ; 14.133 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 12.951 ; 13.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 12.660 ; 12.558 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 13.557 ; 13.027 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 12.057 ; 12.634 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.821 ; 11.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 14.859 ; 14.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 23.416 ; 23.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 23.750 ; 23.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 19.058 ; 19.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 23.501 ; 23.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 25.717 ; 25.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 25.498 ; 25.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.677 ; 18.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 8.017  ; 8.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 8.899  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 7.953  ; 7.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 16.178 ; 16.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 8.128  ; 8.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 8.633  ; 8.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 21.060 ; 21.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 21.297 ; 21.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 19.865 ; 19.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 20.580 ; 20.580 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 20.321 ; 20.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 20.174 ; 20.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 19.926 ; 19.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 20.531 ; 20.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 22.856 ; 22.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 22.285 ; 22.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 22.468 ; 22.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 22.043 ; 22.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 21.281 ; 21.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 21.278 ; 21.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 22.806 ; 22.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 9.023  ; 9.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 9.617  ; 9.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 8.579  ; 8.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.618 ; 13.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.886 ; 13.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.309 ; 13.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.797 ; 13.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 13.418 ; 13.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.002 ; 13.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 15.065 ; 15.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 12.834 ; 12.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 24.963 ; 24.963 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.020 ; 25.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.431 ; 23.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 24.598 ; 24.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.176 ; 25.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 24.927 ; 24.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 24.249 ; 24.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 24.552 ; 24.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.478 ; 23.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 23.996 ; 23.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 23.306 ; 23.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 24.401 ; 24.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.447 ; 23.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 23.438 ; 23.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 13.708 ; 13.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 13.964 ; 13.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 13.948 ; 13.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 13.499 ; 13.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 13.071 ; 13.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.916 ; 12.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 12.255 ; 12.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 11.384 ; 11.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.015 ; 10.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 11.172 ; 11.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 9.919  ; 9.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 14.859 ; 14.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 23.416 ; 23.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 23.750 ; 23.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 19.058 ; 19.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 23.501 ; 23.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 25.717 ; 25.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 25.498 ; 25.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.677 ; 18.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 8.017  ; 8.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 8.899  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 7.953  ; 7.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 16.178 ; 16.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 8.128  ; 8.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 8.633  ; 8.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 21.060 ; 21.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 21.297 ; 21.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 19.865 ; 19.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 20.580 ; 20.580 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 20.321 ; 20.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 20.174 ; 20.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 19.926 ; 19.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 20.531 ; 20.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 22.856 ; 22.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 22.285 ; 22.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 22.468 ; 22.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 22.043 ; 22.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 21.281 ; 21.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 21.278 ; 21.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 22.806 ; 22.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 9.023  ; 9.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 9.617  ; 9.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 8.579  ; 8.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.618 ; 13.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.886 ; 13.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.309 ; 13.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.797 ; 13.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 13.418 ; 13.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.002 ; 13.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 15.065 ; 15.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 12.834 ; 12.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 25.020 ; 25.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.431 ; 23.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 24.598 ; 24.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 25.176 ; 25.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 24.927 ; 24.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 24.249 ; 24.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 24.552 ; 24.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 23.478 ; 23.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 23.996 ; 23.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 23.306 ; 23.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 24.401 ; 24.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.447 ; 23.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 23.438 ; 23.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 13.708 ; 13.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 13.964 ; 13.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 13.948 ; 13.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 13.499 ; 13.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 13.071 ; 13.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.916 ; 12.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.255 ; 12.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 11.384 ; 11.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.015 ; 10.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 11.172 ; 11.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.919  ; 9.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 31.216 ; 31.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.517 ; 31.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 29.973 ; 29.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 31.037 ; 31.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 30.837 ; 30.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 31.452 ; 31.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 30.416 ; 30.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 30.391 ; 30.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 31.794 ; 31.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 31.977 ; 31.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 32.606 ; 32.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 32.079 ; 32.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 32.448 ; 32.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 30.068 ; 30.068 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 29.069 ; 29.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 12.280 ; 12.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 11.463 ; 11.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 33.303 ; 33.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.950 ; 32.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 32.556 ; 32.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 32.991 ; 32.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 33.730 ; 33.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.468 ; 33.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 34.002 ; 34.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 34.109 ; 34.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 34.022 ; 34.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 33.764 ; 33.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 33.432 ; 33.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 33.491 ; 33.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 33.162 ; 33.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 30.075 ; 30.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 29.322 ; 29.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 31.216 ; 31.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.517 ; 31.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 29.973 ; 29.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 31.037 ; 31.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 30.837 ; 30.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 31.452 ; 31.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 30.416 ; 30.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 30.391 ; 30.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 31.794 ; 31.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 31.977 ; 31.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 32.606 ; 32.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 32.079 ; 32.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 32.448 ; 32.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 30.068 ; 30.068 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 29.069 ; 29.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 12.280 ; 12.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 11.463 ; 11.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 33.303 ; 33.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.950 ; 32.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 32.556 ; 32.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 32.991 ; 32.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 33.730 ; 33.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.468 ; 33.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 34.002 ; 34.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 34.109 ; 34.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 34.022 ; 34.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 33.764 ; 33.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 33.432 ; 33.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 33.491 ; 33.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 33.162 ; 33.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 30.075 ; 30.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 29.322 ; 29.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 16.012 ; 16.012 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 17.384 ; 17.384 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 17.245 ; 17.245 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 16.932 ; 16.932 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 18.912 ; 18.912 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 19.301 ; 19.301 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 17.394 ; 17.394 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 18.936 ; 18.936 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 17.791 ; 17.791 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 18.421 ; 18.421 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 18.365 ; 18.365 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 16.932 ; 16.932 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 17.448 ; 17.448 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 18.037 ; 18.037 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 18.905 ; 18.905 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 17.519 ; 17.519 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 18.677 ; 18.677 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 17.791 ; 17.791 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 18.023 ; 18.023 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 17.448 ; 17.448 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 17.983 ; 17.983 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 19.410 ; 19.410 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 19.432 ; 19.432 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 19.974 ; 19.974 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 19.974 ; 19.974 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 18.748 ; 18.748 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 19.189 ; 19.189 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 20.070 ; 20.070 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 19.493 ; 19.493 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 7.237  ; 7.237  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.746 ; 19.746 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.124 ; 20.124 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 20.338 ; 20.338 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 20.102 ; 20.102 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 20.631 ; 20.631 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 20.684 ; 20.684 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 20.039 ; 20.039 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 21.034 ; 21.034 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 21.701 ; 21.701 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 21.638 ; 21.638 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 21.219 ; 21.219 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 20.321 ; 20.321 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 20.800 ; 20.800 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.160 ; 20.160 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 19.903 ; 19.903 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.077 ; 20.077 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 19.746 ; 19.746 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.209 ; 13.209 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.234  ; 7.234  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.374  ; 7.374  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 20.234 ; 20.234 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.234 ; 20.234 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 22.837 ; 22.837 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 23.090 ; 23.090 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 23.952 ; 23.952 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 23.090 ; 23.090 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 15.073 ; 15.073 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 15.247 ; 15.247 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 16.565 ; 16.565 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 15.636 ; 15.636 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 15.863 ; 15.863 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 15.708 ; 15.708 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 16.485 ; 16.485 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 15.073 ; 15.073 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 16.012 ; 16.012 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 17.389 ; 17.389 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 16.201 ; 16.201 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 17.884 ; 17.884 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 17.733 ; 17.733 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 16.351 ; 16.351 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 17.479 ; 17.479 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 18.609 ; 18.609 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 16.912 ; 16.912 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 17.165 ; 17.165 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 17.334 ; 17.334 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 17.998 ; 17.998 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 18.219 ; 18.219 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 17.817 ; 17.817 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 18.601 ; 18.601 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 18.501 ; 18.501 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 18.659 ; 18.659 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 19.730 ; 19.730 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 19.617 ; 19.617 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 17.988 ; 17.988 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 18.231 ; 18.231 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 18.559 ; 18.559 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 17.763 ; 17.763 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 18.193 ; 18.193 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 18.616 ; 18.616 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 17.165 ; 17.165 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.875 ; 11.875 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.687 ; 12.687 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.875 ; 11.875 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.157 ; 12.157 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.875 ; 11.875 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.687 ; 12.687 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.875 ; 11.875 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.157 ; 12.157 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 9.452  ; 9.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 5.853  ; 5.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 8.962  ; 8.962  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 8.959  ; 8.959  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 9.319  ; 9.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 8.868  ; 8.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 8.552  ; 8.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 8.067  ; 8.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 8.199  ; 8.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 7.792  ; 7.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 7.771  ; 7.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 7.916  ; 7.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 6.188  ; 6.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 6.581  ; 6.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 6.826  ; 6.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 7.012  ; 7.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 5.853  ; 5.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 7.407  ; 7.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 7.255  ; 7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 7.940  ; 7.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 9.732  ; 9.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 9.437  ; 9.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 6.926  ; 6.926  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 6.168  ; 6.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 6.254  ; 6.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.343 ; 11.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 10.045 ; 10.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 7.039  ; 7.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 8.133  ; 8.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 8.627  ; 8.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 9.391  ; 9.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 9.392  ; 9.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 7.859  ; 7.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 6.608  ; 6.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 8.808  ; 8.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 8.021  ; 8.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.910  ; 7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.286  ; 7.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.672  ; 7.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.574  ; 7.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.794  ; 6.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.456  ; 6.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.166  ; 6.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 5.923  ; 5.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.773  ; 6.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 6.459  ; 6.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.594  ; 6.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 8.871  ; 8.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 10.157 ; 10.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 7.824  ; 7.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 8.441  ; 8.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 7.757  ; 7.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 6.160  ; 6.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.713  ; 6.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 5.844  ; 5.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 7.331  ; 7.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 6.350  ; 6.350  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 11.727 ; 11.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 9.778  ; 9.778  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 12.891 ; 12.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 12.506 ; 12.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 12.260 ; 11.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 13.687 ; 13.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 12.530 ; 12.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 10.935 ; 11.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.735 ; 11.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 9.601  ; 9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 9.689  ; 9.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 8.067  ; 8.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 7.936  ; 7.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 7.684  ; 7.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 7.737  ; 7.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.171  ; 7.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.944  ; 6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.483  ; 7.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.236  ; 8.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 6.082  ; 6.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 7.373  ; 7.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 12.665 ; 12.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 12.440 ; 12.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 12.882 ; 12.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.561 ; 12.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.485 ; 12.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.080 ; 13.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.907 ; 14.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.493 ; 13.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 9.948  ; 9.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.325 ; 12.237 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 9.948  ; 9.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 13.632 ; 13.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 12.377 ; 12.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.541  ; 9.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.664 ; 12.664 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.820 ; 12.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.855 ; 12.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.594 ; 12.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.237 ; 12.237 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.888 ; 12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.283 ; 12.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.686 ; 13.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.880 ; 13.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.256 ; 11.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.082 ; 11.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.412 ; 12.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 11.910 ; 12.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.541  ; 9.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.958  ; 9.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.687 ; 12.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 12.943 ; 12.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 12.481 ; 12.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 13.665 ; 13.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 13.508 ; 13.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 11.065 ; 11.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 9.054  ; 8.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 11.217 ; 10.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 9.743  ; 11.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 11.270 ; 9.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 9.301  ; 9.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 10.403 ; 11.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 10.375 ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 7.228  ; 7.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 6.284  ; 6.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 6.733  ; 6.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 5.748  ; 5.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.074  ; 5.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.541  ; 5.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.415  ; 5.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 5.270  ; 5.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 5.074  ; 5.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 5.758  ; 5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 5.499  ; 5.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 5.879  ; 5.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.198  ; 6.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 8.403  ; 8.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 7.122  ; 7.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 7.931  ; 7.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 6.565  ; 6.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 8.206  ; 8.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.479  ; 9.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 9.348  ; 9.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 7.594  ; 7.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 7.499  ; 7.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 7.579  ; 7.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.724  ; 7.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 7.499  ; 7.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 8.040  ; 8.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 7.956  ; 7.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 7.968  ; 7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 7.527  ; 7.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 13.331 ; 13.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 14.703 ; 14.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 7.755  ; 7.755  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 14.012 ; 11.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 14.564 ; 15.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 14.251 ; 14.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 16.231 ; 16.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 16.620 ; 16.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 14.792 ; 14.713 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 16.255 ; 16.255 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 15.110 ; 15.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.740 ; 15.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 15.684 ; 15.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 14.251 ; 14.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 10.977 ; 11.724 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 12.164 ; 11.724 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 13.744 ; 12.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 12.331 ; 12.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 12.913 ; 12.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 13.614 ; 11.933 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 13.133 ; 12.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 11.849 ; 12.104 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 10.977 ; 11.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 14.734 ; 13.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 14.948 ; 13.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 13.283 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 13.203 ; 14.106 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 13.961 ; 14.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 13.244 ; 14.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 12.990 ; 12.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 12.762 ; 12.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 12.198 ; 10.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 12.753 ; 11.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 11.323 ; 11.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 10.073 ; 12.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 12.505 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 12.120 ; 12.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 11.874 ; 12.260 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 13.301 ; 13.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 12.742 ; 12.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 11.583 ; 10.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.087 ; 11.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 9.578  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.098  ; 8.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 11.981 ; 11.981 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 11.981 ; 11.981 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 12.665 ; 12.665 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 12.440 ; 12.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 12.882 ; 12.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 12.102 ; 12.102 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 14.901 ; 14.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.561 ; 12.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.485 ; 12.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.362 ; 12.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 11.829 ; 10.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 13.183 ; 10.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 11.829 ; 10.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 15.433 ; 14.190 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 12.935 ; 14.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.575 ; 11.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.664 ; 12.664 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.937 ; 12.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.551 ; 12.551 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 13.146 ; 13.146 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.443 ; 12.443 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.888 ; 12.888 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.283 ; 12.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 13.179 ; 12.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 13.316 ; 12.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.749 ; 11.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.575 ; 11.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.280 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.591 ; 11.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.494 ; 11.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.929 ; 12.303 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 14.488 ; 13.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 14.744 ; 13.501 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 13.488 ; 14.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 13.039 ; 14.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 15.465 ; 14.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 14.066 ; 15.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 8.736  ; 9.054  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 10.853 ; 11.380 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 11.439 ; 9.743  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 9.694  ; 11.270 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 9.401  ; 9.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 11.298 ; 10.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 8.798  ; 10.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 8.400  ; 9.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 9.452  ; 9.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 5.853  ; 5.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 8.962  ; 8.962  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 8.959  ; 8.959  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 9.319  ; 9.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 8.868  ; 8.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 8.552  ; 8.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 8.067  ; 8.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 8.199  ; 8.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 7.792  ; 7.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 7.771  ; 7.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 7.916  ; 7.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 6.188  ; 6.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 6.581  ; 6.581  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 6.505  ; 6.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 6.826  ; 6.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 7.012  ; 7.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 5.853  ; 5.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 7.407  ; 7.407  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 7.255  ; 7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 7.940  ; 7.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 9.732  ; 9.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 9.437  ; 9.437  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 9.180  ; 9.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.926  ; 6.926  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.168  ; 6.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.254  ; 6.254  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.343 ; 11.831 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 10.045 ; 10.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.039  ; 7.039  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 8.133  ; 8.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 8.627  ; 8.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 9.391  ; 9.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 9.392  ; 9.392  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.859  ; 7.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 6.608  ; 6.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 8.808  ; 8.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 8.021  ; 8.021  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.910  ; 7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.286  ; 7.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.672  ; 7.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.181  ; 7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.574  ; 7.574  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.794  ; 6.794  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.456  ; 6.456  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.166  ; 6.166  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.916  ; 5.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.923  ; 5.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.275  ; 6.275  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.773  ; 6.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.459  ; 6.459  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.594  ; 6.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 8.871  ; 8.871  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 10.157 ; 10.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 7.824  ; 7.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 8.441  ; 8.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 7.583  ; 7.583  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 7.757  ; 7.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 6.160  ; 6.160  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.713  ; 6.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 5.844  ; 5.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 7.331  ; 7.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 6.350  ; 6.350  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 11.727 ; 11.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 9.778  ; 9.778  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 12.891 ; 12.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 12.506 ; 12.120 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 12.260 ; 11.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 13.687 ; 13.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 12.530 ; 12.605 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 10.935 ; 11.583 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.735 ; 11.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 9.601  ; 9.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 9.689  ; 9.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 8.067  ; 8.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 6.448  ; 6.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 7.936  ; 7.936  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 7.684  ; 7.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 7.737  ; 7.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.171  ; 7.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.944  ; 6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.483  ; 7.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.236  ; 8.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 6.082  ; 6.082  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 7.373  ; 7.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 11.981 ; 11.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 12.665 ; 12.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 12.440 ; 12.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 12.882 ; 12.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 11.807 ; 11.807 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.561 ; 12.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.485 ; 12.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.080 ; 13.898 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.907 ; 14.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.493 ; 13.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 9.948  ; 9.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.325 ; 12.237 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 9.948  ; 9.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 13.632 ; 13.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 12.377 ; 12.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.541  ; 9.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.664 ; 12.664 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.820 ; 12.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.855 ; 12.855 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.594 ; 12.594 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.237 ; 12.237 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.888 ; 12.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.283 ; 12.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.686 ; 13.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.880 ; 13.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.256 ; 11.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.082 ; 11.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.412 ; 12.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 11.910 ; 12.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.541  ; 9.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.958  ; 9.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.687 ; 12.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 12.943 ; 12.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 12.481 ; 12.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 13.665 ; 13.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 13.508 ; 13.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 11.065 ; 11.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 9.054  ; 8.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 11.217 ; 10.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 9.743  ; 11.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 11.270 ; 9.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.301  ; 9.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 10.403 ; 11.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.375 ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 7.228  ; 7.228  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 6.284  ; 6.284  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 6.733  ; 6.733  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 5.748  ; 5.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.074  ; 5.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.541  ; 5.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.415  ; 5.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 5.270  ; 5.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 5.074  ; 5.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 5.758  ; 5.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 6.102  ; 6.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 5.499  ; 5.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 5.879  ; 5.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.198  ; 6.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 8.403  ; 8.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 7.122  ; 7.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 7.931  ; 7.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 6.565  ; 6.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 8.206  ; 8.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.479  ; 9.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 9.348  ; 9.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 7.594  ; 7.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 7.499  ; 7.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 7.579  ; 7.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.724  ; 7.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 7.499  ; 7.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.040  ; 8.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 7.956  ; 7.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 7.968  ; 7.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 7.527  ; 7.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 13.331 ; 13.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 14.703 ; 14.703 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 7.755  ; 7.755  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 14.012 ; 11.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.564 ; 15.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 14.251 ; 14.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 16.231 ; 16.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 16.620 ; 16.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 14.792 ; 14.713 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 16.255 ; 16.255 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 15.110 ; 15.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.740 ; 15.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 15.684 ; 15.684 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 14.251 ; 14.251 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 10.977 ; 11.724 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 12.164 ; 11.724 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 13.744 ; 12.647 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 12.331 ; 12.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 12.913 ; 12.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.614 ; 11.933 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.133 ; 12.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 11.849 ; 12.104 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 10.977 ; 11.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 14.734 ; 13.894 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.948 ; 13.372 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.283 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 13.203 ; 14.106 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.961 ; 14.421 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.244 ; 14.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 12.990 ; 12.990 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 12.762 ; 12.762 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 12.198 ; 10.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 12.753 ; 11.057 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 11.323 ; 11.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 10.073 ; 12.263 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 12.505 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 12.120 ; 12.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 11.874 ; 12.260 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 13.301 ; 13.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 12.742 ; 12.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 11.583 ; 10.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.087 ; 11.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 9.578  ; 9.601  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.098  ; 8.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 11.981 ; 11.981 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 11.981 ; 11.981 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 12.665 ; 12.665 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 12.440 ; 12.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 12.882 ; 12.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 12.102 ; 12.102 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 14.901 ; 14.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.561 ; 12.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.485 ; 12.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.362 ; 12.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 11.829 ; 10.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 13.183 ; 10.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 11.829 ; 10.984 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 15.433 ; 14.190 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 12.935 ; 14.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.575 ; 11.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.664 ; 12.664 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.937 ; 12.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.551 ; 12.551 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 13.146 ; 13.146 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.443 ; 12.443 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.888 ; 12.888 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.283 ; 12.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 13.179 ; 12.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 13.316 ; 12.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.749 ; 11.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.575 ; 11.082 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.280 ; 12.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.591 ; 11.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.494 ; 11.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.929 ; 12.303 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 14.488 ; 13.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 14.744 ; 13.501 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 13.488 ; 14.730 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 13.039 ; 14.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 15.465 ; 14.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 14.066 ; 15.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 8.736  ; 9.054  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 10.853 ; 11.380 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 11.439 ; 9.743  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 9.694  ; 11.270 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.401  ; 9.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 11.298 ; 10.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 8.798  ; 10.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.400  ; 9.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 11.115 ; 11.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 12.487 ; 12.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 7.760  ; 7.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 10.569 ; 10.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 12.497 ; 12.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 10.204 ; 10.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 12.894 ; 12.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 13.524 ; 13.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 13.468 ; 13.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 12.035 ; 12.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 7.914  ; 7.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 6.252  ; 6.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 7.925  ; 7.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 6.200  ; 6.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 6.200  ; 6.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 6.222  ; 6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 6.227  ; 6.227  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 6.525  ; 6.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 8.355  ; 8.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.483  ; 7.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 6.756  ; 6.756  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 11.223 ; 11.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 11.493 ; 11.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 12.205 ; 12.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 11.245 ; 11.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 12.015 ; 12.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 12.569 ; 12.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 12.129 ; 12.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 13.999 ; 13.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 12.808 ; 12.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 13.165 ; 13.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 12.349 ; 12.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 15.173 ; 15.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 14.596 ; 14.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 7.834  ; 7.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 8.564  ; 8.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 7.518  ; 7.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 7.789  ; 7.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 7.887  ; 7.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 8.409  ; 8.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 8.755  ; 8.755  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 8.964  ; 8.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 8.585  ; 8.585  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 9.069  ; 9.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 8.249  ; 8.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 7.789  ; 7.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 8.760  ; 8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 8.879  ; 8.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 8.279  ; 8.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 10.442 ; 10.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 9.186  ; 9.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.977  ; 7.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.252  ; 8.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.483  ; 8.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.807  ; 8.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.444  ; 8.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.135  ; 8.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.190  ; 8.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.977  ; 7.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.354  ; 9.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.535  ; 9.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.484  ; 8.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.909  ; 8.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.037  ; 8.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.376  ; 8.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 8.984  ; 8.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 9.235  ; 9.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 8.784  ; 8.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 10.078 ; 10.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 9.921  ; 9.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 10.861 ; 10.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 9.204  ; 9.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 8.665  ; 8.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 11.300 ; 11.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.555  ; 9.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.927  ; 9.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 11.088 ; 11.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 2.964  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 11.115 ; 11.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 12.487 ; 12.487 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 7.760  ; 7.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 10.180 ; 10.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 10.569 ; 10.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 12.497 ; 12.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.204 ; 10.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 12.894 ; 12.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 13.524 ; 13.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 13.468 ; 13.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 12.035 ; 12.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 7.914  ; 7.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 6.205  ; 6.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 6.252  ; 6.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 7.925  ; 7.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 6.200  ; 6.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 6.200  ; 6.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 6.222  ; 6.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 6.227  ; 6.227  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 6.525  ; 6.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 8.355  ; 8.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.483  ; 7.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 6.238  ; 6.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 6.433  ; 6.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 6.756  ; 6.756  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 11.223 ; 11.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 11.493 ; 11.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.205 ; 12.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 11.245 ; 11.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 12.015 ; 12.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.569 ; 12.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 12.129 ; 12.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 13.999 ; 13.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 12.808 ; 12.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.165 ; 13.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 12.349 ; 12.349 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 15.173 ; 15.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 14.596 ; 14.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 7.834  ; 7.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.564  ; 8.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 7.518  ; 7.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 7.789  ; 7.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 7.887  ; 7.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 8.409  ; 8.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 9.110  ; 9.110  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 8.755  ; 8.755  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 8.964  ; 8.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 8.585  ; 8.585  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 8.269  ; 8.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 9.069  ; 9.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 8.249  ; 8.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 7.789  ; 7.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 8.760  ; 8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 7.800  ; 7.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 8.879  ; 8.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 8.279  ; 8.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 10.442 ; 10.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 9.186  ; 9.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.977  ; 7.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.252  ; 8.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.483  ; 8.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.807  ; 8.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 8.444  ; 8.444  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.135  ; 8.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.190  ; 8.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.977  ; 7.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.354  ; 9.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 9.535  ; 9.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.484  ; 8.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.909  ; 8.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.037  ; 8.037  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.376  ; 8.376  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 8.984  ; 8.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 9.235  ; 9.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 8.784  ; 8.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 10.078 ; 10.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 9.921  ; 9.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 10.861 ; 10.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 9.204  ; 9.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 8.665  ; 8.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 11.300 ; 11.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.555  ; 9.555  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.927  ; 9.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 11.088 ; 11.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 2.964  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 15.397 ; 15.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 16.713 ; 16.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 17.616 ; 17.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 16.593 ; 16.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 17.436 ; 17.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 16.617 ; 16.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 16.469 ; 16.469 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 15.397 ; 15.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 18.738 ; 18.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 20.210 ; 20.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 18.914 ; 18.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 17.960 ; 17.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 20.885 ; 20.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.046  ; 8.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.527  ; 8.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 8.046  ; 8.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.322  ; 8.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.539  ; 9.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.485 ; 18.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.800 ; 18.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.049 ; 19.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.176 ; 19.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.390 ; 19.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 19.510 ; 19.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.485 ; 18.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 18.983 ; 18.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 20.011 ; 20.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 20.966 ; 20.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 20.832 ; 20.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.740 ; 19.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 19.372 ; 19.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.138 ; 21.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 15.397 ; 15.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.713 ; 16.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 17.616 ; 17.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.593 ; 16.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 17.436 ; 17.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.617 ; 16.617 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 16.469 ; 16.469 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.397 ; 15.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 18.738 ; 18.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 19.045 ; 19.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 20.210 ; 20.210 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 18.914 ; 18.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.960 ; 17.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 17.851 ; 17.851 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 21.474 ; 21.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.885 ; 20.885 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.046  ; 8.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.527  ; 8.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 8.046  ; 8.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.322  ; 8.322  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.539  ; 9.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.485 ; 18.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.800 ; 18.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.049 ; 19.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.176 ; 19.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.390 ; 19.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 19.510 ; 19.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.485 ; 18.485 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 18.983 ; 18.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.011 ; 20.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 20.966 ; 20.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 20.832 ; 20.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.740 ; 19.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 19.372 ; 19.372 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.565 ; 18.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.138 ; 21.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 22.148 ; 22.148 ; 22.148 ; 22.148 ;
; ASn          ; ACSI_WRn      ; 23.520 ; 23.520 ; 23.520 ; 23.520 ;
; ASn          ; BUTTONn       ; 16.279 ;        ;        ; 16.279 ;
; ASn          ; CA1_OUT       ; 21.433 ;        ;        ; 21.433 ;
; ASn          ; CD[0]         ; 30.705 ; 30.705 ; 30.705 ; 30.705 ;
; ASn          ; CD[1]         ; 31.039 ; 31.039 ; 31.039 ; 31.039 ;
; ASn          ; CD[2]         ; 26.347 ; 26.347 ; 26.347 ; 26.347 ;
; ASn          ; CD[3]         ; 30.790 ; 30.790 ; 30.790 ; 30.790 ;
; ASn          ; CD[4]         ; 33.006 ; 33.006 ; 33.006 ; 33.006 ;
; ASn          ; CD[5]         ; 33.103 ; 33.103 ; 33.103 ; 33.103 ;
; ASn          ; CD[6]         ; 32.787 ; 32.787 ; 32.787 ; 32.787 ;
; ASn          ; CD[7]         ; 25.966 ; 25.966 ; 25.966 ; 25.966 ;
; ASn          ; DATA[0]       ; 30.501 ; 30.791 ; 30.791 ; 30.501 ;
; ASn          ; DATA[1]       ; 31.578 ; 31.578 ; 31.578 ; 31.578 ;
; ASn          ; DATA[2]       ; 30.662 ; 30.662 ; 30.662 ; 30.662 ;
; ASn          ; DATA[3]       ; 30.815 ; 31.102 ; 31.102 ; 30.815 ;
; ASn          ; DATA[4]       ; 30.121 ; 30.158 ; 30.158 ; 30.121 ;
; ASn          ; DATA[5]       ; 31.075 ; 31.075 ; 31.075 ; 31.075 ;
; ASn          ; DATA[6]       ; 30.144 ; 30.144 ; 30.144 ; 30.144 ;
; ASn          ; DATA[7]       ; 30.276 ; 30.554 ; 30.554 ; 30.276 ;
; ASn          ; DATA[8]       ; 31.993 ; 31.993 ; 31.993 ; 31.993 ;
; ASn          ; DATA[9]       ; 32.386 ; 32.245 ; 32.245 ; 32.386 ;
; ASn          ; DATA[10]      ; 32.541 ; 32.436 ; 32.436 ; 32.541 ;
; ASn          ; DATA[11]      ; 32.402 ; 32.480 ; 32.480 ; 32.402 ;
; ASn          ; DATA[12]      ; 31.301 ; 31.575 ; 31.575 ; 31.301 ;
; ASn          ; DATA[13]      ; 31.930 ; 32.314 ; 32.314 ; 31.930 ;
; ASn          ; DATA[14]      ; 33.882 ; 33.882 ; 33.882 ; 33.882 ;
; ASn          ; DATA[15]      ; 33.123 ; 33.123 ; 33.123 ; 33.123 ;
; ASn          ; DTACKn        ; 26.778 ; 26.778 ; 26.778 ; 26.778 ;
; ASn          ; FLASH_CEn     ; 15.131 ;        ;        ; 15.131 ;
; ASn          ; FLASH_OEn     ; 15.686 ;        ;        ; 15.686 ;
; ASn          ; IDE_CS0n      ; 13.497 ;        ;        ; 13.497 ;
; ASn          ; IDE_CS1n      ; 12.361 ;        ;        ; 12.361 ;
; ASn          ; IDE_D_EN_INn  ; 15.816 ;        ;        ; 15.816 ;
; ASn          ; IDE_D_EN_OUTn ; 15.431 ;        ;        ; 15.431 ;
; ASn          ; IDE_IORDn     ; 15.185 ;        ;        ; 15.185 ;
; ASn          ; IDE_IOWRn     ; 16.612 ;        ;        ; 16.612 ;
; ASn          ; JOY_RHn       ; 16.709 ;        ;        ; 16.709 ;
; ASn          ; JOY_RLn       ; 15.550 ;        ;        ; 15.550 ;
; ASn          ; JOY_WEn       ;        ; 15.702 ; 15.702 ;        ;
; ASn          ; JOY_WL        ;        ; 13.568 ; 13.568 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 17.975 ; 17.975 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 15.796 ; 15.796 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.442 ; 14.442 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 18.046 ; 18.046 ;        ;
; ASn          ; RAM_CAS1n     ; 16.790 ;        ;        ; 16.790 ;
; ASn          ; RAM_DATA[0]   ; 32.588 ; 32.878 ; 32.878 ; 32.588 ;
; ASn          ; RAM_DATA[1]   ; 33.011 ; 33.011 ; 33.011 ; 33.011 ;
; ASn          ; RAM_DATA[2]   ; 33.245 ; 33.245 ; 33.245 ; 33.245 ;
; ASn          ; RAM_DATA[3]   ; 32.769 ; 33.056 ; 33.056 ; 32.769 ;
; ASn          ; RAM_DATA[4]   ; 33.014 ; 33.051 ; 33.051 ; 33.014 ;
; ASn          ; RAM_DATA[5]   ; 33.091 ; 33.091 ; 33.091 ; 33.091 ;
; ASn          ; RAM_DATA[6]   ; 33.730 ; 33.730 ; 33.730 ; 33.730 ;
; ASn          ; RAM_DATA[7]   ; 33.994 ; 34.272 ; 34.272 ; 33.994 ;
; ASn          ; RAM_DATA[8]   ; 34.221 ; 34.221 ; 34.221 ; 34.221 ;
; ASn          ; RAM_DATA[9]   ; 34.173 ; 34.032 ; 34.032 ; 34.173 ;
; ASn          ; RAM_DATA[10]  ; 32.888 ; 32.783 ; 32.783 ; 32.888 ;
; ASn          ; RAM_DATA[11]  ; 33.228 ; 33.306 ; 33.306 ; 33.228 ;
; ASn          ; RAM_DATA[12]  ; 32.713 ; 32.987 ; 32.987 ; 32.713 ;
; ASn          ; RAM_DATA[13]  ; 32.644 ; 33.028 ; 33.028 ; 32.644 ;
; ASn          ; RAM_DATA[14]  ; 33.889 ; 33.889 ; 33.889 ; 33.889 ;
; ASn          ; RAM_DATA[15]  ; 33.376 ; 33.376 ; 33.376 ; 33.376 ;
; ASn          ; RAM_DQM0H     ;        ; 17.101 ; 17.101 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.357 ; 17.357 ;        ;
; ASn          ; RAM_DQM1H     ; 17.343 ;        ;        ; 17.343 ;
; ASn          ; RAM_DQM1L     ; 16.894 ;        ;        ; 16.894 ;
; ASn          ; RAM_RAS0n     ;        ; 18.078 ; 18.078 ;        ;
; ASn          ; RAM_RAS1n     ; 17.921 ;        ;        ; 17.921 ;
; ASn          ; ROM0n         ; 15.912 ;        ;        ; 15.912 ;
; ASn          ; ROM1n         ; 14.842 ;        ;        ; 14.842 ;
; ASn          ; ROM2n         ; 14.372 ;        ;        ; 14.372 ;
; ASn          ; ROM3n         ; 14.938 ;        ;        ; 14.938 ;
; ASn          ; ROM4n         ; 14.635 ;        ;        ; 14.635 ;
; ASn          ; ROM5n         ; 16.899 ;        ;        ; 16.899 ;
; ASn          ; ROM6n         ; 14.037 ;        ;        ; 14.037 ;
; COM_CTS      ; DATA[2]       ;        ; 21.255 ; 21.255 ;        ;
; COM_CTS      ; DATA[10]      ;        ; 23.591 ; 23.591 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 23.838 ; 23.838 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 23.938 ; 23.938 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 23.020 ; 23.020 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 22.748 ; 22.748 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 24.453 ; 24.453 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 24.535 ; 24.535 ;        ;
; COM_RI       ; DATA[6]       ;        ; 20.562 ; 20.562 ;        ;
; COM_RI       ; DATA[14]      ; 25.036 ; 25.036 ; 25.036 ; 25.036 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.148 ; 24.148 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 25.043 ; 25.043 ; 25.043 ; 25.043 ;
; CONFIG[1]    ; DATA[7]       ; 23.007 ; 23.007 ; 23.007 ; 23.007 ;
; CONFIG[1]    ; DATA[15]      ; 25.610 ; 25.610 ; 25.610 ; 25.610 ;
; CONFIG[1]    ; HSYNC         ; 14.353 ; 14.353 ; 14.353 ; 14.353 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.725 ; 26.725 ; 26.725 ; 26.725 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 17.617 ; 17.961 ; 17.961 ; 17.617 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 17.871 ; 17.871 ; 17.871 ; 17.871 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.805 ; 17.056 ; 17.056 ; 16.805 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 25.863 ; 25.863 ; 25.863 ; 25.863 ;
; CONFIG[1]    ; VSYNC         ; 14.686 ; 14.686 ; 14.686 ; 14.686 ;
; CONFIG[2]    ; DATA[7]       ; 23.109 ; 23.109 ; 23.109 ; 23.109 ;
; CONFIG[2]    ; DATA[15]      ; 25.712 ; 25.712 ; 25.712 ; 25.712 ;
; CONFIG[2]    ; HSYNC         ; 14.455 ; 14.455 ; 14.455 ; 14.455 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.827 ; 26.827 ; 26.827 ; 26.827 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 18.027 ; 17.683 ; 17.683 ; 18.027 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.937 ; 17.937 ; 17.937 ; 17.937 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.122 ; 16.871 ; 16.871 ; 17.122 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 25.965 ; 25.965 ; 25.965 ; 25.965 ;
; CONFIG[2]    ; VSYNC         ; 14.783 ; 14.783 ; 14.783 ; 14.783 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.201 ; 17.201 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.783 ; 14.783 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 32.280 ; 32.280 ; 32.280 ; 32.280 ;
; CONFIG[5]    ; ACSI_WRn      ; 33.652 ; 33.652 ; 33.652 ; 33.652 ;
; CONFIG[5]    ; BUTTONn       ; 26.906 ; 24.941 ; 24.941 ; 26.906 ;
; CONFIG[5]    ; CA1_OUT       ; 31.565 ; 29.600 ; 29.600 ; 31.565 ;
; CONFIG[5]    ; CD[0]         ; 40.837 ; 40.837 ; 40.837 ; 40.837 ;
; CONFIG[5]    ; CD[1]         ; 41.171 ; 41.171 ; 41.171 ; 41.171 ;
; CONFIG[5]    ; CD[2]         ; 36.479 ; 36.479 ; 36.479 ; 36.479 ;
; CONFIG[5]    ; CD[3]         ; 40.922 ; 40.922 ; 40.922 ; 40.922 ;
; CONFIG[5]    ; CD[4]         ; 43.138 ; 43.138 ; 43.138 ; 43.138 ;
; CONFIG[5]    ; CD[5]         ; 43.235 ; 43.235 ; 43.235 ; 43.235 ;
; CONFIG[5]    ; CD[6]         ; 42.919 ; 42.919 ; 42.919 ; 42.919 ;
; CONFIG[5]    ; CD[7]         ; 36.098 ; 36.098 ; 36.098 ; 36.098 ;
; CONFIG[5]    ; DATA[0]       ; 35.799 ; 35.909 ; 35.909 ; 35.799 ;
; CONFIG[5]    ; DATA[1]       ; 36.340 ; 36.340 ; 36.340 ; 36.340 ;
; CONFIG[5]    ; DATA[2]       ; 35.957 ; 35.957 ; 35.957 ; 35.957 ;
; CONFIG[5]    ; DATA[3]       ; 35.868 ; 35.868 ; 35.868 ; 35.868 ;
; CONFIG[5]    ; DATA[4]       ; 34.794 ; 34.831 ; 34.831 ; 34.794 ;
; CONFIG[5]    ; DATA[5]       ; 35.748 ; 35.748 ; 35.748 ; 35.748 ;
; CONFIG[5]    ; DATA[6]       ; 35.753 ; 35.753 ; 35.753 ; 35.753 ;
; CONFIG[5]    ; DATA[7]       ; 35.056 ; 35.227 ; 35.227 ; 35.056 ;
; CONFIG[5]    ; DATA[8]       ; 37.239 ; 37.239 ; 37.239 ; 37.239 ;
; CONFIG[5]    ; DATA[9]       ; 37.059 ; 36.918 ; 36.918 ; 37.059 ;
; CONFIG[5]    ; DATA[10]      ; 38.294 ; 38.294 ; 38.294 ; 38.294 ;
; CONFIG[5]    ; DATA[11]      ; 37.380 ; 37.380 ; 37.380 ; 37.380 ;
; CONFIG[5]    ; DATA[12]      ; 37.054 ; 36.810 ; 36.810 ; 37.054 ;
; CONFIG[5]    ; DATA[13]      ; 37.626 ; 37.626 ; 37.626 ; 37.626 ;
; CONFIG[5]    ; DATA[14]      ; 38.558 ; 38.558 ; 38.558 ; 38.558 ;
; CONFIG[5]    ; DATA[15]      ; 37.802 ; 37.802 ; 37.802 ; 37.802 ;
; CONFIG[5]    ; DTACKn        ; 33.673 ; 33.673 ; 33.673 ; 33.673 ;
; CONFIG[5]    ; FLASH_CEn     ; 24.755 ; 24.459 ; 24.459 ; 24.755 ;
; CONFIG[5]    ; FLASH_OEn     ; 25.310 ; 25.014 ; 25.014 ; 25.310 ;
; CONFIG[5]    ; IDE_CS0n      ; 25.738 ; 23.773 ; 23.773 ; 25.738 ;
; CONFIG[5]    ; IDE_CS1n      ; 24.774 ; 22.809 ; 22.809 ; 24.774 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 25.403 ; 23.438 ; 23.438 ; 25.403 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 25.018 ; 23.053 ; 23.053 ; 25.018 ;
; CONFIG[5]    ; IDE_IORDn     ; 24.772 ; 22.807 ; 22.807 ; 24.772 ;
; CONFIG[5]    ; IDE_IOWRn     ; 26.199 ; 24.234 ; 24.234 ; 26.199 ;
; CONFIG[5]    ; JOY_RHn       ; 27.922 ; 25.957 ; 25.957 ; 27.922 ;
; CONFIG[5]    ; JOY_RLn       ; 26.497 ; 24.532 ; 24.532 ; 26.497 ;
; CONFIG[5]    ; JOY_WEn       ; 24.684 ; 26.649 ; 26.649 ; 24.684 ;
; CONFIG[5]    ; JOY_WL        ; 25.520 ; 27.485 ; 27.485 ; 25.520 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 28.545 ; 27.005 ; 27.005 ; 28.545 ;
; CONFIG[5]    ; RAM_BA[0]     ; 26.366 ; 24.826 ; 24.826 ; 26.366 ;
; CONFIG[5]    ; RAM_BA[1]     ; 25.012 ; 23.472 ; 23.472 ; 25.012 ;
; CONFIG[5]    ; RAM_CAS0n     ; 28.616 ; 27.076 ; 27.076 ; 28.616 ;
; CONFIG[5]    ; RAM_CAS1n     ; 25.820 ; 27.360 ; 27.360 ; 25.820 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 37.886 ; 37.996 ; 37.996 ; 37.886 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 37.773 ; 37.773 ; 37.773 ; 37.773 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 38.540 ; 38.540 ; 38.540 ; 38.540 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 37.822 ; 37.822 ; 37.822 ; 37.822 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 37.687 ; 37.724 ; 37.724 ; 37.687 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 37.764 ; 37.764 ; 37.764 ; 37.764 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 39.339 ; 39.339 ; 39.339 ; 39.339 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 38.774 ; 38.945 ; 38.945 ; 38.774 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 39.467 ; 39.467 ; 39.467 ; 39.467 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 38.846 ; 38.705 ; 38.705 ; 38.846 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 38.641 ; 38.641 ; 38.641 ; 38.641 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 38.206 ; 38.206 ; 38.206 ; 38.206 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 38.466 ; 38.222 ; 38.222 ; 38.466 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 38.340 ; 38.340 ; 38.340 ; 38.340 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 38.565 ; 38.565 ; 38.565 ; 38.565 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 38.055 ; 38.055 ; 38.055 ; 38.055 ;
; CONFIG[5]    ; RAM_DQM0H     ; 27.671 ; 26.131 ; 26.131 ; 27.671 ;
; CONFIG[5]    ; RAM_DQM0L     ; 27.927 ; 26.387 ; 26.387 ; 27.927 ;
; CONFIG[5]    ; RAM_DQM1H     ; 26.373 ; 27.913 ; 27.913 ; 26.373 ;
; CONFIG[5]    ; RAM_DQM1L     ; 25.924 ; 27.464 ; 27.464 ; 25.924 ;
; CONFIG[5]    ; RAM_RAS0n     ; 28.648 ; 27.108 ; 27.108 ; 28.648 ;
; CONFIG[5]    ; RAM_RAS1n     ; 26.951 ; 28.491 ; 28.491 ; 26.951 ;
; CONFIG[5]    ; ROM0n         ; 24.031 ; 22.491 ; 22.491 ; 24.031 ;
; CONFIG[5]    ; ROM1n         ; 22.965 ; 21.425 ; 21.425 ; 22.965 ;
; CONFIG[5]    ; ROM2n         ; 23.996 ; 23.700 ; 23.700 ; 23.996 ;
; CONFIG[5]    ; ROM3n         ; 23.257 ; 23.671 ; 23.671 ; 23.257 ;
; CONFIG[5]    ; ROM4n         ; 22.960 ; 22.700 ; 22.700 ; 22.960 ;
; CONFIG[5]    ; ROM5n         ; 23.699 ; 24.291 ; 24.291 ; 23.699 ;
; CONFIG[5]    ; ROM6n         ; 22.358 ; 22.776 ; 22.776 ; 22.358 ;
; CONFIG[6]    ; DATA[0]       ; 25.262 ; 25.262 ; 25.262 ; 25.262 ;
; CONFIG[6]    ; DATA[1]       ; 26.913 ; 26.913 ; 26.913 ; 26.913 ;
; CONFIG[6]    ; DATA[2]       ; 25.713 ; 25.713 ; 25.713 ; 25.713 ;
; CONFIG[6]    ; DATA[3]       ; 26.557 ; 26.557 ; 26.557 ; 26.557 ;
; CONFIG[6]    ; DATA[4]       ; 25.893 ; 25.893 ; 25.893 ; 25.893 ;
; CONFIG[6]    ; DATA[5]       ; 25.813 ; 25.813 ; 25.813 ; 25.813 ;
; CONFIG[6]    ; DATA[6]       ; 25.124 ; 25.124 ; 25.124 ; 25.124 ;
; CONFIG[6]    ; DATA[7]       ; 25.526 ; 25.526 ; 25.526 ; 25.526 ;
; CONFIG[6]    ; DATA[8]       ; 26.728 ; 26.497 ; 26.497 ; 26.728 ;
; CONFIG[6]    ; DATA[9]       ; 26.626 ; 26.626 ; 26.626 ; 26.626 ;
; CONFIG[6]    ; DATA[10]      ; 28.444 ; 28.057 ; 28.057 ; 28.444 ;
; CONFIG[6]    ; DATA[11]      ; 27.398 ; 27.342 ; 27.342 ; 27.398 ;
; CONFIG[6]    ; DATA[12]      ; 25.797 ; 26.451 ; 26.451 ; 25.797 ;
; CONFIG[6]    ; DATA[13]      ; 26.578 ; 26.313 ; 26.313 ; 26.578 ;
; CONFIG[6]    ; DATA[14]      ; 25.275 ; 25.275 ; 25.275 ; 25.275 ;
; CONFIG[6]    ; DATA[15]      ; 24.698 ; 24.698 ; 24.698 ; 24.698 ;
; CONFIG[6]    ; DTACKn        ; 21.582 ; 21.582 ; 21.582 ; 21.582 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.016 ; 15.016 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.105 ; 14.105 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 16.994 ; 16.252 ; 16.252 ; 16.994 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.549 ; 16.807 ; 16.807 ; 17.549 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 27.349 ; 27.349 ; 27.349 ; 27.349 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 28.346 ; 28.346 ; 28.346 ; 28.346 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 28.296 ; 28.296 ; 28.296 ; 28.296 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 28.511 ; 28.511 ; 28.511 ; 28.511 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 28.786 ; 28.786 ; 28.786 ; 28.786 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.829 ; 27.829 ; 27.829 ; 27.829 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 28.710 ; 28.710 ; 28.710 ; 28.710 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 29.244 ; 29.244 ; 29.244 ; 29.244 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 28.956 ; 28.725 ; 28.725 ; 28.956 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 28.413 ; 28.413 ; 28.413 ; 28.413 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 28.791 ; 28.404 ; 28.404 ; 28.791 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 28.224 ; 28.168 ; 28.168 ; 28.224 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 27.209 ; 27.863 ; 27.863 ; 27.209 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 27.292 ; 27.027 ; 27.027 ; 27.292 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 25.282 ; 25.282 ; 25.282 ; 25.282 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.951 ; 24.951 ; 24.951 ; 24.951 ;
; CONFIG[6]    ; ROM2n         ; 16.235 ; 15.493 ; 15.493 ; 16.235 ;
; CRT_PIN3     ; DATA[7]       ; 18.241 ; 18.241 ; 18.241 ; 18.241 ;
; CRT_PIN3     ; DATA[15]      ; 20.844 ; 20.844 ; 20.844 ; 20.844 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.959 ; 21.959 ; 21.959 ; 21.959 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 13.325 ; 13.669 ; 13.669 ; 13.325 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.579 ; 13.579 ; 13.579 ; 13.579 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.513 ; 12.764 ; 12.764 ; 12.513 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 21.097 ; 21.097 ; 21.097 ; 21.097 ;
; DATA[0]      ; DATA[0]       ; 19.775 ;        ;        ; 19.775 ;
; DATA[0]      ; RAM_DATA[0]   ; 21.862 ;        ;        ; 21.862 ;
; DATA[1]      ; DATA[1]       ; 22.128 ;        ;        ; 22.128 ;
; DATA[1]      ; RAM_DATA[1]   ; 23.561 ;        ;        ; 23.561 ;
; DATA[2]      ; DATA[2]       ; 19.438 ;        ;        ; 19.438 ;
; DATA[2]      ; RAM_DATA[2]   ; 22.021 ;        ;        ; 22.021 ;
; DATA[3]      ; DATA[3]       ; 21.023 ;        ;        ; 21.023 ;
; DATA[3]      ; RAM_DATA[3]   ; 22.977 ;        ;        ; 22.977 ;
; DATA[4]      ; DATA[4]       ; 19.975 ;        ;        ; 19.975 ;
; DATA[4]      ; RAM_DATA[4]   ; 22.868 ;        ;        ; 22.868 ;
; DATA[5]      ; DATA[5]       ; 19.542 ;        ;        ; 19.542 ;
; DATA[5]      ; RAM_DATA[5]   ; 21.558 ;        ;        ; 21.558 ;
; DATA[6]      ; DATA[6]       ; 18.822 ;        ;        ; 18.822 ;
; DATA[6]      ; RAM_DATA[6]   ; 22.408 ;        ;        ; 22.408 ;
; DATA[7]      ; DATA[7]       ; 19.216 ;        ;        ; 19.216 ;
; DATA[7]      ; RAM_DATA[7]   ; 22.934 ;        ;        ; 22.934 ;
; DATA[8]      ; DATA[8]       ; 21.738 ;        ;        ; 21.738 ;
; DATA[8]      ; RAM_DATA[8]   ; 23.966 ;        ;        ; 23.966 ;
; DATA[9]      ; DATA[9]       ; 21.879 ;        ;        ; 21.879 ;
; DATA[9]      ; RAM_DATA[9]   ; 23.666 ;        ;        ; 23.666 ;
; DATA[10]     ; DATA[10]      ; 22.578 ;        ;        ; 22.578 ;
; DATA[10]     ; RAM_DATA[10]  ; 22.925 ;        ;        ; 22.925 ;
; DATA[11]     ; DATA[11]      ; 22.206 ;        ;        ; 22.206 ;
; DATA[11]     ; RAM_DATA[11]  ; 23.032 ;        ;        ; 23.032 ;
; DATA[12]     ; DATA[12]      ; 21.271 ;        ;        ; 21.271 ;
; DATA[12]     ; RAM_DATA[12]  ; 22.683 ;        ;        ; 22.683 ;
; DATA[13]     ; DATA[13]      ; 20.835 ;        ;        ; 20.835 ;
; DATA[13]     ; RAM_DATA[13]  ; 21.549 ;        ;        ; 21.549 ;
; DATA[14]     ; DATA[14]      ; 15.689 ;        ;        ; 15.689 ;
; DATA[14]     ; RAM_DATA[14]  ; 15.696 ;        ;        ; 15.696 ;
; DATA[15]     ; DATA[15]      ; 15.063 ;        ;        ; 15.063 ;
; DATA[15]     ; RAM_DATA[15]  ; 15.316 ;        ;        ; 15.316 ;
; FC[0]        ; ACSI_RDn      ; 19.899 ; 19.899 ; 19.899 ; 19.899 ;
; FC[0]        ; ACSI_WRn      ; 21.271 ; 21.271 ; 21.271 ; 21.271 ;
; FC[0]        ; BUTTONn       ; 17.123 ; 17.123 ; 17.123 ; 17.123 ;
; FC[0]        ; CA1_OUT       ; 19.184 ; 19.184 ; 19.184 ; 19.184 ;
; FC[0]        ; CD[0]         ; 28.456 ; 28.456 ; 28.456 ; 28.456 ;
; FC[0]        ; CD[1]         ; 28.790 ; 28.790 ; 28.790 ; 28.790 ;
; FC[0]        ; CD[2]         ; 24.098 ; 24.098 ; 24.098 ; 24.098 ;
; FC[0]        ; CD[3]         ; 28.541 ; 28.541 ; 28.541 ; 28.541 ;
; FC[0]        ; CD[4]         ; 30.757 ; 30.757 ; 30.757 ; 30.757 ;
; FC[0]        ; CD[5]         ; 30.854 ; 30.854 ; 30.854 ; 30.854 ;
; FC[0]        ; CD[6]         ; 30.538 ; 30.538 ; 30.538 ; 30.538 ;
; FC[0]        ; CD[7]         ; 23.717 ; 23.717 ; 23.717 ; 23.717 ;
; FC[0]        ; DATA[0]       ; 30.607 ; 30.607 ; 30.607 ; 30.607 ;
; FC[0]        ; DATA[1]       ; 31.689 ; 31.689 ; 31.689 ; 31.689 ;
; FC[0]        ; DATA[2]       ; 30.382 ; 30.382 ; 30.382 ; 30.382 ;
; FC[0]        ; DATA[3]       ; 30.962 ; 30.962 ; 30.962 ; 30.962 ;
; FC[0]        ; DATA[4]       ; 30.183 ; 30.183 ; 30.183 ; 30.183 ;
; FC[0]        ; DATA[5]       ; 30.799 ; 30.799 ; 30.799 ; 30.799 ;
; FC[0]        ; DATA[6]       ; 30.177 ; 30.177 ; 30.177 ; 30.177 ;
; FC[0]        ; DATA[7]       ; 29.560 ; 29.560 ; 29.560 ; 29.560 ;
; FC[0]        ; DATA[8]       ; 32.626 ; 32.626 ; 32.626 ; 32.626 ;
; FC[0]        ; DATA[9]       ; 31.417 ; 31.417 ; 31.417 ; 31.417 ;
; FC[0]        ; DATA[10]      ; 32.719 ; 32.719 ; 32.719 ; 32.719 ;
; FC[0]        ; DATA[11]      ; 32.447 ; 32.447 ; 32.447 ; 32.447 ;
; FC[0]        ; DATA[12]      ; 31.585 ; 31.585 ; 31.585 ; 31.585 ;
; FC[0]        ; DATA[13]      ; 32.273 ; 32.273 ; 32.273 ; 32.273 ;
; FC[0]        ; DATA[14]      ; 33.464 ; 33.464 ; 33.464 ; 33.464 ;
; FC[0]        ; DATA[15]      ; 32.163 ; 32.163 ; 32.163 ; 32.163 ;
; FC[0]        ; DTACKn        ; 25.504 ; 25.504 ; 25.504 ; 25.504 ;
; FC[0]        ; FLASH_CEn     ; 16.824 ; 16.824 ; 16.824 ; 16.824 ;
; FC[0]        ; FLASH_OEn     ; 17.379 ; 17.379 ; 17.379 ; 17.379 ;
; FC[0]        ; JOY_RHn       ; 19.551 ; 19.551 ; 19.551 ; 19.551 ;
; FC[0]        ; JOY_RLn       ; 18.392 ; 18.392 ; 18.392 ; 18.392 ;
; FC[0]        ; JOY_WEn       ; 18.544 ; 18.544 ; 18.544 ; 18.544 ;
; FC[0]        ; JOY_WL        ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; FC[0]        ; RAM_ADR[8]    ; 19.506 ; 19.506 ; 19.506 ; 19.506 ;
; FC[0]        ; RAM_BA[0]     ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; FC[0]        ; RAM_BA[1]     ; 15.973 ; 15.973 ; 15.973 ; 15.973 ;
; FC[0]        ; RAM_CAS0n     ; 19.577 ; 19.577 ; 19.577 ; 19.577 ;
; FC[0]        ; RAM_CAS1n     ; 18.321 ; 18.321 ; 18.321 ; 18.321 ;
; FC[0]        ; RAM_DATA[0]   ; 32.694 ; 32.694 ; 32.694 ; 32.694 ;
; FC[0]        ; RAM_DATA[1]   ; 33.122 ; 33.122 ; 33.122 ; 33.122 ;
; FC[0]        ; RAM_DATA[2]   ; 32.965 ; 32.965 ; 32.965 ; 32.965 ;
; FC[0]        ; RAM_DATA[3]   ; 32.916 ; 32.916 ; 32.916 ; 32.916 ;
; FC[0]        ; RAM_DATA[4]   ; 33.076 ; 33.076 ; 33.076 ; 33.076 ;
; FC[0]        ; RAM_DATA[5]   ; 32.815 ; 32.815 ; 32.815 ; 32.815 ;
; FC[0]        ; RAM_DATA[6]   ; 33.763 ; 33.763 ; 33.763 ; 33.763 ;
; FC[0]        ; RAM_DATA[7]   ; 33.278 ; 33.278 ; 33.278 ; 33.278 ;
; FC[0]        ; RAM_DATA[8]   ; 34.854 ; 34.854 ; 34.854 ; 34.854 ;
; FC[0]        ; RAM_DATA[9]   ; 33.204 ; 33.204 ; 33.204 ; 33.204 ;
; FC[0]        ; RAM_DATA[10]  ; 33.066 ; 33.066 ; 33.066 ; 33.066 ;
; FC[0]        ; RAM_DATA[11]  ; 33.273 ; 33.273 ; 33.273 ; 33.273 ;
; FC[0]        ; RAM_DATA[12]  ; 32.997 ; 32.997 ; 32.997 ; 32.997 ;
; FC[0]        ; RAM_DATA[13]  ; 32.987 ; 32.987 ; 32.987 ; 32.987 ;
; FC[0]        ; RAM_DATA[14]  ; 33.471 ; 33.471 ; 33.471 ; 33.471 ;
; FC[0]        ; RAM_DATA[15]  ; 32.416 ; 32.416 ; 32.416 ; 32.416 ;
; FC[0]        ; RAM_DQM0H     ; 18.632 ; 18.632 ; 18.632 ; 18.632 ;
; FC[0]        ; RAM_DQM0L     ; 18.888 ; 18.888 ; 18.888 ; 18.888 ;
; FC[0]        ; RAM_DQM1H     ; 18.874 ; 18.874 ; 18.874 ; 18.874 ;
; FC[0]        ; RAM_DQM1L     ; 18.425 ; 18.425 ; 18.425 ; 18.425 ;
; FC[0]        ; RAM_RAS0n     ; 19.609 ; 19.609 ; 19.609 ; 19.609 ;
; FC[0]        ; RAM_RAS1n     ; 19.452 ; 19.452 ; 19.452 ; 19.452 ;
; FC[0]        ; ROM0n         ; 15.320 ; 15.320 ; 15.320 ; 15.320 ;
; FC[0]        ; ROM1n         ; 14.250 ; 14.250 ; 14.250 ; 14.250 ;
; FC[0]        ; ROM2n         ; 16.065 ; 16.065 ; 16.065 ; 16.065 ;
; FC[0]        ; ROM3n         ; 14.346 ; 14.346 ; 14.346 ; 14.346 ;
; FC[0]        ; ROM4n         ; 14.043 ; 14.043 ; 14.043 ; 14.043 ;
; FC[0]        ; ROM5n         ; 16.307 ; 16.307 ; 16.307 ; 16.307 ;
; FC[0]        ; ROM6n         ; 13.445 ; 13.445 ; 13.445 ; 13.445 ;
; FC[1]        ; ACSI_RDn      ; 19.443 ; 19.443 ; 19.443 ; 19.443 ;
; FC[1]        ; ACSI_WRn      ; 20.815 ; 20.815 ; 20.815 ; 20.815 ;
; FC[1]        ; BUTTONn       ; 17.157 ; 17.157 ; 17.157 ; 17.157 ;
; FC[1]        ; CA1_OUT       ; 18.728 ; 18.728 ; 18.728 ; 18.728 ;
; FC[1]        ; CD[0]         ; 28.000 ; 28.000 ; 28.000 ; 28.000 ;
; FC[1]        ; CD[1]         ; 28.334 ; 28.334 ; 28.334 ; 28.334 ;
; FC[1]        ; CD[2]         ; 23.642 ; 23.642 ; 23.642 ; 23.642 ;
; FC[1]        ; CD[3]         ; 28.085 ; 28.085 ; 28.085 ; 28.085 ;
; FC[1]        ; CD[4]         ; 30.301 ; 30.301 ; 30.301 ; 30.301 ;
; FC[1]        ; CD[5]         ; 30.398 ; 30.398 ; 30.398 ; 30.398 ;
; FC[1]        ; CD[6]         ; 30.082 ; 30.082 ; 30.082 ; 30.082 ;
; FC[1]        ; CD[7]         ; 23.261 ; 23.261 ; 23.261 ; 23.261 ;
; FC[1]        ; DATA[0]       ; 30.151 ; 30.151 ; 30.151 ; 30.151 ;
; FC[1]        ; DATA[1]       ; 31.233 ; 31.233 ; 31.233 ; 31.233 ;
; FC[1]        ; DATA[2]       ; 29.929 ; 29.929 ; 29.929 ; 29.929 ;
; FC[1]        ; DATA[3]       ; 30.506 ; 30.506 ; 30.506 ; 30.506 ;
; FC[1]        ; DATA[4]       ; 29.727 ; 29.727 ; 29.727 ; 29.727 ;
; FC[1]        ; DATA[5]       ; 30.343 ; 30.343 ; 30.343 ; 30.343 ;
; FC[1]        ; DATA[6]       ; 29.724 ; 29.724 ; 29.724 ; 29.724 ;
; FC[1]        ; DATA[7]       ; 29.124 ; 29.124 ; 29.124 ; 29.124 ;
; FC[1]        ; DATA[8]       ; 32.170 ; 32.170 ; 32.170 ; 32.170 ;
; FC[1]        ; DATA[9]       ; 30.961 ; 30.961 ; 30.961 ; 30.961 ;
; FC[1]        ; DATA[10]      ; 32.266 ; 32.266 ; 32.266 ; 32.266 ;
; FC[1]        ; DATA[11]      ; 31.991 ; 31.991 ; 31.991 ; 31.991 ;
; FC[1]        ; DATA[12]      ; 31.129 ; 31.129 ; 31.129 ; 31.129 ;
; FC[1]        ; DATA[13]      ; 31.817 ; 31.817 ; 31.817 ; 31.817 ;
; FC[1]        ; DATA[14]      ; 33.008 ; 33.008 ; 33.008 ; 33.008 ;
; FC[1]        ; DATA[15]      ; 31.707 ; 31.707 ; 31.707 ; 31.707 ;
; FC[1]        ; DTACKn        ; 25.348 ; 25.348 ; 25.348 ; 25.348 ;
; FC[1]        ; FLASH_CEn     ; 16.858 ; 16.858 ; 16.858 ; 16.858 ;
; FC[1]        ; FLASH_OEn     ; 17.413 ; 17.413 ; 17.413 ; 17.413 ;
; FC[1]        ; JOY_RHn       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; FC[1]        ; JOY_RLn       ; 17.936 ; 17.936 ; 17.936 ; 17.936 ;
; FC[1]        ; JOY_WEn       ; 18.088 ; 18.088 ; 18.088 ; 18.088 ;
; FC[1]        ; JOY_WL        ; 15.954 ; 15.954 ; 15.954 ; 15.954 ;
; FC[1]        ; RAM_ADR[8]    ; 19.540 ; 19.540 ; 19.540 ; 19.540 ;
; FC[1]        ; RAM_BA[0]     ; 17.361 ; 17.361 ; 17.361 ; 17.361 ;
; FC[1]        ; RAM_BA[1]     ; 16.007 ; 16.007 ; 16.007 ; 16.007 ;
; FC[1]        ; RAM_CAS0n     ; 19.611 ; 19.611 ; 19.611 ; 19.611 ;
; FC[1]        ; RAM_CAS1n     ; 18.355 ; 18.355 ; 18.355 ; 18.355 ;
; FC[1]        ; RAM_DATA[0]   ; 32.238 ; 32.238 ; 32.238 ; 32.238 ;
; FC[1]        ; RAM_DATA[1]   ; 32.666 ; 32.666 ; 32.666 ; 32.666 ;
; FC[1]        ; RAM_DATA[2]   ; 32.512 ; 32.512 ; 32.512 ; 32.512 ;
; FC[1]        ; RAM_DATA[3]   ; 32.460 ; 32.460 ; 32.460 ; 32.460 ;
; FC[1]        ; RAM_DATA[4]   ; 32.620 ; 32.620 ; 32.620 ; 32.620 ;
; FC[1]        ; RAM_DATA[5]   ; 32.359 ; 32.359 ; 32.359 ; 32.359 ;
; FC[1]        ; RAM_DATA[6]   ; 33.310 ; 33.310 ; 33.310 ; 33.310 ;
; FC[1]        ; RAM_DATA[7]   ; 32.842 ; 32.842 ; 32.842 ; 32.842 ;
; FC[1]        ; RAM_DATA[8]   ; 34.398 ; 34.398 ; 34.398 ; 34.398 ;
; FC[1]        ; RAM_DATA[9]   ; 32.748 ; 32.748 ; 32.748 ; 32.748 ;
; FC[1]        ; RAM_DATA[10]  ; 32.613 ; 32.613 ; 32.613 ; 32.613 ;
; FC[1]        ; RAM_DATA[11]  ; 32.817 ; 32.817 ; 32.817 ; 32.817 ;
; FC[1]        ; RAM_DATA[12]  ; 32.541 ; 32.541 ; 32.541 ; 32.541 ;
; FC[1]        ; RAM_DATA[13]  ; 32.531 ; 32.531 ; 32.531 ; 32.531 ;
; FC[1]        ; RAM_DATA[14]  ; 33.015 ; 33.015 ; 33.015 ; 33.015 ;
; FC[1]        ; RAM_DATA[15]  ; 31.960 ; 31.960 ; 31.960 ; 31.960 ;
; FC[1]        ; RAM_DQM0H     ; 18.666 ; 18.666 ; 18.666 ; 18.666 ;
; FC[1]        ; RAM_DQM0L     ; 18.922 ; 18.922 ; 18.922 ; 18.922 ;
; FC[1]        ; RAM_DQM1H     ; 18.908 ; 18.908 ; 18.908 ; 18.908 ;
; FC[1]        ; RAM_DQM1L     ; 18.459 ; 18.459 ; 18.459 ; 18.459 ;
; FC[1]        ; RAM_RAS0n     ; 19.643 ; 19.643 ; 19.643 ; 19.643 ;
; FC[1]        ; RAM_RAS1n     ; 19.486 ; 19.486 ; 19.486 ; 19.486 ;
; FC[1]        ; ROM0n         ; 15.355 ; 15.355 ; 15.355 ; 15.355 ;
; FC[1]        ; ROM1n         ; 14.285 ; 14.285 ; 14.285 ; 14.285 ;
; FC[1]        ; ROM2n         ; 16.099 ; 16.099 ; 16.099 ; 16.099 ;
; FC[1]        ; ROM3n         ; 14.381 ; 14.381 ; 14.381 ; 14.381 ;
; FC[1]        ; ROM4n         ; 14.078 ; 14.078 ; 14.078 ; 14.078 ;
; FC[1]        ; ROM5n         ; 16.342 ; 16.342 ; 16.342 ; 16.342 ;
; FC[1]        ; ROM6n         ; 13.480 ; 13.480 ; 13.480 ; 13.480 ;
; FC[2]        ; ACSI_RDn      ; 19.742 ; 19.742 ; 19.742 ; 19.742 ;
; FC[2]        ; ACSI_WRn      ; 21.114 ; 21.114 ; 21.114 ; 21.114 ;
; FC[2]        ; CA1_OUT       ;        ; 19.027 ; 19.027 ;        ;
; FC[2]        ; CD[0]         ; 28.299 ; 28.299 ; 28.299 ; 28.299 ;
; FC[2]        ; CD[1]         ; 28.633 ; 28.633 ; 28.633 ; 28.633 ;
; FC[2]        ; CD[2]         ; 23.941 ; 23.941 ; 23.941 ; 23.941 ;
; FC[2]        ; CD[3]         ; 28.384 ; 28.384 ; 28.384 ; 28.384 ;
; FC[2]        ; CD[4]         ; 30.600 ; 30.600 ; 30.600 ; 30.600 ;
; FC[2]        ; CD[5]         ; 30.697 ; 30.697 ; 30.697 ; 30.697 ;
; FC[2]        ; CD[6]         ; 30.381 ; 30.381 ; 30.381 ; 30.381 ;
; FC[2]        ; CD[7]         ; 23.560 ; 23.560 ; 23.560 ; 23.560 ;
; FC[2]        ; DATA[0]       ; 30.450 ; 30.450 ; 30.450 ; 30.450 ;
; FC[2]        ; DATA[1]       ; 31.532 ; 31.532 ; 31.532 ; 31.532 ;
; FC[2]        ; DATA[2]       ; 30.227 ; 30.227 ; 30.227 ; 30.227 ;
; FC[2]        ; DATA[3]       ; 30.805 ; 30.754 ; 30.754 ; 30.805 ;
; FC[2]        ; DATA[4]       ; 30.026 ; 30.026 ; 30.026 ; 30.026 ;
; FC[2]        ; DATA[5]       ; 30.642 ; 30.642 ; 30.642 ; 30.642 ;
; FC[2]        ; DATA[6]       ; 30.022 ; 30.022 ; 30.022 ; 30.022 ;
; FC[2]        ; DATA[7]       ; 29.403 ; 29.403 ; 29.403 ; 29.403 ;
; FC[2]        ; DATA[8]       ; 32.469 ; 32.469 ; 32.469 ; 32.469 ;
; FC[2]        ; DATA[9]       ; 31.260 ; 31.260 ; 31.260 ; 31.260 ;
; FC[2]        ; DATA[10]      ; 32.564 ; 32.564 ; 32.564 ; 32.564 ;
; FC[2]        ; DATA[11]      ; 32.290 ; 32.239 ; 32.239 ; 32.290 ;
; FC[2]        ; DATA[12]      ; 31.428 ; 31.428 ; 31.428 ; 31.428 ;
; FC[2]        ; DATA[13]      ; 32.116 ; 32.116 ; 32.116 ; 32.116 ;
; FC[2]        ; DATA[14]      ; 33.307 ; 33.307 ; 33.307 ; 33.307 ;
; FC[2]        ; DATA[15]      ; 32.006 ; 32.006 ; 32.006 ; 32.006 ;
; FC[2]        ; DTACKn        ; 22.639 ; 22.639 ; 22.639 ; 22.639 ;
; FC[2]        ; JOY_RHn       ;        ; 19.394 ; 19.394 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 18.235 ; 18.235 ;        ;
; FC[2]        ; JOY_WEn       ; 18.387 ;        ;        ; 18.387 ;
; FC[2]        ; JOY_WL        ; 16.253 ;        ;        ; 16.253 ;
; FC[2]        ; RAM_DATA[0]   ; 32.537 ; 32.537 ; 32.537 ; 32.537 ;
; FC[2]        ; RAM_DATA[1]   ; 32.965 ; 32.965 ; 32.965 ; 32.965 ;
; FC[2]        ; RAM_DATA[2]   ; 32.810 ; 32.810 ; 32.810 ; 32.810 ;
; FC[2]        ; RAM_DATA[3]   ; 32.759 ; 32.708 ; 32.708 ; 32.759 ;
; FC[2]        ; RAM_DATA[4]   ; 32.919 ; 32.919 ; 32.919 ; 32.919 ;
; FC[2]        ; RAM_DATA[5]   ; 32.658 ; 32.658 ; 32.658 ; 32.658 ;
; FC[2]        ; RAM_DATA[6]   ; 33.608 ; 33.608 ; 33.608 ; 33.608 ;
; FC[2]        ; RAM_DATA[7]   ; 33.121 ; 33.121 ; 33.121 ; 33.121 ;
; FC[2]        ; RAM_DATA[8]   ; 34.697 ; 34.697 ; 34.697 ; 34.697 ;
; FC[2]        ; RAM_DATA[9]   ; 33.047 ; 33.047 ; 33.047 ; 33.047 ;
; FC[2]        ; RAM_DATA[10]  ; 32.911 ; 32.911 ; 32.911 ; 32.911 ;
; FC[2]        ; RAM_DATA[11]  ; 33.116 ; 33.065 ; 33.065 ; 33.116 ;
; FC[2]        ; RAM_DATA[12]  ; 32.840 ; 32.840 ; 32.840 ; 32.840 ;
; FC[2]        ; RAM_DATA[13]  ; 32.830 ; 32.830 ; 32.830 ; 32.830 ;
; FC[2]        ; RAM_DATA[14]  ; 33.314 ; 33.314 ; 33.314 ; 33.314 ;
; FC[2]        ; RAM_DATA[15]  ; 32.259 ; 32.259 ; 32.259 ; 32.259 ;
; HDINTn       ; DATA[5]       ; 24.068 ;        ;        ; 24.068 ;
; HDINTn       ; DATA[13]      ; 25.542 ;        ;        ; 25.542 ;
; HDINTn       ; RAM_DATA[5]   ; 26.084 ;        ;        ; 26.084 ;
; HDINTn       ; RAM_DATA[13]  ; 26.256 ;        ;        ; 26.256 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.507 ; 24.507 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 25.981 ; 25.981 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.523 ; 26.523 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 26.695 ; 26.695 ;        ;
; IDE_IORDY    ; DTACKn        ; 21.049 ; 21.049 ; 21.049 ; 21.049 ;
; LDSn         ; ACSI_RDn      ; 18.937 ; 18.937 ; 18.937 ; 18.937 ;
; LDSn         ; ACSI_WRn      ; 20.309 ; 20.309 ; 20.309 ; 20.309 ;
; LDSn         ; BUTTONn       ; 15.512 ;        ;        ; 15.512 ;
; LDSn         ; CA1_OUT       ; 18.222 ;        ;        ; 18.222 ;
; LDSn         ; CD[0]         ; 27.494 ; 27.494 ; 27.494 ; 27.494 ;
; LDSn         ; CD[1]         ; 27.828 ; 27.828 ; 27.828 ; 27.828 ;
; LDSn         ; CD[2]         ; 23.136 ; 23.136 ; 23.136 ; 23.136 ;
; LDSn         ; CD[3]         ; 27.579 ; 27.579 ; 27.579 ; 27.579 ;
; LDSn         ; CD[4]         ; 29.795 ; 29.795 ; 29.795 ; 29.795 ;
; LDSn         ; CD[5]         ; 29.892 ; 29.892 ; 29.892 ; 29.892 ;
; LDSn         ; CD[6]         ; 29.576 ; 29.576 ; 29.576 ; 29.576 ;
; LDSn         ; CD[7]         ; 22.755 ; 22.755 ; 22.755 ; 22.755 ;
; LDSn         ; DATA[0]       ; 28.560 ; 28.850 ; 28.850 ; 28.560 ;
; LDSn         ; DATA[1]       ; 29.637 ; 29.637 ; 29.637 ; 29.637 ;
; LDSn         ; DATA[2]       ; 28.721 ; 28.721 ; 28.721 ; 28.721 ;
; LDSn         ; DATA[3]       ; 28.874 ; 29.161 ; 29.161 ; 28.874 ;
; LDSn         ; DATA[4]       ; 28.180 ; 28.217 ; 28.217 ; 28.180 ;
; LDSn         ; DATA[5]       ; 29.134 ; 29.134 ; 29.134 ; 29.134 ;
; LDSn         ; DATA[6]       ; 28.203 ; 28.203 ; 28.203 ; 28.203 ;
; LDSn         ; DATA[7]       ; 28.335 ; 28.613 ; 28.613 ; 28.335 ;
; LDSn         ; DATA[8]       ; 30.052 ; 30.052 ; 30.052 ; 30.052 ;
; LDSn         ; DATA[9]       ; 30.445 ; 30.304 ; 30.304 ; 30.445 ;
; LDSn         ; DATA[10]      ; 30.600 ; 30.495 ; 30.495 ; 30.600 ;
; LDSn         ; DATA[11]      ; 30.461 ; 30.539 ; 30.539 ; 30.461 ;
; LDSn         ; DATA[12]      ; 29.360 ; 29.634 ; 29.634 ; 29.360 ;
; LDSn         ; DATA[13]      ; 29.989 ; 30.373 ; 30.373 ; 29.989 ;
; LDSn         ; DATA[14]      ; 31.941 ; 31.941 ; 31.941 ; 31.941 ;
; LDSn         ; DATA[15]      ; 31.182 ; 31.182 ; 31.182 ; 31.182 ;
; LDSn         ; DTACKn        ; 24.837 ; 24.837 ; 24.837 ; 24.837 ;
; LDSn         ; IDE_IORDn     ; 13.117 ;        ;        ; 13.117 ;
; LDSn         ; IDE_IOWRn     ; 14.546 ;        ;        ; 14.546 ;
; LDSn         ; JOY_RLn       ; 16.673 ;        ;        ; 16.673 ;
; LDSn         ; JOY_WEn       ;        ; 16.825 ; 16.825 ;        ;
; LDSn         ; JOY_WL        ;        ; 13.922 ; 13.922 ;        ;
; LDSn         ; RAM_CAS0n     ; 16.261 ;        ;        ; 16.261 ;
; LDSn         ; RAM_CAS1n     ; 15.005 ;        ;        ; 15.005 ;
; LDSn         ; RAM_DATA[0]   ; 30.647 ; 30.937 ; 30.937 ; 30.647 ;
; LDSn         ; RAM_DATA[1]   ; 31.070 ; 31.070 ; 31.070 ; 31.070 ;
; LDSn         ; RAM_DATA[2]   ; 31.304 ; 31.304 ; 31.304 ; 31.304 ;
; LDSn         ; RAM_DATA[3]   ; 30.828 ; 31.115 ; 31.115 ; 30.828 ;
; LDSn         ; RAM_DATA[4]   ; 31.073 ; 31.110 ; 31.110 ; 31.073 ;
; LDSn         ; RAM_DATA[5]   ; 31.150 ; 31.150 ; 31.150 ; 31.150 ;
; LDSn         ; RAM_DATA[6]   ; 31.789 ; 31.789 ; 31.789 ; 31.789 ;
; LDSn         ; RAM_DATA[7]   ; 32.053 ; 32.331 ; 32.331 ; 32.053 ;
; LDSn         ; RAM_DATA[8]   ; 32.280 ; 32.280 ; 32.280 ; 32.280 ;
; LDSn         ; RAM_DATA[9]   ; 32.232 ; 32.091 ; 32.091 ; 32.232 ;
; LDSn         ; RAM_DATA[10]  ; 30.947 ; 30.842 ; 30.842 ; 30.947 ;
; LDSn         ; RAM_DATA[11]  ; 31.287 ; 31.365 ; 31.365 ; 31.287 ;
; LDSn         ; RAM_DATA[12]  ; 30.772 ; 31.046 ; 31.046 ; 30.772 ;
; LDSn         ; RAM_DATA[13]  ; 30.703 ; 31.087 ; 31.087 ; 30.703 ;
; LDSn         ; RAM_DATA[14]  ; 31.948 ; 31.948 ; 31.948 ; 31.948 ;
; LDSn         ; RAM_DATA[15]  ; 31.435 ; 31.435 ; 31.435 ; 31.435 ;
; LDSn         ; RAM_DQM0L     ; 14.741 ;        ;        ; 14.741 ;
; LDSn         ; RAM_DQM1L     ; 14.286 ;        ;        ; 14.286 ;
; LPT_BSY      ; DATA[0]       ; 23.440 ;        ;        ; 23.440 ;
; LPT_BSY      ; DATA[8]       ; 25.459 ;        ;        ; 25.459 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.527 ;        ;        ; 25.527 ;
; LPT_BSY      ; RAM_DATA[8]   ; 27.687 ;        ;        ; 27.687 ;
; LPT_D[0]     ; DATA[0]       ; 19.574 ;        ;        ; 19.574 ;
; LPT_D[0]     ; DATA[8]       ; 21.252 ;        ;        ; 21.252 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 21.661 ;        ;        ; 21.661 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 23.480 ;        ;        ; 23.480 ;
; LPT_D[1]     ; DATA[1]       ; 21.080 ;        ;        ; 21.080 ;
; LPT_D[1]     ; DATA[9]       ; 21.204 ;        ;        ; 21.204 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 22.513 ;        ;        ; 22.513 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.991 ;        ;        ; 22.991 ;
; LPT_D[2]     ; DATA[2]       ; 20.240 ;        ;        ; 20.240 ;
; LPT_D[2]     ; DATA[10]      ; 22.577 ;        ;        ; 22.577 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 22.823 ;        ;        ; 22.823 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 22.924 ;        ;        ; 22.924 ;
; LPT_D[3]     ; DATA[3]       ; 20.711 ;        ;        ; 20.711 ;
; LPT_D[3]     ; DATA[11]      ; 22.223 ;        ;        ; 22.223 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 22.665 ;        ;        ; 22.665 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 23.049 ;        ;        ; 23.049 ;
; LPT_D[4]     ; DATA[4]       ; 22.828 ;        ;        ; 22.828 ;
; LPT_D[4]     ; DATA[12]      ; 24.045 ;        ;        ; 24.045 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.721 ;        ;        ; 25.721 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 25.457 ;        ;        ; 25.457 ;
; LPT_D[5]     ; DATA[5]       ; 20.161 ;        ;        ; 20.161 ;
; LPT_D[5]     ; DATA[13]      ; 22.249 ;        ;        ; 22.249 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 22.177 ;        ;        ; 22.177 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.963 ;        ;        ; 22.963 ;
; LPT_D[6]     ; DATA[6]       ; 20.170 ;        ;        ; 20.170 ;
; LPT_D[6]     ; DATA[14]      ; 22.975 ; 22.975 ; 22.975 ; 22.975 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 23.756 ;        ;        ; 23.756 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 22.982 ; 22.982 ; 22.982 ; 22.982 ;
; LPT_D[7]     ; DATA[7]       ; 20.541 ;        ;        ; 20.541 ;
; LPT_D[7]     ; DATA[15]      ; 22.601 ; 22.601 ; 22.601 ; 22.601 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 24.259 ;        ;        ; 24.259 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 22.854 ; 22.854 ; 22.854 ; 22.854 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 22.386 ;        ;        ; 22.386 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 24.473 ;        ;        ; 24.473 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.685 ;        ;        ; 24.685 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 26.118 ;        ;        ; 26.118 ;
; RAM_DATA[2]  ; DATA[2]       ; 24.490 ;        ;        ; 24.490 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 27.073 ;        ;        ; 27.073 ;
; RAM_DATA[3]  ; DATA[3]       ; 22.581 ;        ;        ; 22.581 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.535 ;        ;        ; 24.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.917 ;        ;        ; 21.917 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 24.810 ;        ;        ; 24.810 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.287 ;        ;        ; 23.287 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.303 ;        ;        ; 25.303 ;
; RAM_DATA[6]  ; DATA[6]       ; 22.355 ;        ;        ; 22.355 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.941 ;        ;        ; 25.941 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.981 ;        ;        ; 22.981 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 26.699 ;        ;        ; 26.699 ;
; RAM_DATA[8]  ; DATA[8]       ; 25.310 ;        ;        ; 25.310 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 27.538 ;        ;        ; 27.538 ;
; RAM_DATA[9]  ; DATA[9]       ; 24.007 ;        ;        ; 24.007 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.794 ;        ;        ; 25.794 ;
; RAM_DATA[10] ; DATA[10]      ; 25.005 ;        ;        ; 25.005 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 25.352 ;        ;        ; 25.352 ;
; RAM_DATA[11] ; DATA[11]      ; 24.771 ;        ;        ; 24.771 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 25.597 ;        ;        ; 25.597 ;
; RAM_DATA[12] ; DATA[12]      ; 23.020 ;        ;        ; 23.020 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 24.432 ;        ;        ; 24.432 ;
; RAM_DATA[13] ; DATA[13]      ; 24.628 ;        ;        ; 24.628 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 25.342 ;        ;        ; 25.342 ;
; RAM_DATA[14] ; DATA[14]      ; 24.239 ; 24.239 ; 24.239 ; 24.239 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 24.246 ; 24.246 ; 24.246 ; 24.246 ;
; RAM_DATA[15] ; DATA[15]      ; 24.937 ; 24.937 ; 24.937 ; 24.937 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 25.190 ; 25.190 ; 25.190 ; 25.190 ;
; RWn          ; ACSI_RDn      ; 18.870 ; 18.870 ; 18.870 ; 18.870 ;
; RWn          ; ACSI_WRn      ; 20.242 ; 20.242 ; 20.242 ; 20.242 ;
; RWn          ; BUTTONn       ;        ; 15.643 ; 15.643 ;        ;
; RWn          ; CA1_OUT       ;        ; 18.155 ; 18.155 ;        ;
; RWn          ; CD[0]         ; 27.427 ; 27.427 ; 27.427 ; 27.427 ;
; RWn          ; CD[1]         ; 27.761 ; 27.761 ; 27.761 ; 27.761 ;
; RWn          ; CD[2]         ; 23.069 ; 23.069 ; 23.069 ; 23.069 ;
; RWn          ; CD[3]         ; 27.512 ; 27.512 ; 27.512 ; 27.512 ;
; RWn          ; CD[4]         ; 29.728 ; 29.728 ; 29.728 ; 29.728 ;
; RWn          ; CD[5]         ; 29.825 ; 29.825 ; 29.825 ; 29.825 ;
; RWn          ; CD[6]         ; 29.509 ; 29.509 ; 29.509 ; 29.509 ;
; RWn          ; CD[7]         ; 22.688 ; 22.688 ; 22.688 ; 22.688 ;
; RWn          ; DATA[0]       ; 29.578 ; 29.578 ; 29.578 ; 29.578 ;
; RWn          ; DATA[1]       ; 30.660 ; 30.660 ; 30.660 ; 30.660 ;
; RWn          ; DATA[2]       ; 29.356 ; 29.356 ; 29.356 ; 29.356 ;
; RWn          ; DATA[3]       ; 29.933 ; 29.882 ; 29.882 ; 29.933 ;
; RWn          ; DATA[4]       ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
; RWn          ; DATA[5]       ; 29.770 ; 29.770 ; 29.770 ; 29.770 ;
; RWn          ; DATA[6]       ; 29.151 ; 29.151 ; 29.151 ; 29.151 ;
; RWn          ; DATA[7]       ; 28.531 ; 28.531 ; 28.531 ; 28.531 ;
; RWn          ; DATA[8]       ; 31.597 ; 31.597 ; 31.597 ; 31.597 ;
; RWn          ; DATA[9]       ; 30.388 ; 30.388 ; 30.388 ; 30.388 ;
; RWn          ; DATA[10]      ; 31.693 ; 31.693 ; 31.693 ; 31.693 ;
; RWn          ; DATA[11]      ; 31.418 ; 31.367 ; 31.367 ; 31.418 ;
; RWn          ; DATA[12]      ; 30.556 ; 30.556 ; 30.556 ; 30.556 ;
; RWn          ; DATA[13]      ; 31.244 ; 31.244 ; 31.244 ; 31.244 ;
; RWn          ; DATA[14]      ; 32.435 ; 32.435 ; 32.435 ; 32.435 ;
; RWn          ; DATA[15]      ; 31.134 ; 31.134 ; 31.134 ; 31.134 ;
; RWn          ; DTACKn        ; 24.283 ; 24.283 ; 24.283 ; 24.283 ;
; RWn          ; FLASH_CEn     ;        ; 14.864 ; 14.864 ;        ;
; RWn          ; FLASH_OEn     ;        ; 15.419 ; 15.419 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.749 ; 14.749 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 12.847 ;        ;        ; 12.847 ;
; RWn          ; IDE_IORDn     ;        ; 12.986 ; 12.986 ;        ;
; RWn          ; IDE_IOWRn     ; 14.416 ;        ;        ; 14.416 ;
; RWn          ; JOY_RHn       ;        ; 18.522 ; 18.522 ;        ;
; RWn          ; JOY_RLn       ;        ; 17.363 ; 17.363 ;        ;
; RWn          ; JOY_WEn       ; 17.515 ;        ;        ; 17.515 ;
; RWn          ; JOY_WL        ; 15.381 ; 13.745 ; 13.745 ; 15.381 ;
; RWn          ; RAM_DATA[0]   ; 31.665 ; 31.665 ; 31.665 ; 31.665 ;
; RWn          ; RAM_DATA[1]   ; 32.093 ; 32.093 ; 32.093 ; 32.093 ;
; RWn          ; RAM_DATA[2]   ; 31.939 ; 31.939 ; 31.939 ; 31.939 ;
; RWn          ; RAM_DATA[3]   ; 31.887 ; 31.836 ; 31.836 ; 31.887 ;
; RWn          ; RAM_DATA[4]   ; 32.047 ; 32.047 ; 32.047 ; 32.047 ;
; RWn          ; RAM_DATA[5]   ; 31.786 ; 31.786 ; 31.786 ; 31.786 ;
; RWn          ; RAM_DATA[6]   ; 32.737 ; 32.737 ; 32.737 ; 32.737 ;
; RWn          ; RAM_DATA[7]   ; 32.249 ; 32.249 ; 32.249 ; 32.249 ;
; RWn          ; RAM_DATA[8]   ; 33.825 ; 33.825 ; 33.825 ; 33.825 ;
; RWn          ; RAM_DATA[9]   ; 32.175 ; 32.175 ; 32.175 ; 32.175 ;
; RWn          ; RAM_DATA[10]  ; 32.040 ; 32.040 ; 32.040 ; 32.040 ;
; RWn          ; RAM_DATA[11]  ; 32.244 ; 32.193 ; 32.193 ; 32.244 ;
; RWn          ; RAM_DATA[12]  ; 31.968 ; 31.968 ; 31.968 ; 31.968 ;
; RWn          ; RAM_DATA[13]  ; 31.958 ; 31.958 ; 31.958 ; 31.958 ;
; RWn          ; RAM_DATA[14]  ; 32.442 ; 32.442 ; 32.442 ; 32.442 ;
; RWn          ; RAM_DATA[15]  ; 31.387 ; 31.387 ; 31.387 ; 31.387 ;
; RWn          ; RAM_WEn       ; 14.842 ;        ;        ; 14.842 ;
; RWn          ; ROM0n         ;        ; 14.976 ; 14.976 ;        ;
; RWn          ; ROM1n         ;        ; 13.906 ; 13.906 ;        ;
; RWn          ; ROM2n         ;        ; 14.105 ; 14.105 ;        ;
; RWn          ; ROM3n         ;        ; 14.002 ; 14.002 ;        ;
; RWn          ; ROM4n         ;        ; 13.699 ; 13.699 ;        ;
; RWn          ; ROM5n         ;        ; 15.963 ; 15.963 ;        ;
; RWn          ; ROM6n         ;        ; 13.101 ; 13.101 ;        ;
; SCSI_ACKn    ; CD[0]         ; 16.457 ; 16.457 ; 16.457 ; 16.457 ;
; SCSI_ATNn    ; CD[1]         ; 18.058 ; 18.058 ; 18.058 ; 18.058 ;
; SCSI_BSYn    ; CD[6]         ; 22.644 ; 22.644 ; 22.644 ; 22.644 ;
; SCSI_D[0]    ; CD[0]         ; 17.333 ; 17.333 ; 17.333 ; 17.333 ;
; SCSI_D[1]    ; CD[1]         ; 16.480 ; 16.480 ; 16.480 ; 16.480 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.613 ; 16.613 ;        ;
; SCSI_D[3]    ; CD[3]         ; 16.418 ; 16.418 ; 16.418 ; 16.418 ;
; SCSI_D[4]    ; CD[4]         ; 23.558 ; 23.558 ; 23.558 ; 23.558 ;
; SCSI_D[5]    ; CD[5]         ; 23.090 ; 23.090 ; 23.090 ; 23.090 ;
; SCSI_D[6]    ; CD[6]         ; 22.848 ; 22.848 ; 22.848 ; 22.848 ;
; SCSI_D[7]    ; CD[7]         ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; SCSI_DCn     ; CD[3]         ; 18.105 ; 18.105 ; 18.105 ; 18.105 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 16.690 ; 16.690 ; 16.690 ; 16.690 ;
; SCSI_DCn     ; SCSI_D[0]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[1]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[2]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[3]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[4]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[5]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[6]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_D[7]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_DP       ; 15.359 ; 15.359 ; 15.359 ; 15.359 ;
; SCSI_DP      ; CD[0]         ; 16.084 ; 16.084 ; 16.084 ; 16.084 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.209 ; 12.209 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.911 ;        ;        ; 12.911 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.310 ; 12.310 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.664 ;        ;        ; 12.664 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 12.961 ; 12.961 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 12.526 ;        ;        ; 12.526 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.749 ; 13.749 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.994 ;        ;        ; 12.994 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 14.270 ; 14.270 ; 14.270 ; 14.270 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.564 ; 11.564 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 12.276 ; 12.276 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.663 ;        ;        ; 11.663 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.018 ;        ;        ; 12.018 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.320 ; 12.320 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 11.894 ; 11.894 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.108 ;        ;        ; 13.108 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.349 ;        ;        ; 12.349 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 13.629 ; 13.629 ; 13.629 ; 13.629 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.373 ; 12.373 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.079 ; 13.079 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.503 ; 12.503 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.857 ; 12.857 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.065 ;        ;        ; 13.065 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 12.636 ;        ;        ; 12.636 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.893 ;        ;        ; 13.893 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.127 ;        ;        ; 13.127 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 14.414 ; 14.414 ; 14.414 ; 14.414 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.074 ; 17.074 ;        ;
; SCSI_IOn     ; CD[3]         ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 16.228 ; 16.228 ; 16.228 ; 16.228 ;
; SCSI_IOn     ; SCSI_D[0]     ; 14.887 ; 14.887 ; 14.887 ; 14.887 ;
; SCSI_IOn     ; SCSI_D[1]     ; 14.887 ; 14.887 ; 14.887 ; 14.887 ;
; SCSI_IOn     ; SCSI_D[2]     ; 14.341 ; 14.341 ; 14.341 ; 14.341 ;
; SCSI_IOn     ; SCSI_D[3]     ; 14.341 ; 14.341 ; 14.341 ; 14.341 ;
; SCSI_IOn     ; SCSI_D[4]     ; 14.649 ; 14.649 ; 14.649 ; 14.649 ;
; SCSI_IOn     ; SCSI_D[5]     ; 14.649 ; 14.649 ; 14.649 ; 14.649 ;
; SCSI_IOn     ; SCSI_D[6]     ; 14.925 ; 14.925 ; 14.925 ; 14.925 ;
; SCSI_IOn     ; SCSI_D[7]     ; 14.925 ; 14.925 ; 14.925 ; 14.925 ;
; SCSI_IOn     ; SCSI_DP       ; 14.897 ; 14.897 ; 14.897 ; 14.897 ;
; SCSI_IOn     ; SCSI_RDn      ; 13.498 ;        ;        ; 13.498 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.290 ; 13.290 ;        ;
; SCSI_MSGn    ; CD[3]         ; 17.772 ; 17.772 ; 17.772 ; 17.772 ;
; SCSI_MSGn    ; CD[4]         ; 22.329 ; 22.329 ; 22.329 ; 22.329 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 16.357 ; 16.357 ; 16.357 ; 16.357 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_DP       ; 15.026 ; 15.026 ; 15.026 ; 15.026 ;
; SCSI_REQn    ; CD[3]         ; 17.887 ; 17.887 ; 17.887 ; 17.887 ;
; SCSI_REQn    ; CD[5]         ; 22.156 ; 22.156 ; 22.156 ; 22.156 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 16.472 ;        ;        ; 16.472 ;
; SCSI_REQn    ; SCSI_D[0]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[1]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[2]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[3]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[4]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[5]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[6]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_D[7]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_DP       ; 15.141 ; 15.141 ; 15.141 ; 15.141 ;
; SCSI_RSTn    ; CD[7]         ;        ; 18.133 ; 18.133 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.156 ; 16.156 ; 16.156 ; 16.156 ;
; SD_AVR_ENn   ; RESETn        ;        ; 17.730 ; 17.730 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.086 ; 13.086 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 10.631 ; 10.631 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.038 ;        ;        ; 13.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.504 ;        ;        ; 12.504 ;
; SD_RESETn    ; ACSI_RDn      ; 21.724 ; 21.724 ; 21.724 ; 21.724 ;
; SD_RESETn    ; ACSI_WRn      ; 23.096 ; 23.096 ; 23.096 ; 23.096 ;
; SD_RESETn    ; CA1_OUT       ; 21.009 ;        ;        ; 21.009 ;
; SD_RESETn    ; CD[0]         ; 30.281 ; 30.281 ; 30.281 ; 30.281 ;
; SD_RESETn    ; CD[1]         ; 30.615 ; 30.615 ; 30.615 ; 30.615 ;
; SD_RESETn    ; CD[2]         ; 25.923 ; 25.923 ; 25.923 ; 25.923 ;
; SD_RESETn    ; CD[3]         ; 30.366 ; 30.366 ; 30.366 ; 30.366 ;
; SD_RESETn    ; CD[4]         ; 32.582 ; 32.582 ; 32.582 ; 32.582 ;
; SD_RESETn    ; CD[5]         ; 32.679 ; 32.679 ; 32.679 ; 32.679 ;
; SD_RESETn    ; CD[6]         ; 32.363 ; 32.363 ; 32.363 ; 32.363 ;
; SD_RESETn    ; CD[7]         ; 25.542 ; 25.542 ; 25.542 ; 25.542 ;
; SD_RESETn    ; COM_TxD       ; 18.782 ; 18.782 ; 18.782 ; 18.782 ;
; SD_RESETn    ; DATA[0]       ; 27.599 ; 27.925 ; 27.925 ; 27.599 ;
; SD_RESETn    ; DATA[1]       ; 28.162 ; 28.162 ; 28.162 ; 28.162 ;
; SD_RESETn    ; DATA[2]       ; 26.730 ; 26.730 ; 26.730 ; 26.730 ;
; SD_RESETn    ; DATA[3]       ; 27.445 ; 27.445 ; 27.445 ; 27.445 ;
; SD_RESETn    ; DATA[4]       ; 27.186 ; 27.186 ; 27.186 ; 27.186 ;
; SD_RESETn    ; DATA[5]       ; 27.039 ; 27.039 ; 27.039 ; 27.039 ;
; SD_RESETn    ; DATA[6]       ; 26.791 ; 26.791 ; 26.791 ; 26.791 ;
; SD_RESETn    ; DATA[7]       ; 27.396 ; 27.396 ; 27.396 ; 27.396 ;
; SD_RESETn    ; DATA[8]       ; 29.395 ; 29.721 ; 29.721 ; 29.395 ;
; SD_RESETn    ; DATA[9]       ; 29.150 ; 29.150 ; 29.150 ; 29.150 ;
; SD_RESETn    ; DATA[10]      ; 29.333 ; 29.333 ; 29.333 ; 29.333 ;
; SD_RESETn    ; DATA[11]      ; 28.908 ; 28.908 ; 28.908 ; 28.908 ;
; SD_RESETn    ; DATA[12]      ; 28.146 ; 28.146 ; 28.146 ; 28.146 ;
; SD_RESETn    ; DATA[13]      ; 28.143 ; 28.143 ; 28.143 ; 28.143 ;
; SD_RESETn    ; DATA[14]      ; 30.305 ; 30.305 ; 30.305 ; 30.305 ;
; SD_RESETn    ; DATA[15]      ; 29.671 ; 29.671 ; 29.671 ; 29.671 ;
; SD_RESETn    ; DTACKn        ; 19.293 ; 19.293 ; 19.293 ; 19.293 ;
; SD_RESETn    ; RAM_DATA[0]   ; 29.686 ; 30.012 ; 30.012 ; 29.686 ;
; SD_RESETn    ; RAM_DATA[1]   ; 29.595 ; 29.595 ; 29.595 ; 29.595 ;
; SD_RESETn    ; RAM_DATA[2]   ; 29.313 ; 29.313 ; 29.313 ; 29.313 ;
; SD_RESETn    ; RAM_DATA[3]   ; 29.399 ; 29.399 ; 29.399 ; 29.399 ;
; SD_RESETn    ; RAM_DATA[4]   ; 30.079 ; 30.079 ; 30.079 ; 30.079 ;
; SD_RESETn    ; RAM_DATA[5]   ; 29.055 ; 29.055 ; 29.055 ; 29.055 ;
; SD_RESETn    ; RAM_DATA[6]   ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; SD_RESETn    ; RAM_DATA[7]   ; 31.114 ; 31.114 ; 31.114 ; 31.114 ;
; SD_RESETn    ; RAM_DATA[8]   ; 31.623 ; 31.949 ; 31.949 ; 31.623 ;
; SD_RESETn    ; RAM_DATA[9]   ; 30.937 ; 30.937 ; 30.937 ; 30.937 ;
; SD_RESETn    ; RAM_DATA[10]  ; 29.680 ; 29.680 ; 29.680 ; 29.680 ;
; SD_RESETn    ; RAM_DATA[11]  ; 29.734 ; 29.734 ; 29.734 ; 29.734 ;
; SD_RESETn    ; RAM_DATA[12]  ; 29.558 ; 29.558 ; 29.558 ; 29.558 ;
; SD_RESETn    ; RAM_DATA[13]  ; 28.857 ; 28.857 ; 28.857 ; 28.857 ;
; SD_RESETn    ; RAM_DATA[14]  ; 30.312 ; 30.312 ; 30.312 ; 30.312 ;
; SD_RESETn    ; RAM_DATA[15]  ; 29.924 ; 29.924 ; 29.924 ; 29.924 ;
; UDSn         ; ACSI_RDn      ; 20.933 ; 20.933 ; 20.933 ; 20.933 ;
; UDSn         ; ACSI_WRn      ; 22.305 ; 22.305 ; 22.305 ; 22.305 ;
; UDSn         ; CA1_OUT       ; 20.218 ;        ;        ; 20.218 ;
; UDSn         ; CD[0]         ; 29.490 ; 29.490 ; 29.490 ; 29.490 ;
; UDSn         ; CD[1]         ; 29.824 ; 29.824 ; 29.824 ; 29.824 ;
; UDSn         ; CD[2]         ; 25.132 ; 25.132 ; 25.132 ; 25.132 ;
; UDSn         ; CD[3]         ; 29.575 ; 29.575 ; 29.575 ; 29.575 ;
; UDSn         ; CD[4]         ; 31.791 ; 31.791 ; 31.791 ; 31.791 ;
; UDSn         ; CD[5]         ; 31.888 ; 31.888 ; 31.888 ; 31.888 ;
; UDSn         ; CD[6]         ; 31.572 ; 31.572 ; 31.572 ; 31.572 ;
; UDSn         ; CD[7]         ; 24.751 ; 24.751 ; 24.751 ; 24.751 ;
; UDSn         ; DATA[0]       ; 29.286 ; 29.576 ; 29.576 ; 29.286 ;
; UDSn         ; DATA[1]       ; 30.363 ; 30.363 ; 30.363 ; 30.363 ;
; UDSn         ; DATA[2]       ; 29.447 ; 29.447 ; 29.447 ; 29.447 ;
; UDSn         ; DATA[3]       ; 29.600 ; 29.887 ; 29.887 ; 29.600 ;
; UDSn         ; DATA[4]       ; 28.906 ; 28.943 ; 28.943 ; 28.906 ;
; UDSn         ; DATA[5]       ; 29.860 ; 29.860 ; 29.860 ; 29.860 ;
; UDSn         ; DATA[6]       ; 28.929 ; 28.929 ; 28.929 ; 28.929 ;
; UDSn         ; DATA[7]       ; 29.061 ; 29.339 ; 29.339 ; 29.061 ;
; UDSn         ; DATA[8]       ; 30.778 ; 30.778 ; 30.778 ; 30.778 ;
; UDSn         ; DATA[9]       ; 31.171 ; 31.030 ; 31.030 ; 31.171 ;
; UDSn         ; DATA[10]      ; 31.326 ; 31.221 ; 31.221 ; 31.326 ;
; UDSn         ; DATA[11]      ; 31.187 ; 31.265 ; 31.265 ; 31.187 ;
; UDSn         ; DATA[12]      ; 30.086 ; 30.360 ; 30.360 ; 30.086 ;
; UDSn         ; DATA[13]      ; 30.715 ; 31.099 ; 31.099 ; 30.715 ;
; UDSn         ; DATA[14]      ; 32.667 ; 32.667 ; 32.667 ; 32.667 ;
; UDSn         ; DATA[15]      ; 31.908 ; 31.908 ; 31.908 ; 31.908 ;
; UDSn         ; DTACKn        ; 25.563 ; 25.563 ; 25.563 ; 25.563 ;
; UDSn         ; JOY_RHn       ; 14.641 ;        ;        ; 14.641 ;
; UDSn         ; RAM_CAS0n     ; 15.583 ;        ;        ; 15.583 ;
; UDSn         ; RAM_CAS1n     ; 14.327 ;        ;        ; 14.327 ;
; UDSn         ; RAM_DATA[0]   ; 31.373 ; 31.663 ; 31.663 ; 31.373 ;
; UDSn         ; RAM_DATA[1]   ; 31.796 ; 31.796 ; 31.796 ; 31.796 ;
; UDSn         ; RAM_DATA[2]   ; 32.030 ; 32.030 ; 32.030 ; 32.030 ;
; UDSn         ; RAM_DATA[3]   ; 31.554 ; 31.841 ; 31.841 ; 31.554 ;
; UDSn         ; RAM_DATA[4]   ; 31.799 ; 31.836 ; 31.836 ; 31.799 ;
; UDSn         ; RAM_DATA[5]   ; 31.876 ; 31.876 ; 31.876 ; 31.876 ;
; UDSn         ; RAM_DATA[6]   ; 32.515 ; 32.515 ; 32.515 ; 32.515 ;
; UDSn         ; RAM_DATA[7]   ; 32.779 ; 33.057 ; 33.057 ; 32.779 ;
; UDSn         ; RAM_DATA[8]   ; 33.006 ; 33.006 ; 33.006 ; 33.006 ;
; UDSn         ; RAM_DATA[9]   ; 32.958 ; 32.817 ; 32.817 ; 32.958 ;
; UDSn         ; RAM_DATA[10]  ; 31.673 ; 31.568 ; 31.568 ; 31.673 ;
; UDSn         ; RAM_DATA[11]  ; 32.013 ; 32.091 ; 32.091 ; 32.013 ;
; UDSn         ; RAM_DATA[12]  ; 31.498 ; 31.772 ; 31.772 ; 31.498 ;
; UDSn         ; RAM_DATA[13]  ; 31.429 ; 31.813 ; 31.813 ; 31.429 ;
; UDSn         ; RAM_DATA[14]  ; 32.674 ; 32.674 ; 32.674 ; 32.674 ;
; UDSn         ; RAM_DATA[15]  ; 32.161 ; 32.161 ; 32.161 ; 32.161 ;
; UDSn         ; RAM_DQM0H     ; 13.771 ;        ;        ; 13.771 ;
; UDSn         ; RAM_DQM1H     ; 14.022 ;        ;        ; 14.022 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 20.200 ; 20.200 ; 20.200 ; 20.200 ;
; ASn          ; ACSI_WRn      ; 21.572 ; 21.572 ; 21.572 ; 21.572 ;
; ASn          ; BUTTONn       ; 16.279 ;        ;        ; 16.279 ;
; ASn          ; CA1_OUT       ; 21.433 ;        ;        ; 21.433 ;
; ASn          ; CD[0]         ; 22.917 ; 22.917 ; 22.917 ; 22.917 ;
; ASn          ; CD[1]         ; 22.600 ; 22.600 ; 22.600 ; 22.600 ;
; ASn          ; CD[2]         ; 21.661 ; 21.582 ; 21.582 ; 21.661 ;
; ASn          ; CD[3]         ; 22.600 ; 22.600 ; 22.600 ; 22.600 ;
; ASn          ; CD[4]         ; 21.979 ; 21.979 ; 21.979 ; 21.979 ;
; ASn          ; CD[5]         ; 22.572 ; 22.572 ; 22.572 ; 22.572 ;
; ASn          ; CD[6]         ; 22.553 ; 22.553 ; 22.553 ; 22.553 ;
; ASn          ; CD[7]         ; 21.120 ; 21.120 ; 21.120 ; 21.120 ;
; ASn          ; DATA[0]       ; 18.548 ; 19.115 ; 19.115 ; 18.548 ;
; ASn          ; DATA[1]       ; 19.416 ; 19.416 ; 19.416 ; 19.416 ;
; ASn          ; DATA[2]       ; 18.561 ; 18.030 ; 18.030 ; 18.561 ;
; ASn          ; DATA[3]       ; 19.498 ; 19.062 ; 19.062 ; 19.498 ;
; ASn          ; DATA[4]       ; 18.302 ; 18.302 ; 18.302 ; 18.302 ;
; ASn          ; DATA[5]       ; 18.534 ; 18.534 ; 18.534 ; 18.534 ;
; ASn          ; DATA[6]       ; 17.959 ; 17.959 ; 17.959 ; 17.959 ;
; ASn          ; DATA[7]       ; 18.981 ; 18.535 ; 18.535 ; 18.981 ;
; ASn          ; DATA[8]       ; 19.510 ; 19.510 ; 19.510 ; 19.510 ;
; ASn          ; DATA[9]       ; 19.510 ; 19.510 ; 19.510 ; 19.510 ;
; ASn          ; DATA[10]      ; 19.846 ; 19.846 ; 19.846 ; 19.846 ;
; ASn          ; DATA[11]      ; 19.846 ; 19.846 ; 19.846 ; 19.846 ;
; ASn          ; DATA[12]      ; 19.259 ; 19.259 ; 19.259 ; 19.259 ;
; ASn          ; DATA[13]      ; 19.700 ; 19.700 ; 19.700 ; 19.700 ;
; ASn          ; DATA[14]      ; 19.912 ; 19.912 ; 19.912 ; 19.912 ;
; ASn          ; DATA[15]      ; 19.902 ; 19.902 ; 19.902 ; 19.902 ;
; ASn          ; DTACKn        ; 17.594 ; 17.594 ; 17.594 ; 17.594 ;
; ASn          ; FLASH_CEn     ; 15.131 ;        ;        ; 15.131 ;
; ASn          ; FLASH_OEn     ; 15.686 ;        ;        ; 15.686 ;
; ASn          ; IDE_CS0n      ; 13.497 ;        ;        ; 13.497 ;
; ASn          ; IDE_CS1n      ; 12.361 ;        ;        ; 12.361 ;
; ASn          ; IDE_D_EN_INn  ; 15.816 ;        ;        ; 15.816 ;
; ASn          ; IDE_D_EN_OUTn ; 15.431 ;        ;        ; 15.431 ;
; ASn          ; IDE_IORDn     ; 15.185 ;        ;        ; 15.185 ;
; ASn          ; IDE_IOWRn     ; 16.612 ;        ;        ; 16.612 ;
; ASn          ; JOY_RHn       ; 16.709 ;        ;        ; 16.709 ;
; ASn          ; JOY_RLn       ; 15.550 ;        ;        ; 15.550 ;
; ASn          ; JOY_WEn       ;        ; 15.702 ; 15.702 ;        ;
; ASn          ; JOY_WL        ;        ; 13.568 ; 13.568 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 17.975 ; 17.975 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 15.796 ; 15.796 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.442 ; 14.442 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 18.046 ; 18.046 ;        ;
; ASn          ; RAM_CAS1n     ; 16.790 ;        ;        ; 16.790 ;
; ASn          ; RAM_DATA[0]   ; 20.635 ; 21.202 ; 21.202 ; 20.635 ;
; ASn          ; RAM_DATA[1]   ; 20.849 ; 20.849 ; 20.849 ; 20.849 ;
; ASn          ; RAM_DATA[2]   ; 21.144 ; 20.613 ; 20.613 ; 21.144 ;
; ASn          ; RAM_DATA[3]   ; 21.517 ; 21.016 ; 21.016 ; 21.517 ;
; ASn          ; RAM_DATA[4]   ; 21.195 ; 21.195 ; 21.195 ; 21.195 ;
; ASn          ; RAM_DATA[5]   ; 20.550 ; 20.550 ; 20.550 ; 20.550 ;
; ASn          ; RAM_DATA[6]   ; 21.545 ; 21.545 ; 21.545 ; 21.545 ;
; ASn          ; RAM_DATA[7]   ; 22.699 ; 22.253 ; 22.253 ; 22.699 ;
; ASn          ; RAM_DATA[8]   ; 22.149 ; 23.139 ; 23.139 ; 22.149 ;
; ASn          ; RAM_DATA[9]   ; 21.797 ; 21.797 ; 21.797 ; 21.797 ;
; ASn          ; RAM_DATA[10]  ; 20.832 ; 20.832 ; 20.832 ; 20.832 ;
; ASn          ; RAM_DATA[11]  ; 21.311 ; 21.311 ; 21.311 ; 21.311 ;
; ASn          ; RAM_DATA[12]  ; 20.671 ; 20.671 ; 20.671 ; 20.671 ;
; ASn          ; RAM_DATA[13]  ; 20.414 ; 20.414 ; 20.414 ; 20.414 ;
; ASn          ; RAM_DATA[14]  ; 20.677 ; 20.677 ; 20.677 ; 20.677 ;
; ASn          ; RAM_DATA[15]  ; 21.257 ; 21.257 ; 21.257 ; 21.257 ;
; ASn          ; RAM_DQM0H     ;        ; 17.101 ; 17.101 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.357 ; 17.357 ;        ;
; ASn          ; RAM_DQM1H     ; 17.343 ;        ;        ; 17.343 ;
; ASn          ; RAM_DQM1L     ; 16.894 ;        ;        ; 16.894 ;
; ASn          ; RAM_RAS0n     ;        ; 18.078 ; 18.078 ;        ;
; ASn          ; RAM_RAS1n     ; 17.921 ;        ;        ; 17.921 ;
; ASn          ; ROM0n         ; 15.912 ;        ;        ; 15.912 ;
; ASn          ; ROM1n         ; 14.842 ;        ;        ; 14.842 ;
; ASn          ; ROM2n         ; 14.372 ;        ;        ; 14.372 ;
; ASn          ; ROM3n         ; 14.938 ;        ;        ; 14.938 ;
; ASn          ; ROM4n         ; 14.635 ;        ;        ; 14.635 ;
; ASn          ; ROM5n         ; 16.899 ;        ;        ; 16.899 ;
; ASn          ; ROM6n         ; 14.037 ;        ;        ; 14.037 ;
; COM_CTS      ; DATA[2]       ;        ; 21.255 ; 21.255 ;        ;
; COM_CTS      ; DATA[10]      ;        ; 23.591 ; 23.591 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 23.838 ; 23.838 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 23.938 ; 23.938 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 23.020 ; 23.020 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 22.748 ; 22.748 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 24.453 ; 24.453 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 24.535 ; 24.535 ;        ;
; COM_RI       ; DATA[6]       ;        ; 20.562 ; 20.562 ;        ;
; COM_RI       ; DATA[14]      ; 25.036 ; 25.036 ; 25.036 ; 25.036 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.148 ; 24.148 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 25.043 ; 25.043 ; 25.043 ; 25.043 ;
; CONFIG[1]    ; DATA[7]       ; 23.007 ; 23.007 ; 23.007 ; 23.007 ;
; CONFIG[1]    ; DATA[15]      ; 25.610 ; 25.610 ; 25.610 ; 25.610 ;
; CONFIG[1]    ; HSYNC         ; 14.353 ; 14.353 ; 14.353 ; 14.353 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.725 ; 26.725 ; 26.725 ; 26.725 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 17.617 ; 17.961 ; 17.961 ; 17.617 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 17.871 ; 17.871 ; 17.871 ; 17.871 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.805 ; 17.056 ; 17.056 ; 16.805 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 17.087 ; 17.136 ; 17.136 ; 17.087 ;
; CONFIG[1]    ; VSYNC         ; 14.686 ; 14.686 ; 14.686 ; 14.686 ;
; CONFIG[2]    ; DATA[7]       ; 23.109 ; 23.109 ; 23.109 ; 23.109 ;
; CONFIG[2]    ; DATA[15]      ; 25.712 ; 25.712 ; 25.712 ; 25.712 ;
; CONFIG[2]    ; HSYNC         ; 14.455 ; 14.455 ; 14.455 ; 14.455 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.827 ; 26.827 ; 26.827 ; 26.827 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 18.027 ; 17.683 ; 17.683 ; 18.027 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.937 ; 17.937 ; 17.937 ; 17.937 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.122 ; 16.871 ; 16.871 ; 17.122 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 17.202 ; 17.153 ; 17.153 ; 17.202 ;
; CONFIG[2]    ; VSYNC         ; 14.783 ; 14.783 ; 14.783 ; 14.783 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.201 ; 17.201 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.783 ; 14.783 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 27.903 ; 27.903 ; 27.903 ; 27.903 ;
; CONFIG[5]    ; ACSI_WRn      ; 29.275 ; 29.275 ; 29.275 ; 29.275 ;
; CONFIG[5]    ; BUTTONn       ; 24.733 ; 24.477 ; 24.477 ; 24.733 ;
; CONFIG[5]    ; CA1_OUT       ; 29.392 ; 29.136 ; 29.136 ; 29.392 ;
; CONFIG[5]    ; CD[0]         ; 30.620 ; 30.620 ; 30.620 ; 30.620 ;
; CONFIG[5]    ; CD[1]         ; 30.303 ; 30.303 ; 30.303 ; 30.303 ;
; CONFIG[5]    ; CD[2]         ; 29.285 ; 29.364 ; 29.364 ; 29.285 ;
; CONFIG[5]    ; CD[3]         ; 30.303 ; 30.303 ; 30.303 ; 30.303 ;
; CONFIG[5]    ; CD[4]         ; 29.682 ; 29.682 ; 29.682 ; 29.682 ;
; CONFIG[5]    ; CD[5]         ; 30.275 ; 30.275 ; 30.275 ; 30.275 ;
; CONFIG[5]    ; CD[6]         ; 30.256 ; 30.256 ; 30.256 ; 30.256 ;
; CONFIG[5]    ; CD[7]         ; 28.823 ; 28.823 ; 28.823 ; 28.823 ;
; CONFIG[5]    ; DATA[0]       ; 24.308 ; 24.308 ; 24.308 ; 24.308 ;
; CONFIG[5]    ; DATA[1]       ; 24.308 ; 24.308 ; 24.308 ; 24.308 ;
; CONFIG[5]    ; DATA[2]       ; 23.961 ; 23.961 ; 23.961 ; 23.961 ;
; CONFIG[5]    ; DATA[3]       ; 23.961 ; 23.961 ; 23.961 ; 23.961 ;
; CONFIG[5]    ; DATA[4]       ; 23.950 ; 23.950 ; 23.950 ; 23.950 ;
; CONFIG[5]    ; DATA[5]       ; 23.950 ; 23.950 ; 23.950 ; 23.950 ;
; CONFIG[5]    ; DATA[6]       ; 23.590 ; 23.590 ; 23.590 ; 23.590 ;
; CONFIG[5]    ; DATA[7]       ; 23.580 ; 23.580 ; 23.580 ; 23.580 ;
; CONFIG[5]    ; DATA[8]       ; 23.973 ; 23.973 ; 23.973 ; 23.973 ;
; CONFIG[5]    ; DATA[9]       ; 23.973 ; 23.973 ; 23.973 ; 23.973 ;
; CONFIG[5]    ; DATA[10]      ; 24.309 ; 24.309 ; 24.309 ; 24.309 ;
; CONFIG[5]    ; DATA[11]      ; 24.309 ; 24.309 ; 24.309 ; 24.309 ;
; CONFIG[5]    ; DATA[12]      ; 24.369 ; 24.369 ; 24.369 ; 24.369 ;
; CONFIG[5]    ; DATA[13]      ; 24.369 ; 24.369 ; 24.369 ; 24.369 ;
; CONFIG[5]    ; DATA[14]      ; 24.375 ; 24.375 ; 24.375 ; 24.375 ;
; CONFIG[5]    ; DATA[15]      ; 24.365 ; 24.365 ; 24.365 ; 24.365 ;
; CONFIG[5]    ; DTACKn        ; 25.646 ; 25.646 ; 25.646 ; 25.646 ;
; CONFIG[5]    ; FLASH_CEn     ; 21.058 ; 21.314 ; 21.314 ; 21.058 ;
; CONFIG[5]    ; FLASH_OEn     ; 21.613 ; 21.869 ; 21.869 ; 21.613 ;
; CONFIG[5]    ; IDE_CS0n      ; 23.344 ; 23.063 ; 23.063 ; 23.344 ;
; CONFIG[5]    ; IDE_CS1n      ; 22.380 ; 22.099 ; 22.099 ; 22.380 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 23.008 ; 22.727 ; 22.727 ; 23.008 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 22.623 ; 22.342 ; 22.342 ; 22.623 ;
; CONFIG[5]    ; IDE_IORDn     ; 22.377 ; 22.096 ; 22.096 ; 22.377 ;
; CONFIG[5]    ; IDE_IOWRn     ; 23.804 ; 23.523 ; 23.523 ; 23.804 ;
; CONFIG[5]    ; JOY_RHn       ; 25.749 ; 25.493 ; 25.493 ; 25.749 ;
; CONFIG[5]    ; JOY_RLn       ; 24.324 ; 24.068 ; 24.068 ; 24.324 ;
; CONFIG[5]    ; JOY_WEn       ; 24.220 ; 24.476 ; 24.476 ; 24.220 ;
; CONFIG[5]    ; JOY_WL        ; 25.056 ; 25.312 ; 25.312 ; 25.056 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 24.087 ; 21.707 ; 21.707 ; 24.087 ;
; CONFIG[5]    ; RAM_BA[0]     ; 21.908 ; 19.528 ; 19.528 ; 21.908 ;
; CONFIG[5]    ; RAM_BA[1]     ; 20.137 ; 18.174 ; 18.174 ; 20.137 ;
; CONFIG[5]    ; RAM_CAS0n     ; 23.203 ; 21.778 ; 21.778 ; 23.203 ;
; CONFIG[5]    ; RAM_CAS1n     ; 20.522 ; 21.948 ; 21.948 ; 20.522 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 27.373 ; 27.335 ; 27.335 ; 27.373 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 27.642 ; 27.604 ; 27.604 ; 27.642 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 28.036 ; 28.317 ; 28.317 ; 28.036 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 28.254 ; 28.216 ; 28.216 ; 28.254 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 28.448 ; 28.410 ; 28.410 ; 28.448 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 27.973 ; 27.973 ; 27.973 ; 27.973 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 28.967 ; 28.968 ; 28.968 ; 28.967 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 28.227 ; 28.265 ; 28.265 ; 28.227 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 29.744 ; 29.572 ; 29.572 ; 29.744 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 28.781 ; 28.743 ; 28.743 ; 28.781 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 27.162 ; 27.200 ; 27.200 ; 27.162 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 27.561 ; 27.599 ; 27.599 ; 27.561 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 28.094 ; 28.094 ; 28.094 ; 28.094 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 27.542 ; 27.580 ; 27.580 ; 27.542 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 26.529 ; 26.529 ; 26.529 ; 26.529 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 26.547 ; 26.547 ; 26.547 ; 26.547 ;
; CONFIG[5]    ; RAM_DQM0H     ; 22.258 ; 20.833 ; 20.833 ; 22.258 ;
; CONFIG[5]    ; RAM_DQM0L     ; 22.514 ; 21.089 ; 21.089 ; 22.514 ;
; CONFIG[5]    ; RAM_DQM1H     ; 21.075 ; 22.501 ; 22.501 ; 21.075 ;
; CONFIG[5]    ; RAM_DQM1L     ; 20.626 ; 22.052 ; 22.052 ; 20.626 ;
; CONFIG[5]    ; RAM_RAS0n     ; 23.236 ; 21.810 ; 21.810 ; 23.236 ;
; CONFIG[5]    ; RAM_RAS1n     ; 21.653 ; 23.079 ; 23.079 ; 21.653 ;
; CONFIG[5]    ; ROM0n         ; 19.567 ; 19.311 ; 19.311 ; 19.567 ;
; CONFIG[5]    ; ROM1n         ; 20.262 ; 20.006 ; 20.006 ; 20.262 ;
; CONFIG[5]    ; ROM2n         ; 20.299 ; 20.555 ; 20.555 ; 20.299 ;
; CONFIG[5]    ; ROM3n         ; 20.920 ; 20.664 ; 20.664 ; 20.920 ;
; CONFIG[5]    ; ROM4n         ; 20.271 ; 20.373 ; 20.373 ; 20.271 ;
; CONFIG[5]    ; ROM5n         ; 20.547 ; 20.547 ; 20.547 ; 20.547 ;
; CONFIG[5]    ; ROM6n         ; 20.026 ; 19.770 ; 19.770 ; 20.026 ;
; CONFIG[6]    ; DATA[0]       ; 24.520 ; 24.520 ; 24.520 ; 24.520 ;
; CONFIG[6]    ; DATA[1]       ; 26.171 ; 26.171 ; 26.171 ; 26.171 ;
; CONFIG[6]    ; DATA[2]       ; 24.971 ; 24.971 ; 24.971 ; 24.971 ;
; CONFIG[6]    ; DATA[3]       ; 25.815 ; 25.815 ; 25.815 ; 25.815 ;
; CONFIG[6]    ; DATA[4]       ; 25.151 ; 25.151 ; 25.151 ; 25.151 ;
; CONFIG[6]    ; DATA[5]       ; 25.071 ; 25.071 ; 25.071 ; 25.071 ;
; CONFIG[6]    ; DATA[6]       ; 24.382 ; 24.382 ; 24.382 ; 24.382 ;
; CONFIG[6]    ; DATA[7]       ; 24.784 ; 24.784 ; 24.784 ; 24.784 ;
; CONFIG[6]    ; DATA[8]       ; 25.755 ; 25.986 ; 25.986 ; 25.755 ;
; CONFIG[6]    ; DATA[9]       ; 25.884 ; 25.884 ; 25.884 ; 25.884 ;
; CONFIG[6]    ; DATA[10]      ; 27.315 ; 27.702 ; 27.702 ; 27.315 ;
; CONFIG[6]    ; DATA[11]      ; 26.600 ; 26.656 ; 26.656 ; 26.600 ;
; CONFIG[6]    ; DATA[12]      ; 25.709 ; 25.055 ; 25.055 ; 25.709 ;
; CONFIG[6]    ; DATA[13]      ; 25.571 ; 25.836 ; 25.836 ; 25.571 ;
; CONFIG[6]    ; DATA[14]      ; 24.533 ; 24.533 ; 24.533 ; 24.533 ;
; CONFIG[6]    ; DATA[15]      ; 23.956 ; 23.956 ; 23.956 ; 23.956 ;
; CONFIG[6]    ; DTACKn        ; 20.840 ; 20.840 ; 20.840 ; 20.840 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.016 ; 15.016 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.105 ; 14.105 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 16.994 ; 16.252 ; 16.252 ; 16.994 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.549 ; 16.807 ; 16.807 ; 17.549 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 26.607 ; 26.607 ; 26.607 ; 26.607 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 27.604 ; 27.604 ; 27.604 ; 27.604 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 27.554 ; 27.554 ; 27.554 ; 27.554 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 27.769 ; 27.769 ; 27.769 ; 27.769 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 28.044 ; 28.044 ; 28.044 ; 28.044 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.087 ; 27.087 ; 27.087 ; 27.087 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 27.968 ; 27.968 ; 27.968 ; 27.968 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 28.502 ; 28.502 ; 28.502 ; 28.502 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 27.983 ; 28.214 ; 28.214 ; 27.983 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 27.671 ; 27.671 ; 27.671 ; 27.671 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 27.662 ; 28.049 ; 28.049 ; 27.662 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 27.426 ; 27.482 ; 27.482 ; 27.426 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 27.121 ; 26.467 ; 26.467 ; 27.121 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 26.285 ; 26.550 ; 26.550 ; 26.285 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 24.540 ; 24.540 ; 24.540 ; 24.540 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.209 ; 24.209 ; 24.209 ; 24.209 ;
; CONFIG[6]    ; ROM2n         ; 16.235 ; 15.493 ; 15.493 ; 16.235 ;
; CRT_PIN3     ; DATA[7]       ; 18.241 ; 18.241 ; 18.241 ; 18.241 ;
; CRT_PIN3     ; DATA[15]      ; 20.844 ; 20.844 ; 20.844 ; 20.844 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.959 ; 21.959 ; 21.959 ; 21.959 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 13.325 ; 13.669 ; 13.669 ; 13.325 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.579 ; 13.579 ; 13.579 ; 13.579 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.513 ; 12.764 ; 12.764 ; 12.513 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 12.795 ; 12.844 ; 12.844 ; 12.795 ;
; DATA[0]      ; DATA[0]       ; 16.041 ;        ;        ; 16.041 ;
; DATA[0]      ; RAM_DATA[0]   ; 18.128 ;        ;        ; 18.128 ;
; DATA[1]      ; DATA[1]       ; 15.578 ;        ;        ; 15.578 ;
; DATA[1]      ; RAM_DATA[1]   ; 17.011 ;        ;        ; 17.011 ;
; DATA[2]      ; DATA[2]       ; 14.490 ;        ;        ; 14.490 ;
; DATA[2]      ; RAM_DATA[2]   ; 17.073 ;        ;        ; 17.073 ;
; DATA[3]      ; DATA[3]       ; 14.154 ;        ;        ; 14.154 ;
; DATA[3]      ; RAM_DATA[3]   ; 16.108 ;        ;        ; 16.108 ;
; DATA[4]      ; DATA[4]       ; 15.929 ;        ;        ; 15.929 ;
; DATA[4]      ; RAM_DATA[4]   ; 18.822 ;        ;        ; 18.822 ;
; DATA[5]      ; DATA[5]       ; 16.629 ;        ;        ; 16.629 ;
; DATA[5]      ; RAM_DATA[5]   ; 18.645 ;        ;        ; 18.645 ;
; DATA[6]      ; DATA[6]       ; 13.654 ;        ;        ; 13.654 ;
; DATA[6]      ; RAM_DATA[6]   ; 17.240 ;        ;        ; 17.240 ;
; DATA[7]      ; DATA[7]       ; 13.365 ;        ;        ; 13.365 ;
; DATA[7]      ; RAM_DATA[7]   ; 17.083 ;        ;        ; 17.083 ;
; DATA[8]      ; DATA[8]       ; 16.784 ;        ;        ; 16.784 ;
; DATA[8]      ; RAM_DATA[8]   ; 19.012 ;        ;        ; 19.012 ;
; DATA[9]      ; DATA[9]       ; 15.251 ;        ;        ; 15.251 ;
; DATA[9]      ; RAM_DATA[9]   ; 17.038 ;        ;        ; 17.038 ;
; DATA[10]     ; DATA[10]      ; 15.983 ;        ;        ; 15.983 ;
; DATA[10]     ; RAM_DATA[10]  ; 16.330 ;        ;        ; 16.330 ;
; DATA[11]     ; DATA[11]      ; 15.544 ;        ;        ; 15.544 ;
; DATA[11]     ; RAM_DATA[11]  ; 16.370 ;        ;        ; 16.370 ;
; DATA[12]     ; DATA[12]      ; 14.946 ;        ;        ; 14.946 ;
; DATA[12]     ; RAM_DATA[12]  ; 16.358 ;        ;        ; 16.358 ;
; DATA[13]     ; DATA[13]      ; 15.277 ;        ;        ; 15.277 ;
; DATA[13]     ; RAM_DATA[13]  ; 15.991 ;        ;        ; 15.991 ;
; DATA[14]     ; DATA[14]      ; 15.689 ;        ;        ; 15.689 ;
; DATA[14]     ; RAM_DATA[14]  ; 15.696 ;        ;        ; 15.696 ;
; DATA[15]     ; DATA[15]      ; 15.063 ;        ;        ; 15.063 ;
; DATA[15]     ; RAM_DATA[15]  ; 15.316 ;        ;        ; 15.316 ;
; FC[0]        ; ACSI_RDn      ; 17.951 ; 17.951 ; 17.951 ; 17.951 ;
; FC[0]        ; ACSI_WRn      ; 19.323 ; 19.323 ; 19.323 ; 19.323 ;
; FC[0]        ; BUTTONn       ; 17.123 ; 17.123 ; 17.123 ; 17.123 ;
; FC[0]        ; CA1_OUT       ; 19.184 ; 19.184 ; 19.184 ; 19.184 ;
; FC[0]        ; CD[0]         ; 20.668 ; 20.668 ; 20.668 ; 20.668 ;
; FC[0]        ; CD[1]         ; 20.351 ; 20.351 ; 20.351 ; 20.351 ;
; FC[0]        ; CD[2]         ; 19.333 ; 19.333 ; 19.333 ; 19.333 ;
; FC[0]        ; CD[3]         ; 20.351 ; 20.351 ; 20.351 ; 20.351 ;
; FC[0]        ; CD[4]         ; 19.730 ; 19.730 ; 19.730 ; 19.730 ;
; FC[0]        ; CD[5]         ; 20.323 ; 20.323 ; 20.323 ; 20.323 ;
; FC[0]        ; CD[6]         ; 20.304 ; 20.304 ; 20.304 ; 20.304 ;
; FC[0]        ; CD[7]         ; 18.871 ; 18.871 ; 18.871 ; 18.871 ;
; FC[0]        ; DATA[0]       ; 19.619 ; 19.619 ; 19.619 ; 19.619 ;
; FC[0]        ; DATA[1]       ; 19.865 ; 19.865 ; 19.865 ; 19.865 ;
; FC[0]        ; DATA[2]       ; 18.456 ; 18.456 ; 18.456 ; 18.456 ;
; FC[0]        ; DATA[3]       ; 18.504 ; 18.504 ; 18.504 ; 18.504 ;
; FC[0]        ; DATA[4]       ; 18.545 ; 18.545 ; 18.545 ; 18.545 ;
; FC[0]        ; DATA[5]       ; 19.321 ; 19.321 ; 19.321 ; 19.321 ;
; FC[0]        ; DATA[6]       ; 18.008 ; 18.008 ; 18.008 ; 18.008 ;
; FC[0]        ; DATA[7]       ; 18.288 ; 18.288 ; 18.288 ; 18.288 ;
; FC[0]        ; DATA[8]       ; 20.731 ; 20.731 ; 20.731 ; 20.731 ;
; FC[0]        ; DATA[9]       ; 20.301 ; 20.301 ; 20.301 ; 20.301 ;
; FC[0]        ; DATA[10]      ; 20.901 ; 20.901 ; 20.901 ; 20.901 ;
; FC[0]        ; DATA[11]      ; 20.163 ; 20.163 ; 20.163 ; 20.163 ;
; FC[0]        ; DATA[12]      ; 19.621 ; 19.621 ; 19.621 ; 19.621 ;
; FC[0]        ; DATA[13]      ; 20.060 ; 20.060 ; 20.060 ; 20.060 ;
; FC[0]        ; DATA[14]      ; 21.028 ; 21.028 ; 21.028 ; 21.028 ;
; FC[0]        ; DATA[15]      ; 20.451 ; 20.451 ; 20.451 ; 20.451 ;
; FC[0]        ; DTACKn        ; 17.178 ; 17.178 ; 17.178 ; 17.178 ;
; FC[0]        ; FLASH_CEn     ; 16.824 ; 16.824 ; 16.824 ; 16.824 ;
; FC[0]        ; FLASH_OEn     ; 17.379 ; 17.379 ; 17.379 ; 17.379 ;
; FC[0]        ; JOY_RHn       ; 19.551 ; 19.551 ; 19.551 ; 19.551 ;
; FC[0]        ; JOY_RLn       ; 18.392 ; 18.392 ; 18.392 ; 18.392 ;
; FC[0]        ; JOY_WEn       ; 18.544 ; 18.544 ; 18.544 ; 18.544 ;
; FC[0]        ; JOY_WL        ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; FC[0]        ; RAM_ADR[8]    ; 19.506 ; 19.506 ; 19.506 ; 19.506 ;
; FC[0]        ; RAM_BA[0]     ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; FC[0]        ; RAM_BA[1]     ; 15.973 ; 15.973 ; 15.973 ; 15.973 ;
; FC[0]        ; RAM_CAS0n     ; 19.577 ; 19.577 ; 19.577 ; 19.577 ;
; FC[0]        ; RAM_CAS1n     ; 18.321 ; 18.321 ; 18.321 ; 18.321 ;
; FC[0]        ; RAM_DATA[0]   ; 21.706 ; 21.706 ; 21.706 ; 21.706 ;
; FC[0]        ; RAM_DATA[1]   ; 21.298 ; 21.298 ; 21.298 ; 21.298 ;
; FC[0]        ; RAM_DATA[2]   ; 21.039 ; 21.039 ; 21.039 ; 21.039 ;
; FC[0]        ; RAM_DATA[3]   ; 20.458 ; 20.458 ; 20.458 ; 20.458 ;
; FC[0]        ; RAM_DATA[4]   ; 21.438 ; 21.438 ; 21.438 ; 21.438 ;
; FC[0]        ; RAM_DATA[5]   ; 21.337 ; 21.337 ; 21.337 ; 21.337 ;
; FC[0]        ; RAM_DATA[6]   ; 21.594 ; 21.594 ; 21.594 ; 21.594 ;
; FC[0]        ; RAM_DATA[7]   ; 22.006 ; 22.006 ; 22.006 ; 22.006 ;
; FC[0]        ; RAM_DATA[8]   ; 22.959 ; 22.959 ; 22.959 ; 22.959 ;
; FC[0]        ; RAM_DATA[9]   ; 22.088 ; 22.088 ; 22.088 ; 22.088 ;
; FC[0]        ; RAM_DATA[10]  ; 21.248 ; 21.248 ; 21.248 ; 21.248 ;
; FC[0]        ; RAM_DATA[11]  ; 20.989 ; 20.989 ; 20.989 ; 20.989 ;
; FC[0]        ; RAM_DATA[12]  ; 21.033 ; 21.033 ; 21.033 ; 21.033 ;
; FC[0]        ; RAM_DATA[13]  ; 20.774 ; 20.774 ; 20.774 ; 20.774 ;
; FC[0]        ; RAM_DATA[14]  ; 21.035 ; 21.035 ; 21.035 ; 21.035 ;
; FC[0]        ; RAM_DATA[15]  ; 20.704 ; 20.704 ; 20.704 ; 20.704 ;
; FC[0]        ; RAM_DQM0H     ; 18.632 ; 18.632 ; 18.632 ; 18.632 ;
; FC[0]        ; RAM_DQM0L     ; 18.888 ; 18.888 ; 18.888 ; 18.888 ;
; FC[0]        ; RAM_DQM1H     ; 18.874 ; 18.874 ; 18.874 ; 18.874 ;
; FC[0]        ; RAM_DQM1L     ; 18.425 ; 18.425 ; 18.425 ; 18.425 ;
; FC[0]        ; RAM_RAS0n     ; 19.609 ; 19.609 ; 19.609 ; 19.609 ;
; FC[0]        ; RAM_RAS1n     ; 19.452 ; 19.452 ; 19.452 ; 19.452 ;
; FC[0]        ; ROM0n         ; 15.320 ; 15.320 ; 15.320 ; 15.320 ;
; FC[0]        ; ROM1n         ; 14.250 ; 14.250 ; 14.250 ; 14.250 ;
; FC[0]        ; ROM2n         ; 16.065 ; 16.065 ; 16.065 ; 16.065 ;
; FC[0]        ; ROM3n         ; 14.346 ; 14.346 ; 14.346 ; 14.346 ;
; FC[0]        ; ROM4n         ; 14.043 ; 14.043 ; 14.043 ; 14.043 ;
; FC[0]        ; ROM5n         ; 16.307 ; 16.307 ; 16.307 ; 16.307 ;
; FC[0]        ; ROM6n         ; 13.445 ; 13.445 ; 13.445 ; 13.445 ;
; FC[1]        ; ACSI_RDn      ; 17.495 ; 17.495 ; 17.495 ; 17.495 ;
; FC[1]        ; ACSI_WRn      ; 18.867 ; 18.867 ; 18.867 ; 18.867 ;
; FC[1]        ; BUTTONn       ; 17.157 ; 17.157 ; 17.157 ; 17.157 ;
; FC[1]        ; CA1_OUT       ; 18.728 ; 18.728 ; 18.728 ; 18.728 ;
; FC[1]        ; CD[0]         ; 20.212 ; 20.212 ; 20.212 ; 20.212 ;
; FC[1]        ; CD[1]         ; 19.895 ; 19.895 ; 19.895 ; 19.895 ;
; FC[1]        ; CD[2]         ; 18.877 ; 18.877 ; 18.877 ; 18.877 ;
; FC[1]        ; CD[3]         ; 19.895 ; 19.895 ; 19.895 ; 19.895 ;
; FC[1]        ; CD[4]         ; 19.274 ; 19.274 ; 19.274 ; 19.274 ;
; FC[1]        ; CD[5]         ; 19.867 ; 19.867 ; 19.867 ; 19.867 ;
; FC[1]        ; CD[6]         ; 19.848 ; 19.848 ; 19.848 ; 19.848 ;
; FC[1]        ; CD[7]         ; 18.415 ; 18.415 ; 18.415 ; 18.415 ;
; FC[1]        ; DATA[0]       ; 19.230 ; 19.230 ; 19.230 ; 19.230 ;
; FC[1]        ; DATA[1]       ; 19.476 ; 19.476 ; 19.476 ; 19.476 ;
; FC[1]        ; DATA[2]       ; 18.067 ; 18.067 ; 18.067 ; 18.067 ;
; FC[1]        ; DATA[3]       ; 18.115 ; 18.115 ; 18.115 ; 18.115 ;
; FC[1]        ; DATA[4]       ; 18.156 ; 18.156 ; 18.156 ; 18.156 ;
; FC[1]        ; DATA[5]       ; 18.932 ; 18.932 ; 18.932 ; 18.932 ;
; FC[1]        ; DATA[6]       ; 17.619 ; 17.619 ; 17.619 ; 17.619 ;
; FC[1]        ; DATA[7]       ; 17.899 ; 17.899 ; 17.899 ; 17.899 ;
; FC[1]        ; DATA[8]       ; 20.342 ; 20.342 ; 20.342 ; 20.342 ;
; FC[1]        ; DATA[9]       ; 19.912 ; 19.912 ; 19.912 ; 19.912 ;
; FC[1]        ; DATA[10]      ; 20.512 ; 20.512 ; 20.512 ; 20.512 ;
; FC[1]        ; DATA[11]      ; 19.774 ; 19.774 ; 19.774 ; 19.774 ;
; FC[1]        ; DATA[12]      ; 19.232 ; 19.232 ; 19.232 ; 19.232 ;
; FC[1]        ; DATA[13]      ; 19.671 ; 19.671 ; 19.671 ; 19.671 ;
; FC[1]        ; DATA[14]      ; 20.639 ; 20.639 ; 20.639 ; 20.639 ;
; FC[1]        ; DATA[15]      ; 20.062 ; 20.062 ; 20.062 ; 20.062 ;
; FC[1]        ; DTACKn        ; 16.722 ; 16.722 ; 16.722 ; 16.722 ;
; FC[1]        ; FLASH_CEn     ; 16.858 ; 16.858 ; 16.858 ; 16.858 ;
; FC[1]        ; FLASH_OEn     ; 17.413 ; 17.413 ; 17.413 ; 17.413 ;
; FC[1]        ; JOY_RHn       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; FC[1]        ; JOY_RLn       ; 17.936 ; 17.936 ; 17.936 ; 17.936 ;
; FC[1]        ; JOY_WEn       ; 18.088 ; 18.088 ; 18.088 ; 18.088 ;
; FC[1]        ; JOY_WL        ; 15.954 ; 15.954 ; 15.954 ; 15.954 ;
; FC[1]        ; RAM_ADR[8]    ; 19.540 ; 19.540 ; 19.540 ; 19.540 ;
; FC[1]        ; RAM_BA[0]     ; 17.361 ; 17.361 ; 17.361 ; 17.361 ;
; FC[1]        ; RAM_BA[1]     ; 16.007 ; 16.007 ; 16.007 ; 16.007 ;
; FC[1]        ; RAM_CAS0n     ; 19.611 ; 19.611 ; 19.611 ; 19.611 ;
; FC[1]        ; RAM_CAS1n     ; 18.355 ; 18.355 ; 18.355 ; 18.355 ;
; FC[1]        ; RAM_DATA[0]   ; 21.317 ; 21.317 ; 21.317 ; 21.317 ;
; FC[1]        ; RAM_DATA[1]   ; 20.909 ; 20.909 ; 20.909 ; 20.909 ;
; FC[1]        ; RAM_DATA[2]   ; 20.650 ; 20.650 ; 20.650 ; 20.650 ;
; FC[1]        ; RAM_DATA[3]   ; 20.069 ; 20.069 ; 20.069 ; 20.069 ;
; FC[1]        ; RAM_DATA[4]   ; 21.049 ; 21.049 ; 21.049 ; 21.049 ;
; FC[1]        ; RAM_DATA[5]   ; 20.948 ; 20.948 ; 20.948 ; 20.948 ;
; FC[1]        ; RAM_DATA[6]   ; 21.205 ; 21.205 ; 21.205 ; 21.205 ;
; FC[1]        ; RAM_DATA[7]   ; 21.617 ; 21.617 ; 21.617 ; 21.617 ;
; FC[1]        ; RAM_DATA[8]   ; 22.570 ; 22.570 ; 22.570 ; 22.570 ;
; FC[1]        ; RAM_DATA[9]   ; 21.699 ; 21.699 ; 21.699 ; 21.699 ;
; FC[1]        ; RAM_DATA[10]  ; 20.859 ; 20.859 ; 20.859 ; 20.859 ;
; FC[1]        ; RAM_DATA[11]  ; 20.600 ; 20.600 ; 20.600 ; 20.600 ;
; FC[1]        ; RAM_DATA[12]  ; 20.644 ; 20.644 ; 20.644 ; 20.644 ;
; FC[1]        ; RAM_DATA[13]  ; 20.385 ; 20.385 ; 20.385 ; 20.385 ;
; FC[1]        ; RAM_DATA[14]  ; 20.646 ; 20.646 ; 20.646 ; 20.646 ;
; FC[1]        ; RAM_DATA[15]  ; 20.315 ; 20.315 ; 20.315 ; 20.315 ;
; FC[1]        ; RAM_DQM0H     ; 18.666 ; 18.666 ; 18.666 ; 18.666 ;
; FC[1]        ; RAM_DQM0L     ; 18.922 ; 18.922 ; 18.922 ; 18.922 ;
; FC[1]        ; RAM_DQM1H     ; 18.908 ; 18.908 ; 18.908 ; 18.908 ;
; FC[1]        ; RAM_DQM1L     ; 18.459 ; 18.459 ; 18.459 ; 18.459 ;
; FC[1]        ; RAM_RAS0n     ; 19.643 ; 19.643 ; 19.643 ; 19.643 ;
; FC[1]        ; RAM_RAS1n     ; 19.486 ; 19.486 ; 19.486 ; 19.486 ;
; FC[1]        ; ROM0n         ; 15.355 ; 15.355 ; 15.355 ; 15.355 ;
; FC[1]        ; ROM1n         ; 14.285 ; 14.285 ; 14.285 ; 14.285 ;
; FC[1]        ; ROM2n         ; 16.099 ; 16.099 ; 16.099 ; 16.099 ;
; FC[1]        ; ROM3n         ; 14.381 ; 14.381 ; 14.381 ; 14.381 ;
; FC[1]        ; ROM4n         ; 14.078 ; 14.078 ; 14.078 ; 14.078 ;
; FC[1]        ; ROM5n         ; 16.342 ; 16.342 ; 16.342 ; 16.342 ;
; FC[1]        ; ROM6n         ; 13.480 ; 13.480 ; 13.480 ; 13.480 ;
; FC[2]        ; ACSI_RDn      ; 17.794 ; 17.794 ; 17.794 ; 17.794 ;
; FC[2]        ; ACSI_WRn      ; 19.166 ; 19.166 ; 19.166 ; 19.166 ;
; FC[2]        ; CA1_OUT       ;        ; 19.027 ; 19.027 ;        ;
; FC[2]        ; CD[0]         ; 20.511 ; 20.511 ; 20.511 ; 20.511 ;
; FC[2]        ; CD[1]         ; 20.194 ; 20.194 ; 20.194 ; 20.194 ;
; FC[2]        ; CD[2]         ; 19.176 ; 19.255 ; 19.255 ; 19.176 ;
; FC[2]        ; CD[3]         ; 20.194 ; 20.194 ; 20.194 ; 20.194 ;
; FC[2]        ; CD[4]         ; 19.573 ; 19.573 ; 19.573 ; 19.573 ;
; FC[2]        ; CD[5]         ; 20.166 ; 20.166 ; 20.166 ; 20.166 ;
; FC[2]        ; CD[6]         ; 20.147 ; 20.147 ; 20.147 ; 20.147 ;
; FC[2]        ; CD[7]         ; 18.714 ; 18.714 ; 18.714 ; 18.714 ;
; FC[2]        ; DATA[0]       ; 19.993 ; 19.686 ; 19.686 ; 19.993 ;
; FC[2]        ; DATA[1]       ; 19.972 ; 19.932 ; 19.932 ; 19.972 ;
; FC[2]        ; DATA[2]       ; 19.633 ; 19.589 ; 19.589 ; 19.633 ;
; FC[2]        ; DATA[3]       ; 21.063 ; 19.657 ; 19.657 ; 21.063 ;
; FC[2]        ; DATA[4]       ; 19.986 ; 19.124 ; 19.124 ; 19.986 ;
; FC[2]        ; DATA[5]       ; 20.806 ; 20.140 ; 20.140 ; 20.806 ;
; FC[2]        ; DATA[6]       ; 19.605 ; 19.161 ; 19.161 ; 19.605 ;
; FC[2]        ; DATA[7]       ; 19.997 ; 19.024 ; 19.024 ; 19.997 ;
; FC[2]        ; DATA[8]       ; 24.350 ; 21.085 ; 21.085 ; 24.350 ;
; FC[2]        ; DATA[9]       ; 23.449 ; 20.563 ; 20.563 ; 23.449 ;
; FC[2]        ; DATA[10]      ; 23.924 ; 21.963 ; 21.963 ; 23.924 ;
; FC[2]        ; DATA[11]      ; 23.924 ; 21.297 ; 21.297 ; 23.924 ;
; FC[2]        ; DATA[12]      ; 22.698 ; 20.964 ; 20.964 ; 22.698 ;
; FC[2]        ; DATA[13]      ; 23.139 ; 21.396 ; 21.396 ; 23.139 ;
; FC[2]        ; DATA[14]      ; 21.589 ; 21.589 ; 21.589 ; 21.589 ;
; FC[2]        ; DATA[15]      ; 21.330 ; 21.330 ; 21.330 ; 21.330 ;
; FC[2]        ; DTACKn        ; 17.021 ; 17.021 ; 17.021 ; 17.021 ;
; FC[2]        ; JOY_RHn       ;        ; 19.394 ; 19.394 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 18.235 ; 18.235 ;        ;
; FC[2]        ; JOY_WEn       ; 18.387 ;        ;        ; 18.387 ;
; FC[2]        ; JOY_WL        ; 16.253 ;        ;        ; 16.253 ;
; FC[2]        ; RAM_DATA[0]   ; 22.080 ; 21.773 ; 21.773 ; 22.080 ;
; FC[2]        ; RAM_DATA[1]   ; 21.405 ; 21.365 ; 21.365 ; 21.405 ;
; FC[2]        ; RAM_DATA[2]   ; 22.216 ; 22.172 ; 22.172 ; 22.216 ;
; FC[2]        ; RAM_DATA[3]   ; 23.017 ; 21.611 ; 21.611 ; 23.017 ;
; FC[2]        ; RAM_DATA[4]   ; 22.879 ; 22.017 ; 22.017 ; 22.879 ;
; FC[2]        ; RAM_DATA[5]   ; 22.822 ; 22.156 ; 22.156 ; 22.822 ;
; FC[2]        ; RAM_DATA[6]   ; 23.191 ; 22.747 ; 22.747 ; 23.191 ;
; FC[2]        ; RAM_DATA[7]   ; 23.715 ; 22.742 ; 22.742 ; 23.715 ;
; FC[2]        ; RAM_DATA[8]   ; 26.578 ; 23.313 ; 23.313 ; 26.578 ;
; FC[2]        ; RAM_DATA[9]   ; 25.236 ; 22.350 ; 22.350 ; 25.236 ;
; FC[2]        ; RAM_DATA[10]  ; 24.271 ; 22.310 ; 22.310 ; 24.271 ;
; FC[2]        ; RAM_DATA[11]  ; 24.750 ; 22.123 ; 22.123 ; 24.750 ;
; FC[2]        ; RAM_DATA[12]  ; 24.110 ; 22.376 ; 22.376 ; 24.110 ;
; FC[2]        ; RAM_DATA[13]  ; 23.853 ; 22.110 ; 22.110 ; 23.853 ;
; FC[2]        ; RAM_DATA[14]  ; 21.596 ; 21.596 ; 21.596 ; 21.596 ;
; FC[2]        ; RAM_DATA[15]  ; 21.583 ; 21.583 ; 21.583 ; 21.583 ;
; HDINTn       ; DATA[5]       ; 24.068 ;        ;        ; 24.068 ;
; HDINTn       ; DATA[13]      ; 25.542 ;        ;        ; 25.542 ;
; HDINTn       ; RAM_DATA[5]   ; 26.084 ;        ;        ; 26.084 ;
; HDINTn       ; RAM_DATA[13]  ; 26.256 ;        ;        ; 26.256 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.507 ; 24.507 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 25.981 ; 25.981 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.523 ; 26.523 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 26.695 ; 26.695 ;        ;
; IDE_IORDY    ; DTACKn        ; 21.049 ; 21.049 ; 21.049 ; 21.049 ;
; LDSn         ; ACSI_RDn      ; 16.989 ; 16.989 ; 16.989 ; 16.989 ;
; LDSn         ; ACSI_WRn      ; 18.361 ; 18.361 ; 18.361 ; 18.361 ;
; LDSn         ; BUTTONn       ; 15.512 ;        ;        ; 15.512 ;
; LDSn         ; CA1_OUT       ; 18.222 ;        ;        ; 18.222 ;
; LDSn         ; CD[0]         ; 19.706 ; 19.706 ; 19.706 ; 19.706 ;
; LDSn         ; CD[1]         ; 19.389 ; 19.389 ; 19.389 ; 19.389 ;
; LDSn         ; CD[2]         ; 18.450 ; 18.371 ; 18.371 ; 18.450 ;
; LDSn         ; CD[3]         ; 19.389 ; 19.389 ; 19.389 ; 19.389 ;
; LDSn         ; CD[4]         ; 18.768 ; 18.768 ; 18.768 ; 18.768 ;
; LDSn         ; CD[5]         ; 19.361 ; 19.361 ; 19.361 ; 19.361 ;
; LDSn         ; CD[6]         ; 19.342 ; 19.342 ; 19.342 ; 19.342 ;
; LDSn         ; CD[7]         ; 17.909 ; 17.909 ; 17.909 ; 17.909 ;
; LDSn         ; DATA[0]       ; 18.594 ; 19.161 ; 19.161 ; 18.594 ;
; LDSn         ; DATA[1]       ; 19.342 ; 19.342 ; 19.342 ; 19.342 ;
; LDSn         ; DATA[2]       ; 18.607 ; 18.076 ; 18.076 ; 18.607 ;
; LDSn         ; DATA[3]       ; 18.964 ; 18.745 ; 18.745 ; 18.964 ;
; LDSn         ; DATA[4]       ; 18.348 ; 18.348 ; 18.348 ; 18.348 ;
; LDSn         ; DATA[5]       ; 18.580 ; 18.580 ; 18.580 ; 18.580 ;
; LDSn         ; DATA[6]       ; 18.005 ; 18.005 ; 18.005 ; 18.005 ;
; LDSn         ; DATA[7]       ; 18.614 ; 18.240 ; 18.240 ; 18.614 ;
; LDSn         ; DATA[8]       ; 19.007 ; 19.007 ; 19.007 ; 19.007 ;
; LDSn         ; DATA[9]       ; 19.007 ; 19.007 ; 19.007 ; 19.007 ;
; LDSn         ; DATA[10]      ; 19.343 ; 19.343 ; 19.343 ; 19.343 ;
; LDSn         ; DATA[11]      ; 19.343 ; 19.343 ; 19.343 ; 19.343 ;
; LDSn         ; DATA[12]      ; 19.305 ; 19.305 ; 19.305 ; 19.305 ;
; LDSn         ; DATA[13]      ; 19.403 ; 19.403 ; 19.403 ; 19.403 ;
; LDSn         ; DATA[14]      ; 19.409 ; 19.409 ; 19.409 ; 19.409 ;
; LDSn         ; DATA[15]      ; 19.399 ; 19.399 ; 19.399 ; 19.399 ;
; LDSn         ; DTACKn        ; 16.460 ; 16.460 ; 16.460 ; 16.460 ;
; LDSn         ; IDE_IORDn     ; 13.117 ;        ;        ; 13.117 ;
; LDSn         ; IDE_IOWRn     ; 14.546 ;        ;        ; 14.546 ;
; LDSn         ; JOY_RLn       ; 16.673 ;        ;        ; 16.673 ;
; LDSn         ; JOY_WEn       ;        ; 16.825 ; 16.825 ;        ;
; LDSn         ; JOY_WL        ;        ; 13.922 ; 13.922 ;        ;
; LDSn         ; RAM_CAS0n     ; 16.261 ;        ;        ; 16.261 ;
; LDSn         ; RAM_CAS1n     ; 15.005 ;        ;        ; 15.005 ;
; LDSn         ; RAM_DATA[0]   ; 20.681 ; 21.248 ; 21.248 ; 20.681 ;
; LDSn         ; RAM_DATA[1]   ; 20.895 ; 20.895 ; 20.895 ; 20.895 ;
; LDSn         ; RAM_DATA[2]   ; 21.190 ; 20.659 ; 20.659 ; 21.190 ;
; LDSn         ; RAM_DATA[3]   ; 20.918 ; 20.699 ; 20.699 ; 20.918 ;
; LDSn         ; RAM_DATA[4]   ; 21.241 ; 21.241 ; 21.241 ; 21.241 ;
; LDSn         ; RAM_DATA[5]   ; 20.596 ; 20.596 ; 20.596 ; 20.596 ;
; LDSn         ; RAM_DATA[6]   ; 21.591 ; 21.591 ; 21.591 ; 21.591 ;
; LDSn         ; RAM_DATA[7]   ; 22.584 ; 21.958 ; 21.958 ; 22.584 ;
; LDSn         ; RAM_DATA[8]   ; 22.195 ; 23.026 ; 23.026 ; 22.195 ;
; LDSn         ; RAM_DATA[9]   ; 21.843 ; 21.843 ; 21.843 ; 21.843 ;
; LDSn         ; RAM_DATA[10]  ; 20.878 ; 20.878 ; 20.878 ; 20.878 ;
; LDSn         ; RAM_DATA[11]  ; 20.899 ; 20.899 ; 20.899 ; 20.899 ;
; LDSn         ; RAM_DATA[12]  ; 20.717 ; 20.717 ; 20.717 ; 20.717 ;
; LDSn         ; RAM_DATA[13]  ; 20.460 ; 20.460 ; 20.460 ; 20.460 ;
; LDSn         ; RAM_DATA[14]  ; 20.174 ; 20.174 ; 20.174 ; 20.174 ;
; LDSn         ; RAM_DATA[15]  ; 20.776 ; 20.776 ; 20.776 ; 20.776 ;
; LDSn         ; RAM_DQM0L     ; 14.741 ;        ;        ; 14.741 ;
; LDSn         ; RAM_DQM1L     ; 14.286 ;        ;        ; 14.286 ;
; LPT_BSY      ; DATA[0]       ; 23.440 ;        ;        ; 23.440 ;
; LPT_BSY      ; DATA[8]       ; 25.459 ;        ;        ; 25.459 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.527 ;        ;        ; 25.527 ;
; LPT_BSY      ; RAM_DATA[8]   ; 27.687 ;        ;        ; 27.687 ;
; LPT_D[0]     ; DATA[0]       ; 19.574 ;        ;        ; 19.574 ;
; LPT_D[0]     ; DATA[8]       ; 21.252 ;        ;        ; 21.252 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 21.661 ;        ;        ; 21.661 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 23.480 ;        ;        ; 23.480 ;
; LPT_D[1]     ; DATA[1]       ; 21.080 ;        ;        ; 21.080 ;
; LPT_D[1]     ; DATA[9]       ; 21.204 ;        ;        ; 21.204 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 22.513 ;        ;        ; 22.513 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.991 ;        ;        ; 22.991 ;
; LPT_D[2]     ; DATA[2]       ; 20.240 ;        ;        ; 20.240 ;
; LPT_D[2]     ; DATA[10]      ; 22.577 ;        ;        ; 22.577 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 22.823 ;        ;        ; 22.823 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 22.924 ;        ;        ; 22.924 ;
; LPT_D[3]     ; DATA[3]       ; 20.711 ;        ;        ; 20.711 ;
; LPT_D[3]     ; DATA[11]      ; 22.223 ;        ;        ; 22.223 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 22.665 ;        ;        ; 22.665 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 23.049 ;        ;        ; 23.049 ;
; LPT_D[4]     ; DATA[4]       ; 22.828 ;        ;        ; 22.828 ;
; LPT_D[4]     ; DATA[12]      ; 24.045 ;        ;        ; 24.045 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.721 ;        ;        ; 25.721 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 25.457 ;        ;        ; 25.457 ;
; LPT_D[5]     ; DATA[5]       ; 20.161 ;        ;        ; 20.161 ;
; LPT_D[5]     ; DATA[13]      ; 22.249 ;        ;        ; 22.249 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 22.177 ;        ;        ; 22.177 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.963 ;        ;        ; 22.963 ;
; LPT_D[6]     ; DATA[6]       ; 20.170 ;        ;        ; 20.170 ;
; LPT_D[6]     ; DATA[14]      ; 22.975 ; 22.975 ; 22.975 ; 22.975 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 23.756 ;        ;        ; 23.756 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 22.982 ; 22.982 ; 22.982 ; 22.982 ;
; LPT_D[7]     ; DATA[7]       ; 20.541 ;        ;        ; 20.541 ;
; LPT_D[7]     ; DATA[15]      ; 22.601 ; 22.601 ; 22.601 ; 22.601 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 24.259 ;        ;        ; 24.259 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 22.854 ; 22.854 ; 22.854 ; 22.854 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 22.386 ;        ;        ; 22.386 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 24.473 ;        ;        ; 24.473 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.685 ;        ;        ; 24.685 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 26.118 ;        ;        ; 26.118 ;
; RAM_DATA[2]  ; DATA[2]       ; 24.490 ;        ;        ; 24.490 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 27.073 ;        ;        ; 27.073 ;
; RAM_DATA[3]  ; DATA[3]       ; 22.581 ;        ;        ; 22.581 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.535 ;        ;        ; 24.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.917 ;        ;        ; 21.917 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 24.810 ;        ;        ; 24.810 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.287 ;        ;        ; 23.287 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.303 ;        ;        ; 25.303 ;
; RAM_DATA[6]  ; DATA[6]       ; 22.355 ;        ;        ; 22.355 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.941 ;        ;        ; 25.941 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.981 ;        ;        ; 22.981 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 26.699 ;        ;        ; 26.699 ;
; RAM_DATA[8]  ; DATA[8]       ; 25.310 ;        ;        ; 25.310 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 27.538 ;        ;        ; 27.538 ;
; RAM_DATA[9]  ; DATA[9]       ; 24.007 ;        ;        ; 24.007 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.794 ;        ;        ; 25.794 ;
; RAM_DATA[10] ; DATA[10]      ; 25.005 ;        ;        ; 25.005 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 25.352 ;        ;        ; 25.352 ;
; RAM_DATA[11] ; DATA[11]      ; 24.771 ;        ;        ; 24.771 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 25.597 ;        ;        ; 25.597 ;
; RAM_DATA[12] ; DATA[12]      ; 23.020 ;        ;        ; 23.020 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 24.432 ;        ;        ; 24.432 ;
; RAM_DATA[13] ; DATA[13]      ; 24.628 ;        ;        ; 24.628 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 25.342 ;        ;        ; 25.342 ;
; RAM_DATA[14] ; DATA[14]      ; 24.239 ; 24.239 ; 24.239 ; 24.239 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 24.246 ; 24.246 ; 24.246 ; 24.246 ;
; RAM_DATA[15] ; DATA[15]      ; 24.937 ; 24.937 ; 24.937 ; 24.937 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 25.190 ; 25.190 ; 25.190 ; 25.190 ;
; RWn          ; ACSI_RDn      ; 16.922 ; 14.494 ; 14.494 ; 16.922 ;
; RWn          ; ACSI_WRn      ; 15.866 ; 18.294 ; 18.294 ; 15.866 ;
; RWn          ; BUTTONn       ;        ; 15.643 ; 15.643 ;        ;
; RWn          ; CA1_OUT       ;        ; 18.155 ; 18.155 ;        ;
; RWn          ; CD[0]         ; 16.573 ; 16.573 ; 16.573 ; 16.573 ;
; RWn          ; CD[1]         ; 16.256 ; 16.256 ; 16.256 ; 16.256 ;
; RWn          ; CD[2]         ; 15.145 ; 15.032 ; 15.032 ; 15.145 ;
; RWn          ; CD[3]         ; 16.256 ; 16.256 ; 16.256 ; 16.256 ;
; RWn          ; CD[4]         ; 15.429 ; 15.429 ; 15.429 ; 15.429 ;
; RWn          ; CD[5]         ; 16.059 ; 16.059 ; 16.059 ; 16.059 ;
; RWn          ; CD[6]         ; 16.003 ; 16.003 ; 16.003 ; 16.003 ;
; RWn          ; CD[7]         ; 14.728 ; 14.728 ; 14.728 ; 14.728 ;
; RWn          ; DATA[0]       ; 17.420 ; 17.420 ; 17.420 ; 17.420 ;
; RWn          ; DATA[1]       ; 18.456 ; 18.412 ; 18.412 ; 18.456 ;
; RWn          ; DATA[2]       ; 16.650 ; 16.525 ; 16.525 ; 16.650 ;
; RWn          ; DATA[3]       ; 17.407 ; 16.573 ; 16.573 ; 17.407 ;
; RWn          ; DATA[4]       ; 17.250 ; 16.614 ; 16.614 ; 17.250 ;
; RWn          ; DATA[5]       ; 17.935 ; 17.390 ; 17.390 ; 17.935 ;
; RWn          ; DATA[6]       ; 17.384 ; 16.077 ; 16.077 ; 17.384 ;
; RWn          ; DATA[7]       ; 16.880 ; 16.357 ; 16.357 ; 16.880 ;
; RWn          ; DATA[8]       ; 19.201 ; 18.800 ; 18.800 ; 19.201 ;
; RWn          ; DATA[9]       ; 19.201 ; 18.370 ; 18.370 ; 19.201 ;
; RWn          ; DATA[10]      ; 19.097 ; 18.970 ; 18.970 ; 19.097 ;
; RWn          ; DATA[11]      ; 19.537 ; 18.232 ; 18.232 ; 19.537 ;
; RWn          ; DATA[12]      ; 18.944 ; 18.124 ; 18.124 ; 18.944 ;
; RWn          ; DATA[13]      ; 19.241 ; 18.563 ; 18.563 ; 19.241 ;
; RWn          ; DATA[14]      ; 18.387 ; 18.387 ; 18.387 ; 18.387 ;
; RWn          ; DATA[15]      ; 17.810 ; 17.810 ; 17.810 ; 17.810 ;
; RWn          ; DTACKn        ; 16.149 ; 16.149 ; 16.149 ; 16.149 ;
; RWn          ; FLASH_CEn     ;        ; 14.864 ; 14.864 ;        ;
; RWn          ; FLASH_OEn     ;        ; 15.419 ; 15.419 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.749 ; 14.749 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 12.847 ;        ;        ; 12.847 ;
; RWn          ; IDE_IORDn     ;        ; 12.986 ; 12.986 ;        ;
; RWn          ; IDE_IOWRn     ; 14.416 ;        ;        ; 14.416 ;
; RWn          ; JOY_RHn       ;        ; 14.893 ; 14.893 ;        ;
; RWn          ; JOY_RLn       ;        ; 15.911 ; 15.911 ;        ;
; RWn          ; JOY_WEn       ; 16.063 ;        ;        ; 16.063 ;
; RWn          ; JOY_WL        ; 15.381 ; 13.745 ; 13.745 ; 15.381 ;
; RWn          ; RAM_DATA[0]   ; 16.018 ; 16.018 ; 16.018 ; 16.018 ;
; RWn          ; RAM_DATA[1]   ; 14.392 ; 14.392 ; 14.392 ; 14.392 ;
; RWn          ; RAM_DATA[2]   ; 15.649 ; 15.649 ; 15.649 ; 15.649 ;
; RWn          ; RAM_DATA[3]   ; 14.947 ; 14.947 ; 14.947 ; 14.947 ;
; RWn          ; RAM_DATA[4]   ; 15.388 ; 15.388 ; 15.388 ; 15.388 ;
; RWn          ; RAM_DATA[5]   ; 15.555 ; 15.555 ; 15.555 ; 15.555 ;
; RWn          ; RAM_DATA[6]   ; 15.670 ; 15.670 ; 15.670 ; 15.670 ;
; RWn          ; RAM_DATA[7]   ; 15.422 ; 15.422 ; 15.422 ; 15.422 ;
; RWn          ; RAM_DATA[8]   ; 15.494 ; 15.494 ; 15.494 ; 15.494 ;
; RWn          ; RAM_DATA[9]   ; 15.675 ; 15.675 ; 15.675 ; 15.675 ;
; RWn          ; RAM_DATA[10]  ; 14.403 ; 14.658 ; 14.658 ; 14.403 ;
; RWn          ; RAM_DATA[11]  ; 14.230 ; 14.476 ; 14.476 ; 14.230 ;
; RWn          ; RAM_DATA[12]  ; 15.049 ; 15.049 ; 15.049 ; 15.049 ;
; RWn          ; RAM_DATA[13]  ; 14.123 ; 14.123 ; 14.123 ; 14.123 ;
; RWn          ; RAM_DATA[14]  ; 14.177 ; 14.177 ; 14.177 ; 14.177 ;
; RWn          ; RAM_DATA[15]  ; 14.516 ; 14.516 ; 14.516 ; 14.516 ;
; RWn          ; RAM_WEn       ; 14.842 ;        ;        ; 14.842 ;
; RWn          ; ROM0n         ;        ; 14.976 ; 14.976 ;        ;
; RWn          ; ROM1n         ;        ; 13.906 ; 13.906 ;        ;
; RWn          ; ROM2n         ;        ; 14.105 ; 14.105 ;        ;
; RWn          ; ROM3n         ;        ; 14.002 ; 14.002 ;        ;
; RWn          ; ROM4n         ;        ; 13.699 ; 13.699 ;        ;
; RWn          ; ROM5n         ;        ; 15.963 ; 15.963 ;        ;
; RWn          ; ROM6n         ;        ; 13.101 ; 13.101 ;        ;
; SCSI_ACKn    ; CD[0]         ; 16.457 ; 16.457 ; 16.457 ; 16.457 ;
; SCSI_ATNn    ; CD[1]         ; 18.058 ; 18.058 ; 18.058 ; 18.058 ;
; SCSI_BSYn    ; CD[6]         ; 22.644 ; 22.644 ; 22.644 ; 22.644 ;
; SCSI_D[0]    ; CD[0]         ; 17.333 ; 17.333 ; 17.333 ; 17.333 ;
; SCSI_D[1]    ; CD[1]         ; 16.480 ; 16.480 ; 16.480 ; 16.480 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.613 ; 16.613 ;        ;
; SCSI_D[3]    ; CD[3]         ; 16.418 ; 16.418 ; 16.418 ; 16.418 ;
; SCSI_D[4]    ; CD[4]         ; 23.558 ; 23.558 ; 23.558 ; 23.558 ;
; SCSI_D[5]    ; CD[5]         ; 23.090 ; 23.090 ; 23.090 ; 23.090 ;
; SCSI_D[6]    ; CD[6]         ; 22.848 ; 22.848 ; 22.848 ; 22.848 ;
; SCSI_D[7]    ; CD[7]         ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; SCSI_DCn     ; CD[3]         ; 16.694 ; 16.694 ; 16.694 ; 16.694 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 16.690 ; 16.690 ; 16.690 ; 16.690 ;
; SCSI_DCn     ; SCSI_D[0]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[1]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[2]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[3]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[4]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[5]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[6]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_D[7]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_DP       ; 15.359 ; 15.359 ; 15.359 ; 15.359 ;
; SCSI_DP      ; CD[0]         ; 16.084 ; 16.084 ; 16.084 ; 16.084 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.209 ; 12.209 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.911 ;        ;        ; 12.911 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.310 ; 12.310 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.664 ;        ;        ; 12.664 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 12.961 ; 12.961 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 12.526 ;        ;        ; 12.526 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.749 ; 13.749 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.994 ;        ;        ; 12.994 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 13.060 ; 13.060 ; 13.060 ; 13.060 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.564 ; 11.564 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 12.276 ; 12.276 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.663 ;        ;        ; 11.663 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.018 ;        ;        ; 12.018 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.320 ; 12.320 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 11.894 ; 11.894 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.108 ;        ;        ; 13.108 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.349 ;        ;        ; 12.349 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 12.425 ; 12.425 ; 12.425 ; 12.425 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.373 ; 12.373 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.079 ; 13.079 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.503 ; 12.503 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.857 ; 12.857 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.065 ;        ;        ; 13.065 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 12.636 ;        ;        ; 12.636 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.893 ;        ;        ; 13.893 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.127 ;        ;        ; 13.127 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 13.228 ; 13.228 ; 13.228 ; 13.228 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.074 ; 17.074 ;        ;
; SCSI_IOn     ; CD[3]         ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 13.731 ; 16.228 ; 16.228 ; 13.731 ;
; SCSI_IOn     ; SCSI_D[0]     ; 12.390 ; 12.390 ; 12.390 ; 12.390 ;
; SCSI_IOn     ; SCSI_D[1]     ; 12.390 ; 12.390 ; 12.390 ; 12.390 ;
; SCSI_IOn     ; SCSI_D[2]     ; 11.844 ; 11.844 ; 11.844 ; 11.844 ;
; SCSI_IOn     ; SCSI_D[3]     ; 11.844 ; 11.844 ; 11.844 ; 11.844 ;
; SCSI_IOn     ; SCSI_D[4]     ; 12.152 ; 12.152 ; 12.152 ; 12.152 ;
; SCSI_IOn     ; SCSI_D[5]     ; 12.152 ; 12.152 ; 12.152 ; 12.152 ;
; SCSI_IOn     ; SCSI_D[6]     ; 12.428 ; 12.428 ; 12.428 ; 12.428 ;
; SCSI_IOn     ; SCSI_D[7]     ; 12.428 ; 12.428 ; 12.428 ; 12.428 ;
; SCSI_IOn     ; SCSI_DP       ; 12.400 ; 12.400 ; 12.400 ; 12.400 ;
; SCSI_IOn     ; SCSI_RDn      ; 13.498 ;        ;        ; 13.498 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.290 ; 13.290 ;        ;
; SCSI_MSGn    ; CD[3]         ; 17.772 ; 17.772 ; 17.772 ; 17.772 ;
; SCSI_MSGn    ; CD[4]         ; 22.329 ; 22.329 ; 22.329 ; 22.329 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 16.357 ; 16.357 ; 16.357 ; 16.357 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_DP       ; 15.026 ; 15.026 ; 15.026 ; 15.026 ;
; SCSI_REQn    ; CD[3]         ; 17.887 ; 17.887 ; 17.887 ; 17.887 ;
; SCSI_REQn    ; CD[5]         ; 22.156 ; 22.156 ; 22.156 ; 22.156 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 16.472 ;        ;        ; 16.472 ;
; SCSI_REQn    ; SCSI_D[0]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[1]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[2]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[3]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[4]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[5]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[6]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_D[7]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_DP       ; 15.141 ; 15.141 ; 15.141 ; 15.141 ;
; SCSI_RSTn    ; CD[7]         ;        ; 18.133 ; 18.133 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.156 ; 16.156 ; 16.156 ; 16.156 ;
; SD_AVR_ENn   ; RESETn        ;        ; 17.730 ; 17.730 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.086 ; 13.086 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 10.631 ; 10.631 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.038 ;        ;        ; 13.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.504 ;        ;        ; 12.504 ;
; SD_RESETn    ; ACSI_RDn      ; 19.776 ; 19.776 ; 19.776 ; 19.776 ;
; SD_RESETn    ; ACSI_WRn      ; 21.148 ; 21.148 ; 21.148 ; 21.148 ;
; SD_RESETn    ; CA1_OUT       ; 21.009 ;        ;        ; 21.009 ;
; SD_RESETn    ; CD[0]         ; 22.493 ; 22.493 ; 22.493 ; 22.493 ;
; SD_RESETn    ; CD[1]         ; 22.176 ; 22.176 ; 22.176 ; 22.176 ;
; SD_RESETn    ; CD[2]         ; 21.237 ; 21.158 ; 21.158 ; 21.237 ;
; SD_RESETn    ; CD[3]         ; 22.176 ; 22.176 ; 22.176 ; 22.176 ;
; SD_RESETn    ; CD[4]         ; 21.555 ; 21.555 ; 21.555 ; 21.555 ;
; SD_RESETn    ; CD[5]         ; 22.148 ; 22.148 ; 22.148 ; 22.148 ;
; SD_RESETn    ; CD[6]         ; 22.129 ; 22.129 ; 22.129 ; 22.129 ;
; SD_RESETn    ; CD[7]         ; 20.696 ; 20.696 ; 20.696 ; 20.696 ;
; SD_RESETn    ; COM_TxD       ; 18.782 ; 18.782 ; 18.782 ; 18.782 ;
; SD_RESETn    ; DATA[0]       ; 21.801 ; 21.920 ; 21.920 ; 21.801 ;
; SD_RESETn    ; DATA[1]       ; 22.669 ; 22.669 ; 22.669 ; 22.669 ;
; SD_RESETn    ; DATA[2]       ; 21.560 ; 21.283 ; 21.283 ; 21.560 ;
; SD_RESETn    ; DATA[3]       ; 22.823 ; 22.441 ; 22.441 ; 22.823 ;
; SD_RESETn    ; DATA[4]       ; 21.555 ; 21.555 ; 21.555 ; 21.555 ;
; SD_RESETn    ; DATA[5]       ; 21.787 ; 21.787 ; 21.787 ; 21.787 ;
; SD_RESETn    ; DATA[6]       ; 21.212 ; 21.212 ; 21.212 ; 21.212 ;
; SD_RESETn    ; DATA[7]       ; 22.234 ; 21.747 ; 21.747 ; 22.234 ;
; SD_RESETn    ; DATA[8]       ; 23.174 ; 24.164 ; 24.164 ; 23.174 ;
; SD_RESETn    ; DATA[9]       ; 23.196 ; 23.263 ; 23.263 ; 23.196 ;
; SD_RESETn    ; DATA[10]      ; 23.738 ; 23.738 ; 23.738 ; 23.738 ;
; SD_RESETn    ; DATA[11]      ; 23.738 ; 23.738 ; 23.738 ; 23.738 ;
; SD_RESETn    ; DATA[12]      ; 22.512 ; 22.512 ; 22.512 ; 22.512 ;
; SD_RESETn    ; DATA[13]      ; 22.953 ; 22.953 ; 22.953 ; 22.953 ;
; SD_RESETn    ; DATA[14]      ; 23.834 ; 23.834 ; 23.834 ; 23.834 ;
; SD_RESETn    ; DATA[15]      ; 23.257 ; 23.257 ; 23.257 ; 23.257 ;
; SD_RESETn    ; DTACKn        ; 19.194 ; 19.194 ; 19.194 ; 19.194 ;
; SD_RESETn    ; RAM_DATA[0]   ; 23.888 ; 24.007 ; 24.007 ; 23.888 ;
; SD_RESETn    ; RAM_DATA[1]   ; 24.102 ; 24.102 ; 24.102 ; 24.102 ;
; SD_RESETn    ; RAM_DATA[2]   ; 24.143 ; 23.866 ; 23.866 ; 24.143 ;
; SD_RESETn    ; RAM_DATA[3]   ; 24.777 ; 24.395 ; 24.395 ; 24.777 ;
; SD_RESETn    ; RAM_DATA[4]   ; 24.448 ; 24.448 ; 24.448 ; 24.448 ;
; SD_RESETn    ; RAM_DATA[5]   ; 23.803 ; 23.803 ; 23.803 ; 23.803 ;
; SD_RESETn    ; RAM_DATA[6]   ; 24.798 ; 24.798 ; 24.798 ; 24.798 ;
; SD_RESETn    ; RAM_DATA[7]   ; 25.952 ; 25.465 ; 25.465 ; 25.952 ;
; SD_RESETn    ; RAM_DATA[8]   ; 25.402 ; 26.392 ; 26.392 ; 25.402 ;
; SD_RESETn    ; RAM_DATA[9]   ; 24.983 ; 25.050 ; 25.050 ; 24.983 ;
; SD_RESETn    ; RAM_DATA[10]  ; 24.085 ; 24.085 ; 24.085 ; 24.085 ;
; SD_RESETn    ; RAM_DATA[11]  ; 24.564 ; 24.564 ; 24.564 ; 24.564 ;
; SD_RESETn    ; RAM_DATA[12]  ; 23.924 ; 23.924 ; 23.924 ; 23.924 ;
; SD_RESETn    ; RAM_DATA[13]  ; 23.667 ; 23.667 ; 23.667 ; 23.667 ;
; SD_RESETn    ; RAM_DATA[14]  ; 23.841 ; 23.841 ; 23.841 ; 23.841 ;
; SD_RESETn    ; RAM_DATA[15]  ; 23.510 ; 23.510 ; 23.510 ; 23.510 ;
; UDSn         ; ACSI_RDn      ; 18.985 ; 18.985 ; 18.985 ; 18.985 ;
; UDSn         ; ACSI_WRn      ; 20.357 ; 20.357 ; 20.357 ; 20.357 ;
; UDSn         ; CA1_OUT       ; 20.218 ;        ;        ; 20.218 ;
; UDSn         ; CD[0]         ; 21.702 ; 21.702 ; 21.702 ; 21.702 ;
; UDSn         ; CD[1]         ; 21.385 ; 21.385 ; 21.385 ; 21.385 ;
; UDSn         ; CD[2]         ; 20.446 ; 20.367 ; 20.367 ; 20.446 ;
; UDSn         ; CD[3]         ; 21.385 ; 21.385 ; 21.385 ; 21.385 ;
; UDSn         ; CD[4]         ; 20.764 ; 20.764 ; 20.764 ; 20.764 ;
; UDSn         ; CD[5]         ; 21.357 ; 21.357 ; 21.357 ; 21.357 ;
; UDSn         ; CD[6]         ; 21.338 ; 21.338 ; 21.338 ; 21.338 ;
; UDSn         ; CD[7]         ; 19.905 ; 19.905 ; 19.905 ; 19.905 ;
; UDSn         ; DATA[0]       ; 19.189 ; 19.189 ; 19.189 ; 19.189 ;
; UDSn         ; DATA[1]       ; 19.189 ; 19.189 ; 19.189 ; 19.189 ;
; UDSn         ; DATA[2]       ; 18.842 ; 18.842 ; 18.842 ; 18.842 ;
; UDSn         ; DATA[3]       ; 18.842 ; 18.592 ; 18.592 ; 18.842 ;
; UDSn         ; DATA[4]       ; 18.831 ; 18.831 ; 18.831 ; 18.831 ;
; UDSn         ; DATA[5]       ; 18.831 ; 18.831 ; 18.831 ; 18.831 ;
; UDSn         ; DATA[6]       ; 18.471 ; 18.471 ; 18.471 ; 18.471 ;
; UDSn         ; DATA[7]       ; 18.461 ; 18.461 ; 18.461 ; 18.461 ;
; UDSn         ; DATA[8]       ; 18.854 ; 18.854 ; 18.854 ; 18.854 ;
; UDSn         ; DATA[9]       ; 18.854 ; 18.854 ; 18.854 ; 18.854 ;
; UDSn         ; DATA[10]      ; 19.190 ; 19.190 ; 19.190 ; 19.190 ;
; UDSn         ; DATA[11]      ; 19.190 ; 19.190 ; 19.190 ; 19.190 ;
; UDSn         ; DATA[12]      ; 19.250 ; 19.250 ; 19.250 ; 19.250 ;
; UDSn         ; DATA[13]      ; 19.250 ; 19.250 ; 19.250 ; 19.250 ;
; UDSn         ; DATA[14]      ; 19.256 ; 19.256 ; 19.256 ; 19.256 ;
; UDSn         ; DATA[15]      ; 19.246 ; 19.246 ; 19.246 ; 19.246 ;
; UDSn         ; DTACKn        ; 17.386 ; 17.386 ; 17.386 ; 17.386 ;
; UDSn         ; JOY_RHn       ; 14.641 ;        ;        ; 14.641 ;
; UDSn         ; RAM_CAS0n     ; 15.583 ;        ;        ; 15.583 ;
; UDSn         ; RAM_CAS1n     ; 14.327 ;        ;        ; 14.327 ;
; UDSn         ; RAM_DATA[0]   ; 22.044 ; 22.239 ; 22.239 ; 22.044 ;
; UDSn         ; RAM_DATA[1]   ; 20.809 ; 21.029 ; 21.029 ; 20.809 ;
; UDSn         ; RAM_DATA[2]   ; 21.532 ; 22.253 ; 22.253 ; 21.532 ;
; UDSn         ; RAM_DATA[3]   ; 21.052 ; 20.546 ; 20.546 ; 21.052 ;
; UDSn         ; RAM_DATA[4]   ; 21.732 ; 22.007 ; 22.007 ; 21.732 ;
; UDSn         ; RAM_DATA[5]   ; 21.736 ; 21.915 ; 21.915 ; 21.736 ;
; UDSn         ; RAM_DATA[6]   ; 22.171 ; 22.335 ; 22.335 ; 22.171 ;
; UDSn         ; RAM_DATA[7]   ; 22.431 ; 22.700 ; 22.700 ; 22.431 ;
; UDSn         ; RAM_DATA[8]   ; 23.506 ; 23.601 ; 23.601 ; 23.506 ;
; UDSn         ; RAM_DATA[9]   ; 23.254 ; 23.521 ; 23.521 ; 23.254 ;
; UDSn         ; RAM_DATA[10]  ; 21.183 ; 21.183 ; 21.183 ; 21.183 ;
; UDSn         ; RAM_DATA[11]  ; 20.746 ; 20.746 ; 20.746 ; 20.746 ;
; UDSn         ; RAM_DATA[12]  ; 22.100 ; 22.145 ; 22.145 ; 22.100 ;
; UDSn         ; RAM_DATA[13]  ; 21.518 ; 21.397 ; 21.397 ; 21.518 ;
; UDSn         ; RAM_DATA[14]  ; 20.021 ; 20.021 ; 20.021 ; 20.021 ;
; UDSn         ; RAM_DATA[15]  ; 20.230 ; 20.230 ; 20.230 ; 20.230 ;
; UDSn         ; RAM_DQM0H     ; 13.771 ;        ;        ; 13.771 ;
; UDSn         ; RAM_DQM1H     ; 14.022 ;        ;        ; 14.022 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 19.536 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 20.226 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 19.909 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 19.536 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 19.909 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 19.881 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 19.881 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 19.866 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 19.866 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 15.018 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.529 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 13.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 13.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 13.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.885 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.885 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 13.444 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 13.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 13.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 13.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 13.997 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 13.997 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 13.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 13.122 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 13.122 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 13.655 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 13.665 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.413  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 36.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 37.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 36.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 36.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 36.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 36.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 36.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 36.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 36.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 14.739 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 31.562 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 32.290 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 32.290 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 31.943 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 31.943 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 31.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 31.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 31.572 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 31.562 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 31.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 31.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 32.291 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 32.291 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 32.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 32.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 32.357 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 32.347 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.034  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 36.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 9.461  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 9.461  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 9.520  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 9.520  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.979  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 28.654 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 28.285 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 28.285 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 28.831 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 28.831 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 29.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 30.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 29.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 28.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 28.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 27.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 28.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 28.579 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 10.033 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.178  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.479  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.479  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.241  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.241  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.517  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.517  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 9.489  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.051  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.863  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.979  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 9.225  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.377  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.765  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.526  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.516  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.815  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.805  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.737  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.747  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 23.714 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 24.404 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 24.087 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 23.714 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 24.087 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 24.059 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 24.059 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 24.044 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 24.044 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 19.373 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 20.101 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 20.101 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 19.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 19.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 19.743 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 19.743 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 19.383 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 19.373 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 19.766 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 19.766 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 20.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 20.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 20.162 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 20.162 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 20.168 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 20.158 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 23.531 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.362 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 17.362 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.908 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.908 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 18.650 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 19.190 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 18.650 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.667 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.667 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.052 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.665 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.656 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 13.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 13.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 13.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 13.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 12.541 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.885 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.885 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 13.444 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 13.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 13.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 13.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 13.997 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 13.997 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 13.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 13.122 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 13.122 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 13.655 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 13.665 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.413  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 36.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 37.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 36.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 36.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 36.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 36.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 36.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 36.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 36.936 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 14.739 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 31.562 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 32.290 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 32.290 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 31.943 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 31.943 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 31.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 31.932 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 31.572 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 31.562 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 31.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 31.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 32.291 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 32.291 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 32.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 32.351 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 32.357 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 32.347 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.034  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 36.423 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.461  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.461  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.520  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.520  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.979  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 28.654 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 28.285 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 28.285 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 28.831 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 28.831 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 29.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 30.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 29.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 28.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 28.590 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 27.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 27.965 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 28.588 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 28.579 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.033 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.178  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.479  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.479  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.933  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.241  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.241  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.517  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.517  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.489  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.051  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.982  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.863  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.979  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 9.225  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.377  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.765  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.526  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.516  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.815  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.805  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.737  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.747  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 23.714 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 24.404 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 24.087 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.714 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 24.087 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 24.059 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 24.059 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 24.044 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 24.044 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 19.373 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 20.101 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 20.101 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 19.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 19.754 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 19.743 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 19.743 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 19.383 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 19.373 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 19.766 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 19.766 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 20.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 20.102 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 20.162 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 20.162 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 20.168 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 20.158 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 23.531 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.362 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 17.362 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.908 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.908 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 18.650 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 19.190 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 18.650 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.667 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.667 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.052 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 17.042 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.665 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.656 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 7.030  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 16.435 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 17.125 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 16.808 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 16.435 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 16.808 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 16.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 16.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 16.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 16.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 11.917 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 18.749 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.248 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.182 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.604  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 10.088 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 8.264  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.757  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 9.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.612  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.747  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.757  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.289  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 19.203 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 7.030  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.435 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.125 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.808 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.435 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.808 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 11.917 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 18.749 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.248 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.425 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.167 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.184 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.569 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.182 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.173 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.604  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 10.088 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 8.264  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 9.141  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.757  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.612  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.747  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.757  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.289  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.203 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 13.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 13.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 12.502 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 13.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 13.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                             ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 18.039 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 18.729 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 18.412 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 18.039 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 18.412 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 18.384 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 18.384 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 18.369 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 18.369 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 15.018 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.430 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.276  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.478  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.478  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.037  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.027  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.326  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.316  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 8.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 8.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.020  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.696  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.258  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.696  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 7.794  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 7.477  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 7.477  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 7.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 7.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 7.434  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 7.434  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 6.996  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.734  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 7.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 7.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 7.115  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 7.115  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.734  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 7.127  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 7.127  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 7.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 7.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 7.523  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 7.523  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 7.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 7.519  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 7.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 8.954  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.685  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.685  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.710 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.887 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.887 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.629 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 13.169 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.629 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.031 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.257  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 5.595  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 6.304  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 6.304  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 6.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 6.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 6.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 6.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 6.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.051  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 6.444  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 6.280  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.950  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.377  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.765  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.526  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.516  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.815  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.805  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.737  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.747  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 15.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 15.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 15.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 15.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 15.703 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 15.703 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 15.688 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 15.688 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.056 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.784 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.784 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.437 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.437 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.426 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.426 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.066 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.056 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.785 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.785 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.841 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.802 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.710 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.887 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.887 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.629 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 13.169 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.629 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.646 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.646 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.644 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.635 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.278  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.276  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.266  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.134  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.478  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.478  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.037  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.027  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.326  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.316  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 8.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 8.590  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.020  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.696  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.248  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.258  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.696  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 7.095  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 7.794  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 7.477  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 7.477  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 7.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 7.449  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 7.434  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 7.434  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 6.996  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.734  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.462  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.115  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.115  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.104  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.734  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.127  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.127  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.463  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.523  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.523  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.519  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 7.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 8.954  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.685  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.685  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.719  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.306  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 9.006  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.710 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.341 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.887 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.887 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.629 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 13.169 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.629 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.646 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.031 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.257  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 5.595  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.662  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 6.304  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 6.304  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 5.758  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 6.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 6.066  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 6.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 6.342  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 6.314  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.051  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.196  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 6.444  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 6.280  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.203  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.950  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.377  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.767  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.765  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.755  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.623  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.967  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.526  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.516  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.815  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.805  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.204  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.737  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.747  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 8.185  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 15.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 15.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 15.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 15.731 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 15.703 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 15.703 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 15.688 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 15.688 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.056 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.784 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.784 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.437 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.437 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.426 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.426 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.066 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.056 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.449 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.785 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.785 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.851 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.841 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.802 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.710 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.341 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.887 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.887 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.629 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 13.169 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.629 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.646 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.646 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.031 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.644 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.635 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 7.030  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.307  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.997  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.680  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.307  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.680  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.652  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.652  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.637  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.637  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.121 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 10.533 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.878  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.509  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.509  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 10.797 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.337 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 10.797 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.814  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.814  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.803  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.302  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 10.000 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 8.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.762  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.762  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.038  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.038  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 9.010  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.528  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.663  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.151  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.987  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 19.203 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 7.030  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.307  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.997  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.680  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.307  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.680  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.652  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.652  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.637  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.637  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.121 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.533 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.664  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.723  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.878  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.509  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.509  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 10.797 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.337 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 10.797 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.814  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.814  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.199  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.189  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.803  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.236  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.302  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 10.000 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 8.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.000  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.762  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.762  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.038  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.038  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.010  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.528  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.663  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.673  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.151  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.987  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.182  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.203 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 10.402 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 10.402 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 9.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 10.402 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 10.402 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 19.536    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 20.226    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 19.909    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 19.536    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 19.909    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 19.881    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 19.881    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 19.866    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 19.866    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 15.018    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.529    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 13.685    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 13.685    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 13.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.885    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.885    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 13.444    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 13.434    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 13.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 13.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 13.997    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 13.997    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 13.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 13.122    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 13.122    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 13.655    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 13.665    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.413     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 36.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 37.296    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 36.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 36.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 36.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 36.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 36.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 36.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 36.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 14.739    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 31.562    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 32.290    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 32.290    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 31.943    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 31.943    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 31.932    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 31.932    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 31.572    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 31.562    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 31.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 31.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 32.291    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 32.291    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 32.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 32.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 32.357    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 32.347    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 8.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 36.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 9.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 9.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 9.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 9.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.979     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 28.654    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 28.285    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 28.285    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 28.831    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 28.831    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 29.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 30.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 29.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 28.590    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 28.590    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 27.975    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 28.588    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 28.579    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 10.033    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.178     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.479     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.479     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.241     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.241     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.517     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.517     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 9.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.051     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 7.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.863     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.979     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 9.225     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.526     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.516     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.815     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.805     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.737     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.747     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 23.714    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 24.404    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 24.087    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 23.714    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 24.087    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 24.059    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 24.059    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 24.044    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 24.044    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 19.373    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 20.101    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 20.101    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 19.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 19.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 19.743    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 19.743    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 19.383    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 19.373    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 19.766    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 19.766    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 20.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 20.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 20.162    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 20.162    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 20.168    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 20.158    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 23.531    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 17.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 17.362    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 17.362    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 17.908    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 17.908    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 18.650    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 19.190    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 18.650    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 17.667    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 17.667    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 17.052    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 17.665    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 17.656    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 13.685    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 13.685    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 13.683    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 13.673    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 12.541    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.885    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.885    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 13.444    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 13.434    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 13.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 13.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 13.997    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 13.997    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 13.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 13.122    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 13.122    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 13.655    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 13.665    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.413     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 36.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 37.296    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 36.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 36.606    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 36.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 36.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 36.951    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 36.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 36.936    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 14.739    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 31.562    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 32.290    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 32.290    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 31.943    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 31.943    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 31.932    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 31.932    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 31.572    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 31.562    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 31.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 31.955    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 32.291    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 32.291    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 32.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 32.351    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 32.357    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 32.347    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 8.034     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 36.423    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 9.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 9.461     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 9.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 9.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.979     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 28.654    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 28.285    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 28.285    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 28.831    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 28.831    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 29.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 30.113    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 29.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 28.590    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 28.590    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 27.975    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 27.965    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 28.588    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 28.579    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.033    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.178     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.479     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.479     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.933     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.241     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.241     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.517     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.517     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.051     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 7.982     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.863     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.979     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 9.225     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.526     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.516     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.815     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.805     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.737     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.747     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 23.714    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 24.404    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 24.087    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.714    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 24.087    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 24.059    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 24.059    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 24.044    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 24.044    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 19.373    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 20.101    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 20.101    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 19.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 19.754    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 19.743    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 19.743    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 19.383    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 19.373    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 19.766    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 19.766    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 20.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 20.102    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 20.162    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 20.162    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 20.168    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 20.158    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 23.531    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 17.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 17.362    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 17.362    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 17.908    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 17.908    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 18.650    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 19.190    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 18.650    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 17.667    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 17.667    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 17.052    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 17.042    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 17.665    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 17.656    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 7.030     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 16.435    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 17.125    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 16.808    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 16.435    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 16.808    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 16.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 16.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 16.765    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 16.765    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 11.917    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 18.749    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 14.248    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 13.879    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 13.879    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 14.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 14.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 15.167    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 15.707    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 15.167    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 14.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 14.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 13.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 14.182    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 14.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.604     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 10.088    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 8.264     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 9.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 9.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 9.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.612     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.747     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 9.289     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 19.203    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 7.030     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 16.435    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 17.125    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 16.808    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 16.435    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 16.808    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 16.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 16.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 16.765    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 16.765    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 11.917    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 18.749    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 14.248    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 13.879    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 13.879    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 14.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 14.425    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 15.167    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 15.707    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 15.167    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 14.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 14.184    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 13.569    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 13.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 14.182    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 14.173    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.604     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 10.088    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 8.264     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 9.141     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 9.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 9.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.612     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.747     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.757     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 9.289     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.203    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 13.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 13.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 12.502    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 13.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 13.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 18.039    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 18.729    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 18.412    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 18.039    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 18.412    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 18.384    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 18.384    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 18.369    ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 18.369    ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 15.018    ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 15.430    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.478     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.478     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.037     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.027     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.326     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 8.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 8.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.020     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.696     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.258     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.696     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 7.794     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 7.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 7.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 7.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 7.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 7.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 7.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 6.996     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 7.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 7.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 7.115     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 7.115     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 7.127     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 7.127     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 7.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 7.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 7.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 7.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 7.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 7.519     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 7.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 8.954     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 8.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.710    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.887    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.887    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.629    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 13.169    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.629    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.031    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 5.595     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 9.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 7.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 6.304     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 6.304     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 6.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 6.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 6.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 6.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 6.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.051     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 6.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 6.280     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 8.950     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 7.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 8.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 8.526     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 8.516     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.815     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.805     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 8.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 8.737     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 8.747     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 15.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 16.048    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 15.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 15.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 15.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 15.703    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 15.703    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 15.688    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 15.688    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.056    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.784    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.784    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.437    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.437    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.426    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.426    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.066    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.056    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.449    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.449    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.785    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.785    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.841    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.802    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.710    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.887    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.887    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.629    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 13.169    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.629    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.646    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.646    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.031    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.644    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.635    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.478     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.478     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.037     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.027     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.326     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 8.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 8.590     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.020     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.696     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.258     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.696     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 7.095     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 7.794     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 7.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 7.477     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 7.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 7.449     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 7.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 7.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 6.996     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.115     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.115     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.104     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.734     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.127     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.127     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.519     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 7.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 8.954     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 7.719     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 8.306     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 9.006     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 8.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.710    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.341    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.887    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.887    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.629    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 13.169    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.629    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.646    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.031    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 5.595     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 9.662     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 7.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 6.304     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 6.304     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 5.758     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 6.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 6.066     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 6.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 6.342     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 6.314     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.051     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 6.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 6.280     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.203     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 8.950     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 8.767     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 8.765     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 8.755     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 7.623     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.967     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 8.526     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 8.516     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.815     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.805     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 9.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 8.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 8.204     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 8.737     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 8.747     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 8.185     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 15.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 16.048    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 15.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 15.358    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 15.731    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 15.703    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 15.703    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 15.688    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 15.688    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.056    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.784    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.784    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.437    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.437    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.426    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.426    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.066    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.056    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.449    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.449    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.785    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.785    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.851    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.841    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.802    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.710    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.341    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.887    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.887    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.629    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 13.169    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.629    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.646    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.646    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.031    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.021    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.644    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.635    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 7.030     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.307     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.997     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.307     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.652     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.652     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.637     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.637     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.121    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 10.533    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.878     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.509     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.509     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.055    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.055    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 10.797    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.337    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 10.797    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.814     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.814     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.803     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 8.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 8.302     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 10.000    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 8.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 9.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 9.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.762     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.762     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 9.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 9.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 8.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 9.010     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 7.528     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 8.663     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 8.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 9.151     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 8.987     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 19.203    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 7.030     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.307     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.997     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.307     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.652     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.652     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.637     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.637     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.121    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 10.533    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 7.664     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 7.723     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.878     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.509     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.509     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.055    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.055    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 10.797    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.337    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 10.797    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.814     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.814     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.189     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.803     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 8.236     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 8.302     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 10.000    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 8.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 9.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 9.000     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.762     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.762     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 9.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 9.038     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 8.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 9.010     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 7.528     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 8.663     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 8.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 9.151     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 8.987     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 8.182     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 19.203    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 10.402    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 10.402    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 9.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 10.402    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 10.402    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Fast Model Setup Summary                                                            ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -0.296 ; -0.571        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -0.296 ; -0.571        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.788  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.788  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2.514  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2.514  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 24.520 ; 0.000         ;
; CODEC_SCLK                                                 ; 36.825 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.707 ; 0.000         ;
; CLK_PLL1                                                   ; 59.706 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 61.754 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Hold Summary                                                            ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.093 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.093 ; 0.000         ;
; CODEC_SCLK                                                 ; 0.110 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 0.215 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.215 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.215 ; 0.000         ;
; CLK_PLL1                                                   ; 0.240 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 27.015 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 27.015 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 27.018 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 27.018 ; 0.000         ;
; CODEC_SCLK                                                 ; 80.111 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.981 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.981 ; 0.000         ;
; CODEC_SCLK                                                 ; 1.150 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1.171 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1.171 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 8.289  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 8.289  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 11.695 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.498 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.498 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.531 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 29.231 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 29.231 ; 0.000         ;
; CLK_PLL1                                                   ; 30.250 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.250 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; CODEC_SCLK                                                 ; 38.573 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.296 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 10.757     ;
; -0.296 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 10.757     ;
; -0.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.735     ;
; -0.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.735     ;
; -0.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 10.660     ;
; -0.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.012      ; 10.660     ;
; -0.178 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.638     ;
; -0.178 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.638     ;
; -0.093 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.566     ;
; -0.093 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.566     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.558     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.559     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.558     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.559     ;
; -0.084 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.557     ;
; -0.084 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.557     ;
; -0.072 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.544     ;
; -0.072 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.544     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.536     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.537     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.536     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.537     ;
; -0.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.535     ;
; -0.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.535     ;
; -0.059 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.532     ;
; -0.059 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.532     ;
; -0.039 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.513     ;
; -0.039 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.513     ;
; -0.038 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.510     ;
; -0.038 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.023      ; 10.510     ;
; -0.018 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.491     ;
; -0.018 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.024      ; 10.491     ;
; 0.020  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.437     ;
; 0.020  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.437     ;
; 0.079  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.374     ;
; 0.079  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.374     ;
; 0.081  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 10.381     ;
; 0.081  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 10.381     ;
; 0.085  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.368     ;
; 0.085  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.368     ;
; 0.117  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.340     ;
; 0.117  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.340     ;
; 0.118  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.003      ; 10.334     ;
; 0.118  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.003      ; 10.334     ;
; 0.151  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.306     ;
; 0.151  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.306     ;
; 0.171  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.282     ;
; 0.171  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.282     ;
; 0.176  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.277     ;
; 0.176  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.277     ;
; 0.178  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 10.284     ;
; 0.178  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.013      ; 10.284     ;
; 0.182  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.271     ;
; 0.182  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.271     ;
; 0.197  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.256     ;
; 0.197  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.256     ;
; 0.214  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 10.249     ;
; 0.214  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.014      ; 10.249     ;
; 0.215  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.003      ; 10.237     ;
; 0.215  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.003      ; 10.237     ;
; 0.221  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.239     ;
; 0.221  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.011      ; 10.239     ;
; 0.223  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.246     ;
; 0.223  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.246     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.238     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 10.239     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.238     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 10.239     ;
; 0.232  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.237     ;
; 0.232  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.237     ;
; 0.241  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.216     ;
; 0.241  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.216     ;
; 0.242  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.211     ;
; 0.242  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.211     ;
; 0.248  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.209     ;
; 0.248  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.209     ;
; 0.257  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.212     ;
; 0.257  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.020      ; 10.212     ;
; 0.260  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 10.179     ;
; 0.260  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 10.179     ;
; 0.268  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.185     ;
; 0.268  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.004      ; 10.185     ;
; 0.277  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 10.193     ;
; 0.277  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.021      ; 10.193     ;
; 0.281  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 10.157     ;
; 0.281  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.011     ; 10.157     ;
; 0.282  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.183     ;
; 0.282  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.183     ;
; 0.284  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.190     ;
; 0.284  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.025      ; 10.190     ;
; 0.285  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 10.154     ;
; 0.285  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; -0.010     ; 10.154     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.169     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.177     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.008      ; 10.169     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.177     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.175     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 10.176     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.016      ; 10.175     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 10.417       ; 0.017      ; 10.176     ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.296 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 10.757     ;
; -0.296 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 10.757     ;
; -0.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.735     ;
; -0.275 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.735     ;
; -0.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 10.660     ;
; -0.199 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.012      ; 10.660     ;
; -0.178 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.638     ;
; -0.178 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.638     ;
; -0.093 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.566     ;
; -0.093 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.566     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.558     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.559     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.558     ;
; -0.085 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.559     ;
; -0.084 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.557     ;
; -0.084 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.557     ;
; -0.072 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.544     ;
; -0.072 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.544     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.536     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.537     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.536     ;
; -0.064 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.537     ;
; -0.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.535     ;
; -0.063 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.535     ;
; -0.059 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.532     ;
; -0.059 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.532     ;
; -0.039 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.513     ;
; -0.039 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.513     ;
; -0.038 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.510     ;
; -0.038 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.023      ; 10.510     ;
; -0.018 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.491     ;
; -0.018 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.024      ; 10.491     ;
; 0.020  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.437     ;
; 0.020  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.437     ;
; 0.079  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.374     ;
; 0.079  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.374     ;
; 0.081  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 10.381     ;
; 0.081  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 10.381     ;
; 0.085  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.368     ;
; 0.085  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.368     ;
; 0.117  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.340     ;
; 0.117  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.340     ;
; 0.118  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.003      ; 10.334     ;
; 0.118  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.003      ; 10.334     ;
; 0.151  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.306     ;
; 0.151  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.306     ;
; 0.171  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.282     ;
; 0.171  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.282     ;
; 0.176  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.277     ;
; 0.176  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.277     ;
; 0.178  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 10.284     ;
; 0.178  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.013      ; 10.284     ;
; 0.182  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.271     ;
; 0.182  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.271     ;
; 0.197  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.256     ;
; 0.197  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.256     ;
; 0.214  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 10.249     ;
; 0.214  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.014      ; 10.249     ;
; 0.215  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.003      ; 10.237     ;
; 0.215  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.003      ; 10.237     ;
; 0.221  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.239     ;
; 0.221  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.011      ; 10.239     ;
; 0.223  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.246     ;
; 0.223  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.246     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.238     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 10.239     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.238     ;
; 0.231  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 10.239     ;
; 0.232  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.237     ;
; 0.232  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.237     ;
; 0.241  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.216     ;
; 0.241  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.216     ;
; 0.242  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.211     ;
; 0.242  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.211     ;
; 0.248  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.209     ;
; 0.248  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.209     ;
; 0.257  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.212     ;
; 0.257  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.020      ; 10.212     ;
; 0.260  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 10.179     ;
; 0.260  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 10.179     ;
; 0.268  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.185     ;
; 0.268  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.004      ; 10.185     ;
; 0.277  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 10.193     ;
; 0.277  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.021      ; 10.193     ;
; 0.281  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 10.157     ;
; 0.281  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.011     ; 10.157     ;
; 0.282  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.183     ;
; 0.282  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.183     ;
; 0.284  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.190     ;
; 0.284  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.025      ; 10.190     ;
; 0.285  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 10.154     ;
; 0.285  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; -0.010     ; 10.154     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.169     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.177     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.008      ; 10.169     ;
; 0.288  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.177     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.175     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 10.176     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.016      ; 10.175     ;
; 0.290  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3]         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10.417       ; 0.017      ; 10.176     ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.788 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.655      ;
; 0.788 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.655      ;
; 0.807 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.644      ;
; 0.807 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.644      ;
; 0.820 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.641      ;
; 0.820 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.641      ;
; 0.845 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.606      ;
; 0.845 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.606      ;
; 0.848 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.603      ;
; 0.848 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.603      ;
; 0.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.608      ;
; 0.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.608      ;
; 0.871 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.590      ;
; 0.871 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.590      ;
; 0.875 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.583      ;
; 0.875 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.583      ;
; 0.876 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.570      ;
; 0.876 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.570      ;
; 0.878 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.565      ;
; 0.878 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.565      ;
; 0.879 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.567      ;
; 0.879 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.567      ;
; 0.885 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.558      ;
; 0.885 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.558      ;
; 0.900 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 9.545      ;
; 0.900 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 9.545      ;
; 0.901 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 9.549      ;
; 0.901 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.001      ; 9.549      ;
; 0.902 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 9.550      ;
; 0.902 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 9.550      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.557      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.557      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.905 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.546      ;
; 0.905 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.546      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.545      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.552      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.545      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.552      ;
; 0.914 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.532      ;
; 0.914 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.532      ;
; 0.917 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.544      ;
; 0.917 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.544      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.524      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.539      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.524      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.539      ;
; 0.920 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.541      ;
; 0.920 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.541      ;
; 0.922 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.538      ;
; 0.922 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.538      ;
; 0.934 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.527      ;
; 0.934 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.527      ;
; 0.936 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.519      ;
; 0.936 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.519      ;
; 0.942 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.509      ;
; 0.942 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.509      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.516      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.516      ;
; 0.945 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.506      ;
; 0.945 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.002      ; 9.506      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.513      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.511      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.513      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.511      ;
; 0.948 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.511      ;
; 0.948 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.511      ;
; 0.954 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 9.498      ;
; 0.954 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.003      ; 9.498      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.506      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 9.490      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.008      ; 9.502      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.506      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.004     ; 9.490      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.008      ; 9.502      ;
; 0.960 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 9.502      ;
; 0.960 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.013      ; 9.502      ;
; 0.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.490      ;
; 0.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.006      ; 9.490      ;
; 0.968 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.493      ;
; 0.968 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.012      ; 9.493      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.970 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.490      ;
; 0.970 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.011      ; 9.490      ;
; 0.972 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.486      ;
; 0.972 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.009      ; 9.486      ;
; 0.973 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.473      ;
; 0.973 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.473      ;
; 0.974 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.485      ;
; 0.974 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; 0.010      ; 9.485      ;
; 0.975 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.468      ;
; 0.975 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.006     ; 9.468      ;
; 0.976 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.470      ;
; 0.976 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 10.417       ; -0.003     ; 9.470      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                         ; To Node                                                                                  ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.788 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.655      ;
; 0.788 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.655      ;
; 0.807 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.644      ;
; 0.807 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.644      ;
; 0.820 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.641      ;
; 0.820 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.641      ;
; 0.845 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.606      ;
; 0.845 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.606      ;
; 0.848 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.603      ;
; 0.848 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.603      ;
; 0.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.608      ;
; 0.850 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.608      ;
; 0.871 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.590      ;
; 0.871 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.590      ;
; 0.875 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.583      ;
; 0.875 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.583      ;
; 0.876 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.570      ;
; 0.876 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.570      ;
; 0.878 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.565      ;
; 0.878 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.565      ;
; 0.879 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.567      ;
; 0.879 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.567      ;
; 0.885 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.558      ;
; 0.885 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.558      ;
; 0.900 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 9.545      ;
; 0.900 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 9.545      ;
; 0.901 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 9.549      ;
; 0.901 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.001      ; 9.549      ;
; 0.902 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 9.550      ;
; 0.902 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 9.550      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.557      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.557      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.904 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.547      ;
; 0.905 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.546      ;
; 0.905 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.546      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.545      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.552      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.545      ;
; 0.906 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.552      ;
; 0.914 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.532      ;
; 0.914 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.532      ;
; 0.917 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.544      ;
; 0.917 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.544      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.524      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.539      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.524      ;
; 0.919 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.539      ;
; 0.920 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.541      ;
; 0.920 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.541      ;
; 0.922 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.538      ;
; 0.922 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.538      ;
; 0.934 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.527      ;
; 0.934 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.527      ;
; 0.936 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.519      ;
; 0.936 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.519      ;
; 0.942 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.509      ;
; 0.942 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.509      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.516      ;
; 0.944 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.516      ;
; 0.945 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.506      ;
; 0.945 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.002      ; 9.506      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.513      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.511      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.513      ;
; 0.947 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.511      ;
; 0.948 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.511      ;
; 0.948 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.511      ;
; 0.954 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 9.498      ;
; 0.954 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.003      ; 9.498      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.506      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 9.490      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.008      ; 9.502      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.506      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.004     ; 9.490      ;
; 0.955 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.008      ; 9.502      ;
; 0.960 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 9.502      ;
; 0.960 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.013      ; 9.502      ;
; 0.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.490      ;
; 0.965 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.006      ; 9.490      ;
; 0.968 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.493      ;
; 0.968 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.012      ; 9.493      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.969 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.491      ;
; 0.970 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.490      ;
; 0.970 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.011      ; 9.490      ;
; 0.972 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.486      ;
; 0.972 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.009      ; 9.486      ;
; 0.973 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.473      ;
; 0.973 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.473      ;
; 0.974 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.485      ;
; 0.974 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; 0.010      ; 9.485      ;
; 0.975 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.468      ;
; 0.975 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.006     ; 9.468      ;
; 0.976 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.470      ;
; 0.976 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 10.417       ; -0.003     ; 9.470      ;
+-------+---------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                 ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.514 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.636      ;
; 2.514 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.636      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.691      ; 9.518      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.544      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.691      ; 9.518      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.544      ;
; 2.733 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.417      ;
; 2.733 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.417      ;
; 2.751 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.414      ;
; 2.751 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.414      ;
; 2.794 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 9.385      ;
; 2.794 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 9.385      ;
; 2.855 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.295      ;
; 2.855 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.295      ;
; 2.864 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 9.285      ;
; 2.864 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 9.285      ;
; 2.874 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.291      ;
; 2.874 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 9.291      ;
; 2.956 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.194      ;
; 2.956 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.702      ; 9.194      ;
; 2.961 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.720      ; 9.207      ;
; 2.961 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.720      ; 9.207      ;
; 3.011 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 9.151      ;
; 3.011 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 9.151      ;
; 3.015 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 9.147      ;
; 3.015 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 9.147      ;
; 3.185 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.964      ;
; 3.185 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.964      ;
; 3.195 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.967      ;
; 3.195 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.967      ;
; 3.198 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 8.967      ;
; 3.198 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.717      ; 8.967      ;
; 3.353 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.730      ; 8.825      ;
; 3.353 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.730      ; 8.825      ;
; 3.362 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.722      ; 8.808      ;
; 3.362 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.722      ; 8.808      ;
; 3.401 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.748      ;
; 3.401 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.701      ; 8.748      ;
; 3.434 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.728      ;
; 3.434 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.728      ;
; 3.518 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.661      ;
; 3.518 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.661      ;
; 3.596 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.583      ;
; 3.596 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.583      ;
; 3.654 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.508      ;
; 3.654 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.714      ; 8.508      ;
; 3.877 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.302      ;
; 3.877 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 1.731      ; 8.302      ;
; 4.351 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.110      ;
; 4.351 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.110      ;
; 4.352 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.109      ;
; 4.352 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.109      ;
; 4.374 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.087      ;
; 4.374 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.087      ;
; 4.403 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.058      ;
; 4.403 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.058      ;
; 4.411 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.050      ;
; 4.411 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 6.050      ;
; 4.427 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.049      ;
; 4.427 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.049      ;
; 4.428 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.048      ;
; 4.428 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.048      ;
; 4.450 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.026      ;
; 4.450 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.026      ;
; 4.470 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.006      ;
; 4.470 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.006      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.990      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.005      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.990      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 6.005      ;
; 4.479 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.997      ;
; 4.479 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.997      ;
; 4.481 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.980      ;
; 4.481 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.980      ;
; 4.487 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.989      ;
; 4.487 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.989      ;
; 4.493 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.983      ;
; 4.493 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.983      ;
; 4.520 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.941      ;
; 4.520 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.941      ;
; 4.522 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.954      ;
; 4.522 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.954      ;
; 4.530 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.946      ;
; 4.530 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.946      ;
; 4.541 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.920      ;
; 4.541 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.920      ;
; 4.542 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.919      ;
; 4.542 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.919      ;
; 4.547 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.929      ;
; 4.547 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.929      ;
; 4.557 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.919      ;
; 4.557 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.919      ;
; 4.564 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.897      ;
; 4.564 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.897      ;
; 4.590 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.886      ;
; 4.590 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.886      ;
; 4.593 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.868      ;
; 4.593 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.013      ; 5.868      ;
; 4.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.880      ;
; 4.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 10.416       ; 0.028      ; 5.880      ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                 ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.514 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.636      ;
; 2.514 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.636      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.691      ; 9.518      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.544      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.691      ; 9.518      ;
; 2.621 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.544      ;
; 2.733 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.417      ;
; 2.733 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.417      ;
; 2.751 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.414      ;
; 2.751 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.414      ;
; 2.794 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 9.385      ;
; 2.794 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 9.385      ;
; 2.855 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.295      ;
; 2.855 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[5] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.295      ;
; 2.864 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 9.285      ;
; 2.864 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 9.285      ;
; 2.874 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.291      ;
; 2.874 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 9.291      ;
; 2.956 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.194      ;
; 2.956 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.702      ; 9.194      ;
; 2.961 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.720      ; 9.207      ;
; 2.961 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.720      ; 9.207      ;
; 3.011 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 9.151      ;
; 3.011 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 9.151      ;
; 3.015 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 9.147      ;
; 3.015 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 9.147      ;
; 3.185 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.964      ;
; 3.185 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.964      ;
; 3.195 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.967      ;
; 3.195 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.967      ;
; 3.198 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 8.967      ;
; 3.198 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.717      ; 8.967      ;
; 3.353 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.730      ; 8.825      ;
; 3.353 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.730      ; 8.825      ;
; 3.362 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.722      ; 8.808      ;
; 3.362 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.722      ; 8.808      ;
; 3.401 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.748      ;
; 3.401 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.701      ; 8.748      ;
; 3.434 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.728      ;
; 3.434 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.728      ;
; 3.518 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.661      ;
; 3.518 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.661      ;
; 3.596 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.583      ;
; 3.596 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.583      ;
; 3.654 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.508      ;
; 3.654 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[0]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.714      ; 8.508      ;
; 3.877 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.302      ;
; 3.877 ; I_SYSCLOCKS|altpll_component|pll|clk[0]         ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 1.731      ; 8.302      ;
; 4.351 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.110      ;
; 4.351 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.110      ;
; 4.352 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.109      ;
; 4.352 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.109      ;
; 4.374 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.087      ;
; 4.374 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.087      ;
; 4.403 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.058      ;
; 4.403 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.058      ;
; 4.411 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.050      ;
; 4.411 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 6.050      ;
; 4.427 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.049      ;
; 4.427 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.049      ;
; 4.428 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.048      ;
; 4.428 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.048      ;
; 4.450 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.026      ;
; 4.450 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.026      ;
; 4.470 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.006      ;
; 4.470 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.006      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.990      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.005      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.990      ;
; 4.471 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 6.005      ;
; 4.479 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.997      ;
; 4.479 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.997      ;
; 4.481 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.980      ;
; 4.481 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.980      ;
; 4.487 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.989      ;
; 4.487 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.989      ;
; 4.493 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.983      ;
; 4.493 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.983      ;
; 4.520 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.941      ;
; 4.520 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[6] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.941      ;
; 4.522 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.954      ;
; 4.522 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.954      ;
; 4.530 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.946      ;
; 4.530 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.946      ;
; 4.541 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.920      ;
; 4.541 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.920      ;
; 4.542 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.919      ;
; 4.542 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.919      ;
; 4.547 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.929      ;
; 4.547 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.929      ;
; 4.557 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.919      ;
; 4.557 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.919      ;
; 4.564 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.897      ;
; 4.564 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.897      ;
; 4.590 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.886      ;
; 4.590 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.886      ;
; 4.593 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.868      ;
; 4.593 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|ADDRESS[7] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.013      ; 5.868      ;
; 4.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.880      ;
; 4.596 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11] ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DATA_I[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 10.416       ; 0.028      ; 5.880      ;
+-------+-------------------------------------------------+---------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 24.520 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.902      ;
; 24.562 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.860      ;
; 24.577 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.845      ;
; 24.761 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.661      ;
; 24.776 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.646      ;
; 24.824 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.598      ;
; 24.863 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.559      ;
; 24.901 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.521      ;
; 24.911 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.511      ;
; 25.055 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 25.390       ; 0.000      ; 0.367      ;
+--------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CODEC_SCLK'                                                                                                                              ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                   ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[23]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[22]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[21]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[20]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[19]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[18]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[17]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[16]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[12]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[9]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.825 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[8]   ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.059      ; 3.966      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[179] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[178] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[177] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[176] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[175] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[174] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[173] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.902 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[172] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.069      ; 3.899      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[86]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[85]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[84]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[83]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[82]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[81]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[80]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[79]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[78]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[77]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[76]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.991 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[75]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.797      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[74]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[67]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 36.992 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[63]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.058      ; 3.798      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[167] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[164] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.005 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[153] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.048      ; 3.775      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[102] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[101] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[100] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[99]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[98]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[97]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[96]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[95]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[94]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[93]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[92]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[91]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[90]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[89]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[88]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.006 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[87]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.051      ; 3.777      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[171] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[170] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[169] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[168] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[62]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[61]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[60]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[59]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[58]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[57]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[15]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[14]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.061 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[13]  ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.056      ; 3.727      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[152] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[151] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[146] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[145] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[144] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[143] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[142] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[141] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
; 37.103 ; A4299:I_4299|BUFFER_IN[233] ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[140] ; CODEC_SCLK   ; CODEC_SCLK  ; 40.700       ; 0.047      ; 3.676      ;
+--------+-----------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 38.707 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.387      ;
; 38.727 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
; 38.727 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 39.062       ; 0.000      ; 0.367      ;
+--------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 59.706 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.031     ; 2.795      ;
; 59.757 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.031     ; 2.744      ;
; 59.938 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.031     ; 2.563      ;
; 60.000 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.031     ; 2.501      ;
; 60.047 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.031     ; 2.454      ;
; 61.350 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.182      ;
; 61.350 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.182      ;
; 61.350 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.182      ;
; 61.350 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.182      ;
; 61.350 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.182      ;
; 61.401 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.131      ;
; 61.401 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.131      ;
; 61.401 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.131      ;
; 61.401 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.131      ;
; 61.401 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.131      ;
; 61.570 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.962      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.950      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.950      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.950      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.950      ;
; 61.582 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.950      ;
; 61.621 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.911      ;
; 61.644 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.888      ;
; 61.644 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.888      ;
; 61.644 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.888      ;
; 61.644 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.888      ;
; 61.644 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.888      ;
; 61.691 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.841      ;
; 61.691 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.841      ;
; 61.691 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.841      ;
; 61.691 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.841      ;
; 61.691 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.841      ;
; 61.802 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.730      ;
; 61.864 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.668      ;
; 61.911 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.621      ;
; 62.092 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.440      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 61.754 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.002      ; 0.780      ;
; 61.759 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.002      ; 0.775      ;
; 61.815 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.002      ; 0.719      ;
; 61.879 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.002      ; 0.655      ;
; 61.917 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.615      ;
; 62.007 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.525      ;
; 62.010 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.522      ;
; 62.022 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.510      ;
; 62.127 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.405      ;
; 62.129 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.403      ;
; 62.129 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.403      ;
; 62.132 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.400      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                        ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                           ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.093 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 1.936      ;
; 0.093 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 1.936      ;
; 0.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 1.940      ;
; 0.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 1.940      ;
; 0.184 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 2.027      ;
; 0.184 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.691      ; 2.027      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[1]                                                                    ; \SLOW_CPU:TMP[1]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[0]                                                                    ; \SLOW_CPU:TMP[0]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[2]                                                                    ; \SLOW_CPU:TMP[2]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; SYNCn                                                                               ; SYNCn                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; VMA_68K30Ln                                                                         ; VMA_68K30Ln                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                        ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                           ; To Node                                                                             ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.093 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 1.936      ;
; 0.093 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 1.936      ;
; 0.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 1.940      ;
; 0.097 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 1.940      ;
; 0.184 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 2.027      ;
; 0.184 ; I_SYSCLOCKS|altpll_component|pll|clk[0]                                             ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T2_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.691      ; 2.027      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\OUTBUFFERS:OP_STOP     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.WRITE                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DMA_PHASE.READ                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[0]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_RDYOUT:TMP[1]                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|BKPT_REQ                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.HALTED         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.BKPT~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|PHASE2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|ALU_BSY                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|PIPE_FULL               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_RESET              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_INT                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_ILLEGAL            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|ADR_OFFSET[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_STATUS ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTS~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPcc             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[1]                                                                    ; \SLOW_CPU:TMP[1]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[0]                                                                    ; \SLOW_CPU:TMP[0]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \SLOW_CPU:TMP[2]                                                                    ; \SLOW_CPU:TMP[2]                                                                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_WR                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; SYNCn                                                                               ; SYNCn                                                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.RESTORE_PC     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|WRITE_CYCLE                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAP               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\PIPE_STATUS:CNT[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|CAS2_COND                                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TST~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[1]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEP_PNTR_I[0]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MOVEM_FIRST_RD                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; VMA_68K30Ln                                                                         ; VMA_68K30Ln                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[0]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; WF68K30L_TOP:I_CPU|FC_LATCH[2]                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T3_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.T1_RD_DEST            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                                              ; To Node                                                                                                                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.110 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[180]                                                                          ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.132      ; 0.394      ;
; 0.111 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[179]                                                                          ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.132      ; 0.395      ;
; 0.149 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                          ; A4299:I_4299|BUFFER_IN[219]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.096      ; 0.397      ;
; 0.190 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.499      ;
; 0.191 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.500      ;
; 0.192 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.501      ;
; 0.194 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[7] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.499      ;
; 0.194 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.503      ;
; 0.195 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[6] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.500      ;
; 0.196 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[5] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.501      ;
; 0.198 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[4] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.503      ;
; 0.199 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.508      ;
; 0.200 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.509      ;
; 0.200 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.171      ; 0.509      ;
; 0.201 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[178]                                                                          ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.126      ; 0.479      ;
; 0.203 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[162]                                                                          ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.043      ; 0.398      ;
; 0.203 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[3] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.508      ;
; 0.204 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|BUFFER_IN[244]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.043      ; 0.399      ;
; 0.204 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[161]                                                                          ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.043      ; 0.399      ;
; 0.204 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                          ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.043      ; 0.399      ;
; 0.204 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[1] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.509      ;
; 0.204 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|cntr_4of:cntr1|safe_q[2] ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.167      ; 0.509      ;
; 0.211 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[230]                                                                          ; A4299:I_4299|BUFFER_IN[231]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.115      ; 0.478      ;
; 0.212 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]                                                                          ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.238      ; 0.602      ;
; 0.212 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[229]                                                                          ; A4299:I_4299|BUFFER_IN[230]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.115      ; 0.479      ;
; 0.215 ; A4299:I_4299|INT                                                                                                       ; A4299:I_4299|INT                                                                                                                                          ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; A4299:I_4299|SYNC                                                                                                      ; A4299:I_4299|SYNC                                                                                                                                         ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.367      ;
; 0.237 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[193]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.389      ;
; 0.238 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[24]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[25]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[10]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[11]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.097      ; 0.487      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[105]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[106]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[66]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[55]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[56]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[35]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[30]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[248]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[249]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[214]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[215]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[191]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[192]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                 ; A4299:I_4299|\CODEC_TRANSMIT:BITCNT[7]                                                                                                                    ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[33]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[221]                                                                          ; A4299:I_4299|BUFFER_IN[222]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.096      ; 0.488      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[175]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[176]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.392      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[167]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[72]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[73]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[70]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[71]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[51]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[52]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[36]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[245]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[246]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[227]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[228]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[212]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[213]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.241 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[205]                                                                          ; A4299:I_4299|BUFFER_IN[206]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.393      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[165]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[166]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[162]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[163]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[158]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[159]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[154]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[155]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[68]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[69]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[64]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[65]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[46]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[47]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[37]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[38]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[252]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[253]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[161]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[162]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[165]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[188]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.242 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[164]                                                                          ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.394      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[160]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[161]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[49]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[50]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[34]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[35]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[31]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[32]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[26]                                                                          ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[27]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[231]                                                                          ; A4299:I_4299|BUFFER_IN[232]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[236]                                                                          ; A4299:I_4299|BUFFER_IN[237]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[166]                                                                          ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[169]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[170]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.243 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.395      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[253]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[254]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[240]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[241]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.244 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[168]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.396      ;
; 0.245 ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[156]                                                                         ; A4299:I_4299|\CODEC_TRANSMIT:SHIFTREG_OUT[157]                                                                                                            ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[217]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[210]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[211]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[243]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[244]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[179]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[180]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.245 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[194]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.397      ;
; 0.246 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[187]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.398      ;
; 0.246 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[184]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.398      ;
; 0.247 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[222]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[223]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.399      ;
; 0.247 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[195]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[196]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.399      ;
; 0.247 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[185]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[186]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.399      ;
; 0.247 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[173]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[174]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.399      ;
; 0.248 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[218]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[219]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.400      ;
; 0.252 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[201]                                                                          ; A4299:I_4299|BUFFER_IN[202]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.000      ; 0.404      ;
; 0.252 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[171]                                                                          ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.098      ; 0.502      ;
; 0.256 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[182]                                                                          ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[183]                                                                                                             ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.195      ; 0.603      ;
; 0.282 ; A4299:I_4299|\CODEC_RECEIEVE:SHIFTREG_IN[167]                                                                          ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.231      ; 0.665      ;
+-------+------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.222 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.022      ; 0.398      ;
; 0.223 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.002        ; 0.022      ; 0.399      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]     ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[7]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.392      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                   ; To Node                                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:TIME_SLICE_CNT[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:TIME_SLICE_CNT[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.RAM                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MCU_PHASE_I.DMA                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[4]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:TEMP[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|DTACK_MCUn                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.222 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.022      ; 0.398      ;
; 0.223 ; SCLK_6M4                                                                                    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.002        ; 0.022      ; 0.399      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.239 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.391      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]     ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[14]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[12]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[13]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]          ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]           ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[7]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[23]                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[24]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.000      ; 0.392      ;
+-------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                                                                                                        ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                                     ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[0]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET_RECOVERY  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.WRITE_ITL_PTD               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|TIMEOUT                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Tx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.SYNC_DATA                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Tx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_READ                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][2]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_RD_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[2]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_HEADER[1][3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET_RECOVERY ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL0_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmInterval[31]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[1]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SOC[0]                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_RD_MC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ITL1_WR_HC                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_MC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|ATL_WR_HC_I                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_HI           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\DATA_TIMING:TIMER[1]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|uPInterrupt[6]                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ATL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|DMA_STATE.ITL_WRITE                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:EOP_BIT[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16[16]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|FmRemaining[31]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_I         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:CRC16_LO           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|\UPSTREAM_CTRL:SE0_LOCK_II        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[3]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[0]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\FIFO_CONTROL:SCND_SCAN              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[2]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[7]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:PACKET_SIZE[1]     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|RhDescriptorA[1]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[5]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL0_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ITL1_BUFF_DONE                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|ATL_BUFF_DONE                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.READ_HI                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_II                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_ATTACHED                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_II_STATE.PORT_RESET          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|SPEED_I                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.PREAMBLE                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.HANDSHAKE_Rx               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_Rx                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_HI                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[1]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|PTD_CNT[0]                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TOKEN_SOF                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.TRANSMIT_ITL_DATA           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_PID                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_ATTACHED                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; USB1160_TOP:I_USB|ROOTHUB_2PORT:I_ROOTHUB|PORT_I_STATE.PORT_RESET           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.WRITE_LO                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BUS_CYCLE.COMMAND                    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ATL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|HC_STATE.RECEIVE_ITL_DATA            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SETUP_RDY                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|\NRZI_TRANSCEIVER:NRZI_OUT           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.TOKEN_EOP                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; USB1160_TOP:I_USB|HOST_CONTROLLER:I_HC|SIE_STATE.DATA_EOP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; USB1160_TOP:I_USB|MC_INTERFACE:I_MC_IF|BufferStatus[1]                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 0.000        ; 0.000      ; 0.367      ;
+-------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                  ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; SCLK_6M4          ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.367      ;
; 0.235 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.000      ; 0.387      ;
+-------+-------------------+-------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                          ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.359 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.511      ;
; 0.369 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.521      ;
; 0.407 ; CLK_24576             ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.559      ;
; 0.446 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.598      ;
; 0.494 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.646      ;
; 0.509 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.661      ;
; 0.693 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.845      ;
; 0.708 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.860      ;
; 0.750 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
+-------+-----------------------+-----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; CLK_0M5              ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.248 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.400      ;
; 0.251 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.403      ;
; 0.251 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.403      ;
; 0.253 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.405      ;
; 0.358 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.510      ;
; 0.370 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.522      ;
; 0.373 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.525      ;
; 0.463 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.615      ;
; 0.501 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.002      ; 0.655      ;
; 0.565 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.002      ; 0.719      ;
; 0.621 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.002      ; 0.775      ;
; 0.626 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.002      ; 0.780      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.240 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.392      ;
; 0.288 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.440      ;
; 0.364 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.516      ;
; 0.365 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.517      ;
; 0.373 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.525      ;
; 0.374 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.526      ;
; 0.469 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.621      ;
; 0.502 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.654      ;
; 0.503 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.655      ;
; 0.513 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.665      ;
; 0.514 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.666      ;
; 0.516 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.668      ;
; 0.537 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.689      ;
; 0.538 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.690      ;
; 0.548 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.700      ;
; 0.572 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.724      ;
; 0.578 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.730      ;
; 0.583 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.735      ;
; 0.607 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.759      ;
; 0.689 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.841      ;
; 0.689 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.841      ;
; 0.736 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.888      ;
; 0.736 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.888      ;
; 0.736 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.888      ;
; 0.759 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.911      ;
; 0.798 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.950      ;
; 0.798 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.950      ;
; 0.798 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.950      ;
; 0.798 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.950      ;
; 0.810 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.962      ;
; 1.030 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.182      ;
; 2.333 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.031     ; 2.454      ;
; 2.380 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.031     ; 2.501      ;
; 2.442 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.031     ; 2.563      ;
; 2.623 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.031     ; 2.744      ;
; 2.674 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; -0.031     ; 2.795      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                              ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.264      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; -0.003     ; 4.263      ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                              ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                           ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.000      ; 4.267      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.015 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.264      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[3]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.007      ; 4.273      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.009      ; 4.275      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.005     ; 4.261      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.012      ; 4.278      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.004     ; 4.262      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
; 27.016 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; -0.003     ; 4.263      ;
+--------+------------------------------------------------+-------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                                               ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.036      ; 4.300      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_STATUS                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[4]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[0]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[2]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[1]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.003      ; 4.267      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.033      ; 4.297      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 4.287      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.025      ; 4.289      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][13]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.023      ; 4.287      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][4]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 4.290      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][4]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.026      ; 4.290      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.028      ; 4.292      ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                      ; To Node                                                                               ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.036      ; 4.300      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[15]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_STATUS                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[4]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[0]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.035      ; 4.299      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[2]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[1]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[3]                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.011      ; 4.275      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[3]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.003      ; 4.267      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[2]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][15]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\PRESCALER:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.001      ; 4.265      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][15]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][14]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.033      ; 4.297      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.012      ; 4.276      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 4.287      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[8][14]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.029      ; 4.293      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.017      ; 4.281      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[3]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.005      ; 4.269      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.025      ; 4.289      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][6]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][6]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][5]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][12]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][12]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][13]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.030      ; 4.294      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][13]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.023      ; 4.287      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][0]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.032      ; 4.296      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][8]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.027      ; 4.291      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][4]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 4.290      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][4]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.026      ; 4.290      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][7]           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.031      ; 4.295      ;
; 27.018 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][11]          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.028      ; 4.292      ;
+--------+------------------------------------------------+---------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 80.111 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 81.400       ; 0.247      ; 1.535      ;
+--------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                                 ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.013      ; 1.146      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.002      ; 1.158      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[4]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.033      ; 2.607      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[5]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[7]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[6]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[8]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[13]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[2]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[4]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.033      ; 2.607      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[5]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[7]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[6]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[8]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[13]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[2]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.003      ; 2.577      ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                      ; To Node                                                                                 ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 0.981 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.013      ; 1.146      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 1.004 ; RESET_CORE_Sn                                  ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.002      ; 1.158      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[4]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.033      ; 2.607      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[5]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[7]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[6]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[8]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[13]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[2]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.022      ; 2.596      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.028      ; 2.602      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[15]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.027      ; 2.601      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[14]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.049      ; 2.623      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[4]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.033      ; 2.607      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[5]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[7]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[6]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[12]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[0]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[8]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[13]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[3]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[2]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[1]                                                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; MDAT_BUFFER[10]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.019      ; 2.593      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[0]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[1]            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
; 2.422 ; WF25912IP_SD_TOP_CTYPE_SOC:I_MCU|INIT_STATE[0] ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 0.003      ; 2.577      ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'CODEC_SCLK'                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                           ; To Node                                                                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.150 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|dffe4 ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0 ; CODEC_SCLK   ; CODEC_SCLK  ; 0.000        ; 0.247      ; 1.535      ;
+-------+-----------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.333      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.424      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.525      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.017      ; 1.549      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.008      ; 1.664      ;
; 1.508 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.670      ;
; 1.508 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.010      ; 1.670      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.016      ; 1.681      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                  ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.171 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.333      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.271 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.424      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.525      ;
; 1.372 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.525      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.001     ; 1.531      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.380 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.017      ; 1.549      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.504 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.008      ; 1.664      ;
; 1.508 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.670      ;
; 1.508 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.010      ; 1.670      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.016      ; 1.681      ;
+-------+---------------+--------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1'                                                                                                                                                                    ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                     ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a0~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a1~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a2~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a3~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a4~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg7  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg8  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_address_reg9  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_datain_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_memory_reg0   ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a5~porta_we_reg        ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg1  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg10 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg11 ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg2  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg3  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg4  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg5  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg6  ;
; 8.289 ; 10.416       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; Rise       ; USB1160_TOP:I_USB|FIFO_BUFFER:I_FIFO|altsyncram:FIFO_rtl_0|altsyncram_ec41:auto_generated|ram_block1a6~porta_address_reg7  ;
+-------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576                                           ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]                               ;
; 11.695 ; 12.695       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 11.695 ; 12.695       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]                               ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; CLK_24576|clk                                       ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|inclk[0] ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk1~clkctrl|outclk   ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
; 12.695 ; 12.695       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                           ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg1   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg10  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg11  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg2   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg3   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg4   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg5   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg6   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg7   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg8   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_address_reg9   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_datain_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_memory_reg0    ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a0~porta_we_reg         ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a10~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_address_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_datain_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_memory_reg0   ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a11~porta_we_reg        ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; altsyncram:VRAM_rtl_0|altsyncram_3e41:auto_generated|ram_block1a12~porta_address_reg2  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4                                            ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]                                   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|inclk[0] ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk0~clkctrl|outclk   ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; SCLK_6M4|clk                                        ;
; 19.531 ; 19.531       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
; 19.531 ; 19.531       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; \P_6M4:TMP_6M4[0]|clk                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_0M5|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CODEC_SCLK'                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock      ; Clock Edge ; Target                                                                                                                                                    ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0                    ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_datain_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~porta_memory_reg0  ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg0 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg1 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg2 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg3 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg4 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg5 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg6 ;
; 38.573 ; 40.700       ; 2.127          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 38.573 ; 40.700       ; 2.127          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|altshift_taps:\CODEC_RECEIEVE:SHIFTREG_IN[1]_rtl_0|shift_taps_ihm:auto_generated|altsyncram_21b1:altsyncram2|ram_block5a0~portb_address_reg7 ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[162]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[163]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[164]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[165]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[166]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[167]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[168]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[169]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[170]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[171]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[172]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[173]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[174]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[175]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[176]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[177]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[178]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[179]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[180]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[181]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[182]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[183]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[184]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[185]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[186]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[187]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[188]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[189]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[190]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[191]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; High Pulse Width ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
; 39.700 ; 40.700       ; 1.000          ; Low Pulse Width  ; CODEC_SCLK ; Fall       ; A4299:I_4299|BUFFER_IN[192]                                                                                                                               ;
+--------+--------------+----------------+------------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.116  ; 0.116  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 4.704  ; 4.704  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.087  ; 0.087  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 5.500  ; 5.500  ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 12.818 ; 12.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.852  ; 3.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 6.080  ; 6.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.822  ; 3.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.142  ; 5.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 4.670  ; 4.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 4.834  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 4.779  ; 4.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 4.771  ; 4.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 5.102  ; 5.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 5.142  ; 5.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 4.979  ; 4.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 8.204  ; 8.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.452  ; 8.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 9.340  ; 9.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 5.393  ; 5.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 14.735 ; 14.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 9.630  ; 9.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 9.622  ; 9.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 14.735 ; 14.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 10.248 ; 10.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 6.642  ; 6.642  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.404  ; 7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 8.015  ; 8.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 6.967  ; 6.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.334  ; 7.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.578  ; 7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 7.771  ; 7.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.838  ; 7.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.994  ; 7.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.401  ; 7.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.873  ; 5.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.589  ; 5.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 4.674  ; 4.674  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.161  ; 6.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 12.636 ; 12.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 12.636 ; 12.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 12.442 ; 12.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 12.532 ; 12.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 6.428  ; 6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 2.801  ; 2.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 5.484  ; 5.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 7.668  ; 7.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 4.238  ; 4.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 4.937  ; 4.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 9.429  ; 9.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 12.023 ; 12.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 9.266  ; 9.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.911  ; 8.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.672  ; 7.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.841  ; 7.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.135  ; 8.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 8.911  ; 8.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.056  ; 8.056  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.637  ; 8.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 2.223  ; 2.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 1.911  ; 1.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 2.320  ; 2.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 2.195  ; 2.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 2.206  ; 2.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.472  ; 9.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.273  ; 8.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.415  ; 9.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.653  ; 8.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.590  ; 8.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.760  ; 8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.128  ; 9.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.212  ; 9.212  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.742  ; 8.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.854  ; 8.854  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.984  ; 8.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.512  ; 8.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.889  ; 8.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.197  ; 9.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.472  ; 9.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 1.875  ; 1.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.475  ; 4.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 12.178 ; 12.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 4.426  ; 4.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 4.663  ; 4.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 4.535  ; 4.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 4.481  ; 4.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 4.673  ; 4.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 4.546  ; 4.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.525  ; 4.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.682  ; 4.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.632  ; 5.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.486  ; 5.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 5.502  ; 5.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.754  ; 4.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 7.035  ; 7.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 3.766  ; 3.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 6.628  ; 6.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 11.395 ; 11.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 4.063  ; 4.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 5.036  ; 5.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 4.678  ; 4.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 4.632  ; 4.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 4.678  ; 4.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 4.553  ; 4.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 4.077  ; 4.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 4.250  ; 4.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 5.277  ; 5.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 4.832  ; 4.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 12.288 ; 12.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 4.900  ; 4.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 4.434  ; 4.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 11.759 ; 11.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.723  ; 3.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 4.551  ; 4.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.436  ; 4.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 3.727  ; 3.727  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 7.984  ; 7.984  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.193  ; 8.193  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 8.247  ; 8.247  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 13.836 ; 13.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.976  ; 8.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.968  ; 8.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 13.836 ; 13.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 10.028 ; 10.028 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 6.261  ; 6.261  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.988  ; 5.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 6.805  ; 6.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.319  ; 7.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.808  ; 7.808  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 7.204  ; 7.204  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 6.667  ; 6.667  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 7.182  ; 7.182  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 7.347  ; 7.347  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 7.166  ; 7.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.233  ; 7.233  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 7.618  ; 7.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.610  ; 7.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.221  ; 7.221  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 6.770  ; 6.770  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 4.780  ; 4.780  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 4.613  ; 4.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 7.485  ; 7.485  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 1.400  ; 1.400  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 1.904  ; 1.904  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 1.670  ; 1.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 11.650 ; 11.650 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 11.650 ; 11.650 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 11.456 ; 11.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 11.546 ; 11.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 4.365  ; 4.365  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 4.060  ; 4.060  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.661  ; 8.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 4.487  ; 4.487  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.798  ; 8.798  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 10.964 ; 10.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 8.661  ; 8.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.320  ; 8.320  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.582  ; 7.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.824  ; 7.824  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.752  ; 7.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 8.320  ; 8.320  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.425  ; 7.425  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.794  ; 7.794  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.963  ; 7.963  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.330  ; 9.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.814  ; 7.814  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.926  ; 8.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.330  ; 9.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.446  ; 8.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.290  ; 8.290  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 8.608  ; 8.608  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 8.897  ; 8.897  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.607  ; 8.607  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.072  ; 8.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.634  ; 8.634  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.600  ; 8.600  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.921  ; 7.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.258  ; 8.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.104  ; 8.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.496  ; 8.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 11.192 ; 11.192 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 10.486 ; 10.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 4.103  ; 4.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 4.012  ; 4.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 11.229 ; 11.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 12.818 ; 12.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.852  ; 3.852  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.080  ; 6.080  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.822  ; 3.822  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.142  ; 5.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.670  ; 4.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 4.834  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.779  ; 4.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 4.771  ; 4.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.102  ; 5.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.142  ; 5.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.979  ; 4.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 8.204  ; 8.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.452  ; 8.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 9.340  ; 9.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 5.393  ; 5.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 14.735 ; 14.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 9.630  ; 9.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 9.622  ; 9.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 14.735 ; 14.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 10.248 ; 10.248 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 6.642  ; 6.642  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 8.241  ; 8.241  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.404  ; 7.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 8.015  ; 8.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.967  ; 6.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.334  ; 7.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.578  ; 7.578  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.771  ; 7.771  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.903  ; 7.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.838  ; 7.838  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.994  ; 7.994  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.812  ; 7.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.401  ; 7.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.873  ; 5.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.589  ; 5.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 4.674  ; 4.674  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.161  ; 6.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 12.636 ; 12.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 12.636 ; 12.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 12.442 ; 12.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 12.532 ; 12.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 6.428  ; 6.428  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 2.801  ; 2.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 5.484  ; 5.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 7.668  ; 7.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 4.238  ; 4.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 4.937  ; 4.937  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 9.429  ; 9.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 12.023 ; 12.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 9.266  ; 9.266  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.911  ; 8.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.672  ; 7.672  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.841  ; 7.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.135  ; 8.135  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 8.911  ; 8.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.056  ; 8.056  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.637  ; 8.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 8.442  ; 8.442  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 2.223  ; 2.223  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 1.911  ; 1.911  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 2.320  ; 2.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 2.195  ; 2.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 2.206  ; 2.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.472  ; 9.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 8.273  ; 8.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 9.185  ; 9.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.415  ; 9.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.653  ; 8.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.590  ; 8.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.760  ; 8.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.128  ; 9.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.212  ; 9.212  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.742  ; 8.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.854  ; 8.854  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.984  ; 8.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.512  ; 8.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.889  ; 8.889  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.197  ; 9.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.472  ; 9.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 1.875  ; 1.875  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.475  ; 4.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 12.178 ; 12.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 4.426  ; 4.426  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 4.663  ; 4.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 4.535  ; 4.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 4.481  ; 4.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 4.673  ; 4.673  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 4.546  ; 4.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.525  ; 4.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.682  ; 4.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.632  ; 5.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.486  ; 5.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 5.502  ; 5.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.754  ; 4.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 7.035  ; 7.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 3.766  ; 3.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 6.628  ; 6.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 11.395 ; 11.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 4.063  ; 4.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 5.036  ; 5.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 4.678  ; 4.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 4.632  ; 4.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 4.678  ; 4.678  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 4.553  ; 4.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 4.077  ; 4.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 4.250  ; 4.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 5.277  ; 5.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 4.832  ; 4.832  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 12.288 ; 12.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 4.900  ; 4.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.434  ; 4.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.759 ; 11.759 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.723  ; 3.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 4.551  ; 4.551  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.436  ; 4.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 3.727  ; 3.727  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.984  ; 7.984  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.193  ; 8.193  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 8.247  ; 8.247  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 13.836 ; 13.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.976  ; 8.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.968  ; 8.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 13.836 ; 13.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 10.028 ; 10.028 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 6.261  ; 6.261  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.988  ; 5.988  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.805  ; 6.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.319  ; 7.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.808  ; 7.808  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.204  ; 7.204  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.667  ; 6.667  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.182  ; 7.182  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.347  ; 7.347  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.166  ; 7.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.233  ; 7.233  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.618  ; 7.618  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.610  ; 7.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.221  ; 7.221  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.770  ; 6.770  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 4.613  ; 4.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 7.485  ; 7.485  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 1.400  ; 1.400  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 1.904  ; 1.904  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 1.670  ; 1.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.650 ; 11.650 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.650 ; 11.650 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 11.456 ; 11.456 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 11.546 ; 11.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 4.365  ; 4.365  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 4.060  ; 4.060  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.661  ; 8.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 4.487  ; 4.487  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.798  ; 8.798  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.964 ; 10.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 8.661  ; 8.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.320  ; 8.320  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.582  ; 7.582  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.824  ; 7.824  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.752  ; 7.752  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 8.320  ; 8.320  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.425  ; 7.425  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.794  ; 7.794  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.963  ; 7.963  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.330  ; 9.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.814  ; 7.814  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.330  ; 9.330  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.446  ; 8.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.981  ; 7.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.290  ; 8.290  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 8.608  ; 8.608  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.897  ; 8.897  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.607  ; 8.607  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.072  ; 8.072  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.634  ; 8.634  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.600  ; 8.600  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.921  ; 7.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.258  ; 8.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.104  ; 8.104  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.192 ; 11.192 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 10.486 ; 10.486 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 4.103  ; 4.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 4.012  ; 4.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.229 ; 11.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 11.045 ; 11.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 7.125  ; 7.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 7.106  ; 7.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 13.076 ; 13.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.273  ; 8.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 5.741  ; 5.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 13.076 ; 13.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 9.249  ; 9.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 5.558  ; 5.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.285  ; 5.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 7.396  ; 7.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 6.485  ; 6.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 7.396  ; 7.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 6.521  ; 6.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 6.985  ; 6.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 6.759  ; 6.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 6.014  ; 6.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 6.422  ; 6.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 6.644  ; 6.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 6.549  ; 6.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 4.675  ; 4.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 10.992 ; 10.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 10.992 ; 10.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 10.888 ; 10.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 7.944  ; 7.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 10.250 ; 10.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.450  ; 6.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.996  ; 6.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.965  ; 6.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 6.929  ; 6.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.260  ; 7.260  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.494  ; 7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.340  ; 8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.623  ; 7.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.536  ; 7.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.637  ; 7.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.848  ; 7.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 8.194  ; 8.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.990  ; 7.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.631  ; 6.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.579  ; 6.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.572  ; 6.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.182  ; 7.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 6.899  ; 6.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 7.393  ; 7.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 10.534 ; 10.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 10.515 ; 10.515 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 6.882  ; 6.882  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 9.441  ; 9.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 9.441  ; 9.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 6.670  ; 6.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 6.651  ; 6.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 6.062  ; 6.062  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 6.730  ; 6.730  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 11.045 ; 11.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.125  ; 7.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 7.106  ; 7.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 13.076 ; 13.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.273  ; 8.273  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 5.741  ; 5.741  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 13.076 ; 13.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 9.249  ; 9.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 5.558  ; 5.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.285  ; 5.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.396  ; 7.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.485  ; 6.485  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.396  ; 7.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.521  ; 6.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.985  ; 6.985  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.759  ; 6.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.014  ; 6.014  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.422  ; 6.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.644  ; 6.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.549  ; 6.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 4.675  ; 4.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 10.992 ; 10.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 10.992 ; 10.992 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 10.798 ; 10.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 10.888 ; 10.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 7.944  ; 7.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.250 ; 10.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.450  ; 6.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.996  ; 6.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.965  ; 6.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 6.929  ; 6.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.830  ; 7.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.260  ; 7.260  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.494  ; 7.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.340  ; 8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.623  ; 7.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.536  ; 7.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.637  ; 7.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.848  ; 7.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.194  ; 8.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.990  ; 7.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.631  ; 6.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.579  ; 6.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.572  ; 6.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.182  ; 7.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 6.899  ; 6.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 7.393  ; 7.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 10.534 ; 10.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.783  ; 9.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.515 ; 10.515 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 6.882  ; 6.882  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 9.441  ; 9.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 9.441  ; 9.441  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 6.670  ; 6.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 6.651  ; 6.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 6.062  ; 6.062  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 6.730  ; 6.730  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 11.257 ; 11.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 7.298  ; 7.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 7.779  ; 7.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 13.174 ; 13.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 13.174 ; 13.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 9.360  ; 9.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 5.533  ; 5.533  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 5.260  ; 5.260  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.455  ; 6.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.694  ; 6.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 6.946  ; 6.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 5.957  ; 5.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.070  ; 6.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.323  ; 6.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.619  ; 6.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 6.724  ; 6.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 6.542  ; 6.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 6.525  ; 6.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 6.659  ; 6.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.343  ; 6.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 4.312  ; 4.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 4.189  ; 4.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 11.103 ; 11.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 11.103 ; 11.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 10.909 ; 10.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 10.999 ; 10.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 8.234  ; 8.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.371  ; 8.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 10.462 ; 10.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.758  ; 7.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.247  ; 7.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.758  ; 7.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.318  ; 7.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 7.307  ; 7.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.235  ; 7.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.464  ; 7.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.451  ; 8.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.584  ; 7.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.693  ; 7.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.749  ; 7.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 8.169  ; 8.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 7.708  ; 7.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.563  ; 7.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.558  ; 7.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.515  ; 7.515  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.359  ; 7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.831  ; 7.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 7.636  ; 7.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 10.645 ; 10.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 9.834  ; 9.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 10.727 ; 10.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 11.257 ; 11.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 7.298  ; 7.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 7.779  ; 7.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 13.174 ; 13.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 13.174 ; 13.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 9.360  ; 9.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 5.533  ; 5.533  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 5.260  ; 5.260  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.455  ; 6.455  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.507  ; 7.507  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.694  ; 6.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.946  ; 6.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.957  ; 5.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.070  ; 6.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.323  ; 6.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.619  ; 6.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.267  ; 6.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.724  ; 6.724  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.542  ; 6.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.525  ; 6.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.659  ; 6.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.343  ; 6.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 4.312  ; 4.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 4.189  ; 4.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 11.103 ; 11.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 11.103 ; 11.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 10.909 ; 10.909 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 10.999 ; 10.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.234  ; 8.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.371  ; 8.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 10.462 ; 10.462 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.881  ; 7.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.758  ; 7.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.107  ; 7.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.138  ; 7.138  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.247  ; 7.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.758  ; 7.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.318  ; 7.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 7.307  ; 7.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.235  ; 7.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.464  ; 7.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.451  ; 8.451  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.705  ; 8.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.584  ; 7.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.693  ; 7.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.749  ; 7.749  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.169  ; 8.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 7.708  ; 7.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.563  ; 7.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.558  ; 7.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.515  ; 7.515  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.359  ; 7.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.831  ; 7.831  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 7.636  ; 7.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.072  ; 8.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 10.645 ; 10.645 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.834  ; 9.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 10.727 ; 10.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.071  ; 0.071  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -4.120 ; -4.120 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.033  ; 0.033  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -4.849 ; -4.849 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.678 ; -3.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.457 ; -3.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.702 ; -3.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.627 ; -3.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.511 ; -3.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.576 ; -3.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.505 ; -3.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.726 ; -3.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -3.685 ; -3.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -3.695 ; -3.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.241 ; -4.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.156 ; -5.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.494 ; -7.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.023 ; -5.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.449 ; -2.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.176 ; -2.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.573 ; -4.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.624 ; -4.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.404 ; -4.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.837 ; -4.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.733 ; -4.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.304 ; -4.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.146 ; -4.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.276 ; -4.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.186 ; -4.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.040 ; -4.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.134 ; -4.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.018 ; -4.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.736 ; -3.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.998 ; -4.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.894 ; -4.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.205 ; -4.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.346 ; -1.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.466 ; -4.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -3.729 ; -3.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.021 ; -5.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -4.189 ; -4.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.158 ; -5.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.984 ; -3.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -4.255 ; -4.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.344 ; -6.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.566 ; -6.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.336 ; -7.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.065 ; -6.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.776 ; -6.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.576 ; -6.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.334 ; -3.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.441 ; -1.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -1.796 ; -1.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -1.671 ; -1.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.686 ; -1.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.224 ; -4.224 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.318 ; -4.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -5.017 ; -5.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.145 ; -4.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.246 ; -4.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.148 ; -4.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.310 ; -4.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.961 ; -3.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.755 ; -1.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.355 ; -4.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.202 ; -4.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.403 ; -3.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.400 ; -3.400 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.542 ; -3.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.530 ; -3.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.622 ; -3.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.552 ; -3.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.779 ; -3.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.561 ; -3.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -3.739 ; -3.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.890 ; -3.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.240 ; -4.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -3.640 ; -3.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.289 ; -4.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -3.936 ; -3.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.913 ; -4.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.922 ; -3.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.123 ; -4.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -5.154 ; -5.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -3.810 ; -3.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -4.780 ; -4.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -4.011 ; -4.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -5.529 ; -5.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.603 ; -3.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -4.431 ; -4.431 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.316 ; -4.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.607 ; -3.607 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.823 ; -6.823 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.790 ; -6.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -7.326 ; -7.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.608 ; -7.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.600 ; -7.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.866 ; -7.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.620 ; -4.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.932 ; -4.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.276 ; -4.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.034 ; -4.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.305 ; -4.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -5.183 ; -5.183 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -5.105 ; -5.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.782 ; -4.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.567 ; -4.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.764 ; -4.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.122 ; -4.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.362 ; -4.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.229 ; -4.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.241 ; -4.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.126 ; -4.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.239 ; -4.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.899 ; -3.899 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -1.279 ; -1.279 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -1.473 ; -1.473 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -1.479 ; -1.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.457 ; -5.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -4.245 ; -4.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.940 ; -3.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -7.918 ; -7.918 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.367 ; -4.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.055 ; -8.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.848 ; -4.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.686 ; -7.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.663 ; -6.663 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.734 ; -6.734 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.646 ; -7.646 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.437 ; -6.437 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.003 ; -7.003 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.595 ; -6.595 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.269 ; -7.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.938 ; -7.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.230 ; -8.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.599 ; -7.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.388 ; -7.388 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.748 ; -7.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.068 ; -8.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.529 ; -7.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.935 ; -7.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.329 ; -7.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.722 ; -7.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.583 ; -7.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.589 ; -7.589 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.563 ; -7.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.698 ; -7.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.092 ; -4.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.942 ; -5.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.983 ; -3.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -3.892 ; -3.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.699 ; -5.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.678 ; -3.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.457 ; -3.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.702 ; -3.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.627 ; -3.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.511 ; -3.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.576 ; -3.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.505 ; -3.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.726 ; -3.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -3.685 ; -3.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -3.695 ; -3.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.241 ; -4.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.156 ; -5.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.494 ; -7.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.023 ; -5.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.449 ; -2.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.176 ; -2.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.573 ; -4.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.624 ; -4.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.404 ; -4.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.837 ; -4.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.733 ; -4.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.304 ; -4.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.146 ; -4.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.276 ; -4.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.186 ; -4.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.040 ; -4.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.134 ; -4.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.018 ; -4.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.736 ; -3.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.998 ; -4.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.894 ; -4.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.205 ; -4.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.346 ; -1.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.466 ; -4.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -3.729 ; -3.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.021 ; -5.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -4.189 ; -4.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.158 ; -5.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.984 ; -3.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -4.255 ; -4.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.344 ; -6.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.566 ; -6.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.336 ; -7.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.065 ; -6.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.776 ; -6.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.576 ; -6.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.334 ; -3.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.441 ; -1.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.796 ; -1.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -1.671 ; -1.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.686 ; -1.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.224 ; -4.224 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.318 ; -4.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -5.017 ; -5.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.145 ; -4.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.246 ; -4.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.148 ; -4.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.310 ; -4.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.961 ; -3.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.755 ; -1.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.355 ; -4.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.202 ; -4.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.403 ; -3.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.400 ; -3.400 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.542 ; -3.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.530 ; -3.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.622 ; -3.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.552 ; -3.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.779 ; -3.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.561 ; -3.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -3.739 ; -3.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.890 ; -3.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.240 ; -4.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -3.640 ; -3.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.289 ; -4.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -3.936 ; -3.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.913 ; -4.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.922 ; -3.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.123 ; -4.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -5.154 ; -5.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -3.810 ; -3.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -4.780 ; -4.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -4.011 ; -4.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.529 ; -5.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.603 ; -3.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.316 ; -4.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.607 ; -3.607 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.823 ; -6.823 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.790 ; -6.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.326 ; -7.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.608 ; -7.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.600 ; -7.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.866 ; -7.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.620 ; -4.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.932 ; -4.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.276 ; -4.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.034 ; -4.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.305 ; -4.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -5.183 ; -5.183 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -5.105 ; -5.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.567 ; -4.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.764 ; -4.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.122 ; -4.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.362 ; -4.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.229 ; -4.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.241 ; -4.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.126 ; -4.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.239 ; -4.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.899 ; -3.899 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -1.279 ; -1.279 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -1.473 ; -1.473 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -1.479 ; -1.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.457 ; -5.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -4.245 ; -4.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.940 ; -3.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.918 ; -7.918 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.367 ; -4.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.055 ; -8.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.848 ; -4.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.686 ; -7.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.663 ; -6.663 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.734 ; -6.734 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.646 ; -7.646 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.437 ; -6.437 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.003 ; -7.003 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.595 ; -6.595 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.269 ; -7.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.938 ; -7.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.230 ; -8.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.599 ; -7.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.388 ; -7.388 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.748 ; -7.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.068 ; -8.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.529 ; -7.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.935 ; -7.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.329 ; -7.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.722 ; -7.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.583 ; -7.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.589 ; -7.589 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.563 ; -7.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.698 ; -7.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.092 ; -4.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.942 ; -5.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.983 ; -3.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.699 ; -5.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.017 ; -4.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -6.571 ; -6.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -6.854 ; -6.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.698 ; -6.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.881 ; -4.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.948 ; -2.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.668 ; -2.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.559 ; -4.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.229 ; -4.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.249 ; -4.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.657 ; -4.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.303 ; -4.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.154 ; -4.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -4.256 ; -4.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.102 ; -5.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.002 ; -5.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.116 ; -7.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.253 ; -7.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.416 ; -4.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.313 ; -7.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.830 ; -5.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.243 ; -6.243 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.411 ; -6.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.156 ; -7.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.626 ; -6.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.039 ; -4.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.980 ; -3.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.057 ; -4.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.185 ; -4.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.275 ; -4.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.044 ; -4.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.973 ; -3.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.083 ; -4.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.866 ; -3.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.960 ; -3.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.037 ; -4.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.799 ; -3.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.786 ; -3.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -3.483 ; -3.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.530 ; -5.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.283 ; -5.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.037 ; -5.037 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.940 ; -5.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -6.026 ; -6.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.901 ; -4.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.489 ; -5.489 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.017 ; -4.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.571 ; -6.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.854 ; -6.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.698 ; -6.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.881 ; -4.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.948 ; -2.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.668 ; -2.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.559 ; -4.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.229 ; -4.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.249 ; -4.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.657 ; -4.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.303 ; -4.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.154 ; -4.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.256 ; -4.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.102 ; -5.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.002 ; -5.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.116 ; -7.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.253 ; -7.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.416 ; -4.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.313 ; -7.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.830 ; -5.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.243 ; -6.243 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.411 ; -6.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.156 ; -7.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.626 ; -6.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.039 ; -4.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.980 ; -3.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.057 ; -4.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.185 ; -4.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.275 ; -4.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.044 ; -4.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.973 ; -3.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.083 ; -4.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.866 ; -3.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.960 ; -3.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.037 ; -4.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.799 ; -3.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.786 ; -3.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.483 ; -3.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.530 ; -5.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.283 ; -5.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.037 ; -5.037 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.940 ; -5.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.026 ; -6.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.901 ; -4.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.489 ; -5.489 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -6.604 ; -6.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -6.406 ; -6.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.887 ; -6.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.490 ; -7.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.482 ; -7.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.657 ; -7.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.502 ; -4.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -5.007 ; -5.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.973 ; -4.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -4.856 ; -4.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -4.358 ; -4.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -4.409 ; -4.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.930 ; -4.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.343 ; -4.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.422 ; -4.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.197 ; -4.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -3.738 ; -3.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -3.593 ; -3.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -3.585 ; -3.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -3.745 ; -3.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -5.555 ; -5.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -7.451 ; -7.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.588 ; -7.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.242 ; -5.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.828 ; -5.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.936 ; -5.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.444 ; -6.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -4.035 ; -4.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.302 ; -6.302 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.344 ; -7.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -8.331 ; -8.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.585 ; -8.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.464 ; -7.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.614 ; -6.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.573 ; -7.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.629 ; -7.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -8.049 ; -8.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.368 ; -7.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.945 ; -6.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.254 ; -7.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.048 ; -7.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.069 ; -7.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -5.648 ; -5.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.333 ; -5.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.604 ; -6.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.406 ; -6.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.887 ; -6.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.490 ; -7.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.482 ; -7.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.657 ; -7.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.502 ; -4.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -5.007 ; -5.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.973 ; -4.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.856 ; -4.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.358 ; -4.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.409 ; -4.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.930 ; -4.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.343 ; -4.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.422 ; -4.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.197 ; -4.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -3.738 ; -3.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -3.593 ; -3.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -3.585 ; -3.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -3.745 ; -3.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.555 ; -5.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.451 ; -7.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.588 ; -7.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.242 ; -5.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.828 ; -5.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.936 ; -5.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.444 ; -6.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -4.035 ; -4.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.302 ; -6.302 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.344 ; -7.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -8.331 ; -8.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.585 ; -8.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.464 ; -7.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.614 ; -6.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.573 ; -7.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.629 ; -7.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -8.049 ; -8.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.368 ; -7.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.945 ; -6.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.254 ; -7.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.048 ; -7.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.069 ; -7.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.648 ; -5.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.333 ; -5.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.950  ; 7.950  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.579  ; 8.579  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.757  ; 7.757  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 12.044 ; 12.044 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 11.202 ; 11.202 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 11.259 ; 11.259 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 9.421  ; 9.421  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 11.402 ; 11.402 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 12.042 ; 12.042 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 12.016 ; 12.016 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 12.044 ; 12.044 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 9.224  ; 9.224  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 11.037 ; 11.037 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 9.895  ; 9.895  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 9.984  ; 9.984  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 9.418  ; 9.418  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 9.762  ; 9.762  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 9.676  ; 9.676  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 9.638  ; 9.638  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 9.502  ; 9.502  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 9.716  ; 9.716  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 10.630 ; 10.630 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 10.359 ; 10.359 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 10.539 ; 10.539 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 10.339 ; 10.339 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 10.061 ; 10.061 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 10.010 ; 10.010 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 11.037 ; 11.037 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 10.644 ; 10.644 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 3.721  ; 3.721  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.675 ; 11.675 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.843 ; 10.843 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.697 ; 10.697 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 10.547 ; 10.547 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.694 ; 10.694 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 10.911 ; 10.911 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.578 ; 10.578 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.078 ; 11.078 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 11.452 ; 11.452 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.675 ; 11.675 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 11.243 ; 11.243 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 10.818 ; 10.818 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.839 ; 10.839 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.722 ; 10.722 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.464 ; 10.464 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.125 ; 11.125 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.895 ; 10.895 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.177  ; 6.177  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.434  ; 3.434  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.514  ; 3.514  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 9.398  ; 9.398  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.374  ; 8.374  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 9.398  ; 9.398  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 10.110 ; 10.110 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.110 ; 10.110 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 9.649  ; 9.649  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.943  ; 8.943  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 7.759  ; 7.759  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 8.471  ; 8.471  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 7.731  ; 7.731  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 7.896  ; 7.896  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 7.430  ; 7.430  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.877  ; 7.877  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 7.334  ; 7.334  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 7.626  ; 7.626  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 8.333  ; 8.333  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 8.356  ; 8.356  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 8.397  ; 8.397  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 8.304  ; 8.304  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 8.788  ; 8.788  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 8.731  ; 8.731  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 8.943  ; 8.943  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 8.730  ; 8.730  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.449  ; 9.449  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 8.707  ; 8.707  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 9.184  ; 9.184  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 8.860  ; 8.860  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 8.828  ; 8.828  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 8.665  ; 8.665  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 8.817  ; 8.817  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 8.910  ; 8.910  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 9.362  ; 9.362  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 9.378  ; 9.378  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 9.240  ; 9.240  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 8.676  ; 8.676  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 8.804  ; 8.804  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 9.449  ; 9.449  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 9.185  ; 9.185  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 9.031  ; 9.031  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 8.981  ; 8.981  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.681  ; 5.681  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.363  ; 5.363  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.465  ; 8.465  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.681  ; 5.681  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.363  ; 5.363  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.465  ; 8.465  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 14.029 ; 14.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 14.658 ; 14.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 8.891  ; 8.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 7.783  ; 7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 7.725  ; 7.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 8.699  ; 8.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 8.005  ; 8.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 7.928  ; 7.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 7.564  ; 7.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 7.609  ; 7.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 7.886  ; 7.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 7.536  ; 7.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 8.060  ; 8.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 8.423  ; 8.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 8.416  ; 8.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 8.403  ; 8.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 8.342  ; 8.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 8.718  ; 8.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 8.798  ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 8.891  ; 8.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 8.758  ; 8.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 4.699  ; 4.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.025  ; 3.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.899 ; 11.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 13.836 ; 13.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 18.123 ; 18.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 17.281 ; 17.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 17.338 ; 17.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 15.500 ; 15.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 17.481 ; 17.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 18.121 ; 18.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 18.095 ; 18.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 18.123 ; 18.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 15.303 ; 15.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.682  ; 3.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 16.262 ; 16.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.221 ; 15.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 15.036 ; 15.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.106 ; 15.106 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.095 ; 15.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 14.961 ; 14.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 14.780 ; 14.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.587 ; 15.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 15.598 ; 15.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 16.047 ; 16.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 15.649 ; 15.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 15.435 ; 15.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.633 ; 15.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 16.262 ; 16.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 15.840 ; 15.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 4.502  ; 4.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 8.872  ; 8.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 8.668  ; 8.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 8.620  ; 8.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 8.872  ; 8.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 8.371  ; 8.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 11.043 ; 11.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 11.252 ; 11.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.872  ; 2.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 5.893  ; 5.893  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 2.891  ; 2.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 11.370 ; 11.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 11.317 ; 11.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 11.148 ; 11.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 11.073 ; 11.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 11.561 ; 11.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 12.204 ; 12.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 11.778 ; 11.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.860 ; 11.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 12.245 ; 12.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 4.593  ; 4.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 4.078  ; 4.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.803  ; 3.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.548  ; 3.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 4.078  ; 4.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 3.877  ; 3.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 3.391  ; 3.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 12.671 ; 12.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 9.572  ; 9.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 9.969  ; 9.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 10.996 ; 10.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 10.944 ; 10.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 10.063 ; 10.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 10.552 ; 10.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.671 ; 12.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 9.505  ; 9.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 10.666 ; 10.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 10.100 ; 10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 10.038 ; 10.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 11.343 ; 11.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 12.809 ; 12.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 12.223 ; 12.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 16.632 ; 16.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.934 ; 15.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 16.165 ; 16.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 16.038 ; 16.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 15.922 ; 15.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.035 ; 16.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 16.537 ; 16.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.516 ; 16.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 16.632 ; 16.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 16.482 ; 16.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.326 ; 16.326 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 16.149 ; 16.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 16.096 ; 16.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.087 ; 16.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 16.350 ; 16.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.091 ; 16.091 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.395 ; 12.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 12.488 ; 12.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 12.458 ; 12.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 12.287 ; 12.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.764 ; 12.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.731 ; 12.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 5.665  ; 5.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 10.460 ; 10.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 10.762 ; 10.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 10.475 ; 10.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 10.370 ; 10.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 10.682 ; 10.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 10.185 ; 10.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 4.364  ; 4.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.989  ; 2.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 3.193  ; 3.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.932  ; 2.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.979  ; 2.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 3.339  ; 3.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 3.111  ; 3.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 3.220  ; 3.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 3.548  ; 3.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.637  ; 3.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 3.995  ; 3.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.388  ; 4.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 4.171  ; 4.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.314  ; 3.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.420  ; 3.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 7.690  ; 7.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 5.941  ; 5.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 6.358  ; 6.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 6.331  ; 6.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 8.761  ; 8.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 9.390  ; 9.390  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.864  ; 3.864  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 6.631  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 8.568  ; 8.345  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 12.013 ; 12.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 12.070 ; 12.070 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 10.232 ; 10.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 12.213 ; 12.213 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 12.853 ; 12.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 12.827 ; 12.827 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 10.035 ; 10.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 11.077 ; 11.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 9.710  ; 9.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 10.036 ; 10.036 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 9.768  ; 9.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 9.849  ; 9.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 9.502  ; 9.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 9.910  ; 9.910  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 9.693  ; 9.693  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 9.534  ; 9.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 10.319 ; 10.319 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 10.413 ; 10.294 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 10.779 ; 10.779 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 10.455 ; 10.435 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 10.167 ; 10.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 10.365 ; 10.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.077 ; 11.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 10.655 ; 10.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.517  ; 5.818  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 5.726  ; 6.027  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 6.102  ; 6.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 5.798  ; 5.787  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 6.049  ; 6.037  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.880  ; 5.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 5.805  ; 5.793  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 6.293  ; 6.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 6.936  ; 6.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 6.510  ; 6.287  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 6.369  ; 6.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 6.754  ; 6.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 4.592  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 7.082  ; 5.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.815  ; 4.815  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.265  ; 5.265  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.243  ; 5.243  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 5.865  ; 5.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.945  ; 5.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.005  ; 5.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.142  ; 5.142  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 7.082  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.278  ; 5.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 6.278  ; 5.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 5.754  ; 4.561  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 7.220  ; 6.027  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.441  ; 6.634  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 11.364 ; 11.364 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.877 ; 10.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.749 ; 10.749 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 10.897 ; 10.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 10.781 ; 10.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 10.737 ; 10.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 10.850 ; 10.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.269 ; 11.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 11.270 ; 11.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.364 ; 11.364 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 11.297 ; 11.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 11.058 ; 11.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.955 ; 10.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 10.828 ; 10.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.819 ; 10.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.165 ; 11.165 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.906 ; 10.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 6.806  ; 5.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 6.899  ; 5.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.676  ; 6.869  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.505  ; 6.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 7.175  ; 5.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.949  ; 7.142  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 5.234  ; 3.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.856  ; 5.332  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 5.236  ; 5.537  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.950  ; 5.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.849  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 5.218  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.663  ; 4.879  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 4.742  ; 4.742  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 14.029 ; 14.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 14.658 ; 14.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 8.891  ; 8.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 7.783  ; 7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 7.725  ; 7.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 8.699  ; 8.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 8.005  ; 8.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 7.928  ; 7.928  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 7.564  ; 7.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 7.609  ; 7.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 7.886  ; 7.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 7.536  ; 7.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 8.060  ; 8.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 8.265  ; 8.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 8.423  ; 8.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 8.416  ; 8.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 8.403  ; 8.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 8.342  ; 8.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 8.718  ; 8.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 8.240  ; 8.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 8.798  ; 8.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 8.891  ; 8.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 8.758  ; 8.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.699  ; 4.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.025  ; 3.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.899 ; 11.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 13.836 ; 13.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 18.123 ; 18.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.281 ; 17.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.338 ; 17.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 15.500 ; 15.500 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 17.481 ; 17.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 18.121 ; 18.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 18.095 ; 18.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 18.123 ; 18.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 15.303 ; 15.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.682  ; 3.682  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.262 ; 16.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.221 ; 15.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.036 ; 15.036 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.106 ; 15.106 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.095 ; 15.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.961 ; 14.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.780 ; 14.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.587 ; 15.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.598 ; 15.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 16.047 ; 16.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.649 ; 15.649 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 15.435 ; 15.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.633 ; 15.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 16.262 ; 16.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.840 ; 15.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 4.502  ; 4.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 8.872  ; 8.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 8.668  ; 8.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 8.620  ; 8.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 8.872  ; 8.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 8.614  ; 8.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 8.371  ; 8.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 11.043 ; 11.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 11.252 ; 11.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.872  ; 2.872  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 5.893  ; 5.893  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 2.891  ; 2.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 11.370 ; 11.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 11.317 ; 11.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 11.148 ; 11.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 11.073 ; 11.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 11.561 ; 11.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 12.204 ; 12.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 11.778 ; 11.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.860 ; 11.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 12.245 ; 12.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 4.593  ; 4.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 4.078  ; 4.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.803  ; 3.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.548  ; 3.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 4.078  ; 4.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.767  ; 3.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 4.115  ; 4.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 3.877  ; 3.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 3.391  ; 3.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 12.671 ; 12.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 9.572  ; 9.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 9.969  ; 9.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 10.322 ; 10.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 10.333 ; 10.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 10.996 ; 10.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 10.944 ; 10.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 10.063 ; 10.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 10.552 ; 10.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.671 ; 12.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 9.505  ; 9.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 10.666 ; 10.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 10.100 ; 10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 10.038 ; 10.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 11.343 ; 11.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 12.809 ; 12.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 12.223 ; 12.223 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 16.632 ; 16.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.018 ; 16.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.934 ; 15.934 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 16.165 ; 16.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 16.038 ; 16.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 15.922 ; 15.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.035 ; 16.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 16.537 ; 16.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.516 ; 16.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 16.632 ; 16.632 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 16.482 ; 16.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.326 ; 16.326 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 16.149 ; 16.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 16.096 ; 16.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.087 ; 16.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 16.350 ; 16.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.091 ; 16.091 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.395 ; 12.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 12.488 ; 12.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 12.458 ; 12.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 12.287 ; 12.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.764 ; 12.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.731 ; 12.731 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 5.665  ; 5.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 10.460 ; 10.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 10.762 ; 10.762 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 10.475 ; 10.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 10.370 ; 10.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 10.682 ; 10.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.185 ; 10.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.940  ; 3.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 4.364  ; 4.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.989  ; 2.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 3.193  ; 3.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.932  ; 2.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.979  ; 2.979  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 3.339  ; 3.339  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 3.111  ; 3.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 3.220  ; 3.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 3.548  ; 3.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.448  ; 4.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.776  ; 3.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.637  ; 3.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 3.995  ; 3.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.388  ; 4.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 4.171  ; 4.171  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.314  ; 3.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.461  ; 3.461  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.497  ; 3.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.420  ; 3.420  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 7.690  ; 7.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 5.941  ; 5.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 6.358  ; 6.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 6.331  ; 6.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 8.761  ; 8.761  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 9.390  ; 9.390  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.864  ; 3.864  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 6.631  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 8.568  ; 8.345  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 12.013 ; 12.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 12.070 ; 12.070 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 10.232 ; 10.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 12.213 ; 12.213 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 12.853 ; 12.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 12.827 ; 12.827 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 12.855 ; 12.855 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 10.035 ; 10.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 11.077 ; 11.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 9.710  ; 9.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 10.036 ; 10.036 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 9.768  ; 9.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 9.849  ; 9.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 9.502  ; 9.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 9.910  ; 9.910  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 9.693  ; 9.693  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 9.534  ; 9.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 10.319 ; 10.319 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 10.413 ; 10.294 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 10.779 ; 10.779 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 10.455 ; 10.435 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 10.167 ; 10.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 10.365 ; 10.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.077 ; 11.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 10.655 ; 10.655 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.517  ; 5.818  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 5.726  ; 6.027  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 6.102  ; 6.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 5.798  ; 5.787  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 6.049  ; 6.037  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.880  ; 5.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 5.805  ; 5.793  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 6.293  ; 6.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 6.936  ; 6.713  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 6.510  ; 6.287  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 6.369  ; 6.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 6.754  ; 6.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.592  ; 4.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 7.082  ; 5.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.815  ; 4.815  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.265  ; 5.265  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.243  ; 5.243  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 5.865  ; 5.865  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.945  ; 5.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.005  ; 5.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.142  ; 5.142  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 7.082  ; 5.889  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.278  ; 5.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 6.278  ; 5.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 5.754  ; 4.561  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 7.220  ; 6.027  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.441  ; 6.634  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 11.364 ; 11.364 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 10.877 ; 10.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 10.749 ; 10.749 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 10.897 ; 10.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 10.781 ; 10.853 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 10.737 ; 10.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 10.850 ; 10.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 11.269 ; 11.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 11.270 ; 11.331 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 11.364 ; 11.364 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 11.297 ; 11.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 11.058 ; 11.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 10.955 ; 10.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 10.828 ; 10.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 10.819 ; 10.816 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.165 ; 11.165 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.906 ; 10.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 6.806  ; 5.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 6.899  ; 5.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.676  ; 6.869  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.505  ; 6.698  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 7.175  ; 5.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.949  ; 7.142  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 5.234  ; 3.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.856  ; 5.332  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 5.236  ; 5.537  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.950  ; 5.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.849  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 5.218  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.663  ; 4.879  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.742  ; 4.742  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 6.153  ; 6.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.782  ; 6.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.403  ; 3.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 10.247 ; 10.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 9.405  ; 9.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 9.462  ; 9.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 7.624  ; 7.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 10.245 ; 10.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 10.219 ; 10.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 10.247 ; 10.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 7.427  ; 7.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 3.710  ; 3.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.710  ; 3.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 3.470  ; 3.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.302  ; 3.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.252  ; 3.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 3.470  ; 3.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 6.545  ; 6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 4.060  ; 4.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 4.060  ; 4.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 3.717  ; 3.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 8.098  ; 8.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 8.187  ; 8.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 7.621  ; 7.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 7.965  ; 7.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 7.879  ; 7.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 7.841  ; 7.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 8.833  ; 8.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 8.742  ; 8.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 8.542  ; 8.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 8.264  ; 8.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 8.213  ; 8.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.770  ; 3.770  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.754  ; 3.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 6.430  ; 6.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.886  ; 4.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.596  ; 5.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.687  ; 5.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.454  ; 5.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 5.589  ; 5.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.430  ; 6.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.659  ; 5.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.608  ; 5.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.097  ; 6.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.341  ; 5.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.511  ; 5.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.452  ; 5.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 10.127 ; 10.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.127 ; 10.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 9.774  ; 9.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 9.233  ; 9.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 9.669  ; 9.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.823  ; 9.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.655  ; 9.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.878  ; 9.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 9.272  ; 9.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 9.422  ; 9.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.202  ; 9.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.328  ; 9.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.173  ; 9.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.626  ; 5.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.719  ; 5.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.687  ; 5.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.393  ; 5.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.369  ; 5.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.899  ; 3.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.680  ; 4.680  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.126  ; 4.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.181  ; 4.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.003  ; 4.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 6.153  ; 6.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.782  ; 6.782  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.403  ; 3.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.247 ; 10.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.405  ; 9.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.462  ; 9.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.624  ; 7.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 9.605  ; 9.605  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 10.245 ; 10.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 10.219 ; 10.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.247 ; 10.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.427  ; 7.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 3.710  ; 3.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.710  ; 3.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 3.470  ; 3.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.302  ; 3.302  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.252  ; 3.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 3.470  ; 3.470  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 6.545  ; 6.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 4.060  ; 4.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 4.060  ; 4.060  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.477  ; 3.477  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 3.717  ; 3.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 8.098  ; 8.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 8.187  ; 8.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.621  ; 7.621  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.965  ; 7.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 7.879  ; 7.879  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.841  ; 7.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 7.705  ; 7.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 8.833  ; 8.833  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 8.742  ; 8.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 8.542  ; 8.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 8.264  ; 8.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 8.213  ; 8.213  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.240  ; 9.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.847  ; 8.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.770  ; 3.770  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.855  ; 3.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.754  ; 3.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 6.430  ; 6.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.886  ; 4.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.596  ; 5.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.687  ; 5.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.454  ; 5.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 5.589  ; 5.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.430  ; 6.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.659  ; 5.659  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.608  ; 5.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.097  ; 6.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.341  ; 5.341  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.511  ; 5.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.541  ; 4.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 6.040  ; 6.040  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.452  ; 5.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.127 ; 10.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 10.127 ; 10.127 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 9.774  ; 9.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 9.233  ; 9.233  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 9.669  ; 9.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 9.884  ; 9.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.823  ; 9.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 9.655  ; 9.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.878  ; 9.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 9.610  ; 9.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 9.272  ; 9.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 9.422  ; 9.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 9.202  ; 9.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.328  ; 9.328  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.173  ; 9.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.626  ; 5.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.719  ; 5.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.687  ; 5.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.393  ; 5.393  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.369  ; 5.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.899  ; 3.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.680  ; 4.680  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.126  ; 4.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.181  ; 4.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.003  ; 4.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 11.834 ; 11.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 11.962 ; 11.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 11.379 ; 11.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 11.853 ; 11.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 11.733 ; 11.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 12.041 ; 12.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 11.511 ; 11.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 11.534 ; 11.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 12.133 ; 12.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 12.163 ; 12.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 12.477 ; 12.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 12.191 ; 12.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 12.268 ; 12.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 11.792 ; 11.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 11.316 ; 11.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 4.975  ; 4.975  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 4.687  ; 4.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 4.941  ; 4.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 13.290 ; 13.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.782 ; 12.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.675 ; 12.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.508 ; 12.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.968 ; 12.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.981 ; 12.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 13.087 ; 13.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 13.178 ; 13.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 13.047 ; 13.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 13.290 ; 13.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 12.977 ; 12.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.852 ; 12.852 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.722 ; 12.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 11.880 ; 11.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 11.567 ; 11.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 11.834 ; 11.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 11.962 ; 11.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 11.379 ; 11.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 11.853 ; 11.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 11.733 ; 11.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.041 ; 12.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 11.511 ; 11.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 11.534 ; 11.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 12.133 ; 12.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 12.163 ; 12.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.011 ; 13.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 12.477 ; 12.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 12.191 ; 12.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 12.268 ; 12.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.792 ; 11.792 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 11.316 ; 11.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 4.975  ; 4.975  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 4.687  ; 4.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 4.941  ; 4.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 13.290 ; 13.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.782 ; 12.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.675 ; 12.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.508 ; 12.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.785 ; 12.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.968 ; 12.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.981 ; 12.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 13.087 ; 13.087 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 13.270 ; 13.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 13.178 ; 13.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 13.047 ; 13.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 13.290 ; 13.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 12.977 ; 12.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.852 ; 12.852 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.722 ; 12.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 11.880 ; 11.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 11.567 ; 11.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.204  ; 7.204  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.833  ; 7.833  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.757  ; 7.757  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 7.413  ; 7.413  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 8.162  ; 8.162  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 7.565  ; 7.565  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 8.167  ; 8.167  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 7.725  ; 7.725  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 7.934  ; 7.934  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 7.893  ; 7.893  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 7.413  ; 7.413  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 7.447  ; 7.447  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 7.727  ; 7.727  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 8.047  ; 8.047  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 7.478  ; 7.478  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 7.980  ; 7.980  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 7.632  ; 7.632  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 7.736  ; 7.736  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 7.447  ; 7.447  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 7.658  ; 7.658  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 8.260  ; 8.260  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 8.550  ; 8.550  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 8.515  ; 8.515  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 8.013  ; 8.013  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 8.133  ; 8.133  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.669  ; 8.669  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 8.335  ; 8.335  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 3.721  ; 3.721  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.586  ; 8.586  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.675  ; 8.675  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.760  ; 8.760  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.607  ; 8.607  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.912  ; 8.912  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.867  ; 8.867  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.676  ; 8.676  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.023  ; 9.023  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.394  ; 9.394  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.345  ; 9.345  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.144  ; 9.144  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.829  ; 8.829  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 9.015  ; 9.015  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.674  ; 8.674  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.587  ; 8.587  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.757  ; 8.757  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.586  ; 8.586  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.177  ; 6.177  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.434  ; 3.434  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.514  ; 3.514  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.374  ; 8.374  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.374  ; 8.374  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 9.398  ; 9.398  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.649  ; 9.649  ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.110 ; 10.110 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 9.649  ; 9.649  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.384  ; 6.384  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 6.486  ; 6.486  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 6.970  ; 6.970  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 6.593  ; 6.593  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 6.742  ; 6.742  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 6.641  ; 6.641  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.001  ; 7.001  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 6.384  ; 6.384  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 6.733  ; 6.733  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.375  ; 7.375  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 6.858  ; 6.858  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 7.591  ; 7.591  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 7.466  ; 7.466  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 6.947  ; 6.947  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.298  ; 7.298  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.927  ; 7.927  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.166  ; 7.166  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 7.417  ; 7.417  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 7.434  ; 7.434  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 7.683  ; 7.683  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.722  ; 7.722  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 7.674  ; 7.674  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 7.876  ; 7.876  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 7.941  ; 7.941  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 7.960  ; 7.960  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.469  ; 8.469  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 8.420  ; 8.420  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 7.742  ; 7.742  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.870  ; 7.870  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.966  ; 7.966  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.608  ; 7.608  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 7.752  ; 7.752  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.015  ; 8.015  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 7.417  ; 7.417  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.549  ; 5.549  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.358  ; 5.358  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.549  ; 5.549  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.358  ; 5.358  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 4.016  ; 4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 4.645  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.768  ; 3.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.700  ; 3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.624  ; 3.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 2.817  ; 2.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.003  ; 3.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.112  ; 3.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 3.352  ; 3.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.226  ; 4.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 2.950  ; 2.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.572  ; 4.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 4.348  ; 4.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.057  ; 3.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.398  ; 3.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 3.595  ; 3.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 2.836  ; 2.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.873  ; 3.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.239  ; 3.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.172  ; 3.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.124  ; 3.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 2.848  ; 2.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 2.845  ; 2.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 2.690  ; 2.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.604  ; 2.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.570  ; 2.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.679  ; 2.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 2.834  ; 2.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.792  ; 2.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 3.988  ; 3.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.306  ; 3.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.532  ; 3.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 2.984  ; 2.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 2.661  ; 2.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 2.868  ; 2.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.561  ; 2.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.186  ; 3.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.668  ; 4.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.136  ; 4.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 5.171  ; 5.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.002  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.927  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.415  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.945  ; 5.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.452  ; 4.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.802  ; 4.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.939  ; 3.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 4.244  ; 4.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.381  ; 3.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.474  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.231  ; 3.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.023  ; 3.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.240  ; 3.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.501  ; 3.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.667  ; 2.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 3.129  ; 3.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.013  ; 5.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.095  ; 5.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.835  ; 4.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.874  ; 5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.976  ; 4.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.837  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.915  ; 5.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.413  ; 5.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.319  ; 5.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.156  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.156  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.221  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.091  ; 5.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.076  ; 5.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.188  ; 5.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.115  ; 5.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.029  ; 5.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.201  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.202  ; 5.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.103  ; 5.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.163  ; 5.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.593  ; 4.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.498  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.948  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.777  ; 4.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.343  ; 4.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.234  ; 5.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.326  ; 5.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.631  ; 5.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.598  ; 5.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.730  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.536  ; 3.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.503  ; 4.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 3.792  ; 4.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.322  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.597  ; 3.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.982  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.039  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.708  ; 2.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.577  ; 2.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.429  ; 2.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.397  ; 2.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.324  ; 2.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.543  ; 2.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.643  ; 2.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.449  ; 2.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.715  ; 2.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.043  ; 3.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.844  ; 2.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.489  ; 3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.315  ; 3.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.301  ; 3.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.340  ; 3.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.378  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.330  ; 3.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 3.329  ; 3.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 3.161  ; 3.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.445  ; 5.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.074  ; 6.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.085  ; 3.244  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 5.632  ; 4.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.998  ; 6.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.403  ; 6.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.510  ; 6.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.848  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.408  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 5.966  ; 5.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.175  ; 6.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 4.812  ; 4.635  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 5.347  ; 4.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 4.809  ; 4.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 5.079  ; 5.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 5.349  ; 4.679  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 5.194  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 4.604  ; 4.740  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 5.784  ; 5.477  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 5.819  ; 5.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.295  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 5.229  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 5.476  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 5.143  ; 5.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.252  ; 5.252  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.051  ; 5.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 4.677  ; 4.073  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 4.886  ; 4.282  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.440  ; 4.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.169  ; 4.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 5.003  ; 5.171  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.834  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.759  ; 4.927  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.247  ; 5.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 5.049  ; 4.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.720  ; 4.452  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.534  ; 4.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.931  ; 3.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.148  ; 3.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.013  ; 5.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.095  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.868  ; 4.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.874  ; 5.874  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.976  ; 4.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.071  ; 5.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.054  ; 4.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.726  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 5.250  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.726  ; 4.416  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 6.192  ; 5.691  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.134  ; 5.606  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.076  ; 5.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.188  ; 5.188  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.115  ; 5.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.118  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.226  ; 5.226  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.035  ; 5.035  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.202  ; 5.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.250  ; 5.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.310  ; 5.163  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.740  ; 4.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.222  ; 4.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.995  ; 4.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.977  ; 4.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.114  ; 4.876  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.778  ; 5.277  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.871  ; 5.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.369  ; 5.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.198  ; 5.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 6.147  ; 5.674  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.641  ; 6.114  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.422  ; 3.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.236  ; 4.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.396  ; 3.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.742  ; 4.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.640  ; 3.597  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.378  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.454  ; 4.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.296  ; 3.725  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.016  ; 4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 4.645  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.768  ; 3.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.700  ; 3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.624  ; 3.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 2.817  ; 2.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.003  ; 3.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.112  ; 3.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 3.352  ; 3.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.226  ; 4.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 2.950  ; 2.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.572  ; 4.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.348  ; 4.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.057  ; 3.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.398  ; 3.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 3.595  ; 3.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 2.836  ; 2.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.873  ; 3.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.239  ; 3.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.172  ; 3.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.124  ; 3.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 2.848  ; 2.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 2.845  ; 2.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 2.690  ; 2.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.604  ; 2.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.570  ; 2.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.679  ; 2.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 2.834  ; 2.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.792  ; 2.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 3.988  ; 3.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.306  ; 3.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.532  ; 3.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 2.984  ; 2.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 2.661  ; 2.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 2.868  ; 2.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.561  ; 2.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.186  ; 3.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.668  ; 4.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.136  ; 4.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 5.171  ; 5.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.002  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.927  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.415  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.945  ; 5.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.452  ; 4.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.802  ; 4.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.939  ; 3.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 4.244  ; 4.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.381  ; 3.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.474  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.231  ; 3.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.023  ; 3.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.240  ; 3.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.501  ; 3.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.667  ; 2.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 3.129  ; 3.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.013  ; 5.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.095  ; 5.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.835  ; 4.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.874  ; 5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.976  ; 4.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.837  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.915  ; 5.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.413  ; 5.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.319  ; 5.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.156  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.156  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.221  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.091  ; 5.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.076  ; 5.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.188  ; 5.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.115  ; 5.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.029  ; 5.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.201  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.202  ; 5.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.103  ; 5.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.163  ; 5.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.593  ; 4.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.498  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.948  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.777  ; 4.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.343  ; 4.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.234  ; 5.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.326  ; 5.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.631  ; 5.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.598  ; 5.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.730  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.536  ; 3.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.503  ; 4.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 3.792  ; 4.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.322  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.597  ; 3.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.982  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.039  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.708  ; 2.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.577  ; 2.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.429  ; 2.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.397  ; 2.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.324  ; 2.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.543  ; 2.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.643  ; 2.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.449  ; 2.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.715  ; 2.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.043  ; 3.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.844  ; 2.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.489  ; 3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.315  ; 3.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.301  ; 3.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.340  ; 3.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.378  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.330  ; 3.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 3.329  ; 3.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 3.161  ; 3.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.445  ; 5.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.074  ; 6.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.085  ; 3.244  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 5.632  ; 4.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.998  ; 6.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.403  ; 6.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.510  ; 6.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.848  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.408  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.966  ; 5.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.175  ; 6.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.812  ; 4.635  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.347  ; 4.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.809  ; 4.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.079  ; 5.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.349  ; 4.679  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.194  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.604  ; 4.740  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 5.784  ; 5.477  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.819  ; 5.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.295  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.229  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.476  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.143  ; 5.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.252  ; 5.252  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.051  ; 5.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 4.677  ; 4.073  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 4.886  ; 4.282  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.440  ; 4.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.169  ; 4.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 5.003  ; 5.171  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.834  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.759  ; 4.927  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.247  ; 5.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 5.049  ; 4.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.720  ; 4.452  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.534  ; 4.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.931  ; 3.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.148  ; 3.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.013  ; 5.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.095  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.868  ; 4.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.874  ; 5.874  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.976  ; 4.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.054  ; 4.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.726  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 5.250  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.726  ; 4.416  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 6.192  ; 5.691  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.134  ; 5.606  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.076  ; 5.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.188  ; 5.188  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.115  ; 5.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.118  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.226  ; 5.226  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.202  ; 5.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.250  ; 5.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.310  ; 5.163  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.740  ; 4.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.222  ; 4.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.995  ; 4.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.977  ; 4.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.114  ; 4.876  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.778  ; 5.277  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.871  ; 5.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.369  ; 5.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.198  ; 5.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 6.147  ; 5.674  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.641  ; 6.114  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.422  ; 3.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.236  ; 4.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.396  ; 3.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.742  ; 4.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.640  ; 3.597  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.378  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.454  ; 4.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.296  ; 3.725  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 4.761  ; 4.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.390  ; 5.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.289  ; 4.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.122  ; 5.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 5.282  ; 5.282  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.450  ; 5.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 4.970  ; 4.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 2.697  ; 2.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.298  ; 3.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.830  ; 2.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.632  ; 3.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.292  ; 3.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.777  ; 2.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.945  ; 2.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 4.484  ; 4.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 4.704  ; 4.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.931  ; 4.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 4.765  ; 4.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.032  ; 5.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 4.978  ; 4.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 5.542  ; 5.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 5.240  ; 5.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.316  ; 5.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 4.952  ; 4.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 6.226  ; 6.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.369  ; 3.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.384  ; 3.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 3.415  ; 3.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.635  ; 3.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 3.894  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.775  ; 3.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.675  ; 3.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 3.564  ; 3.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 3.557  ; 3.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.434  ; 3.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.483  ; 4.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.051  ; 4.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 3.576  ; 3.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 3.842  ; 3.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.644  ; 3.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.011  ; 4.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 4.057  ; 4.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.639  ; 3.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.542  ; 3.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.483  ; 3.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 3.634  ; 3.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.989  ; 3.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 3.967  ; 3.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.797  ; 3.797  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 4.309  ; 4.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.283  ; 4.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.740  ; 3.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 4.650  ; 4.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.892  ; 3.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.043  ; 4.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.611  ; 4.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.761  ; 4.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.390  ; 5.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.289  ; 4.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.122  ; 5.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.282  ; 5.282  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.970  ; 4.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 2.697  ; 2.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.298  ; 3.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.830  ; 2.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.632  ; 3.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.292  ; 3.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.777  ; 2.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.945  ; 2.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.484  ; 4.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 4.704  ; 4.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.931  ; 4.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.765  ; 4.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.032  ; 5.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 4.978  ; 4.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.542  ; 5.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.240  ; 5.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.316  ; 5.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 4.952  ; 4.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.226  ; 6.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.369  ; 3.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.384  ; 3.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 3.415  ; 3.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.635  ; 3.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 3.894  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.775  ; 3.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.675  ; 3.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 3.564  ; 3.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 3.557  ; 3.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.434  ; 3.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.483  ; 4.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.051  ; 4.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 3.576  ; 3.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 3.842  ; 3.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.644  ; 3.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.011  ; 4.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 4.057  ; 4.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.639  ; 3.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.542  ; 3.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.483  ; 3.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 3.634  ; 3.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.989  ; 3.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 3.967  ; 3.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.797  ; 3.797  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 4.309  ; 4.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.283  ; 4.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.740  ; 3.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.650  ; 4.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.892  ; 3.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.043  ; 4.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.611  ; 4.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.550  ; 6.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 6.516  ; 6.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.529  ; 6.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 8.007  ; 8.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 7.057  ; 7.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 8.231  ; 8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.560  ; 3.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.543  ; 7.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.679  ; 7.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.601  ; 7.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.431  ; 8.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.650  ; 8.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.550  ; 6.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.516  ; 6.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.529  ; 6.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 8.007  ; 8.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.057  ; 7.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.231  ; 8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.560  ; 3.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.543  ; 7.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.679  ; 7.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.601  ; 7.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.431  ; 8.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.650  ; 8.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 10.086 ; 10.086 ; 10.086 ; 10.086 ;
; ASn          ; ACSI_WRn      ; 10.715 ; 10.715 ; 10.715 ; 10.715 ;
; ASn          ; BUTTONn       ; 7.765  ;        ;        ; 7.765  ;
; ASn          ; CA1_OUT       ; 9.893  ;        ;        ; 9.893  ;
; ASn          ; CD[0]         ; 13.338 ; 13.338 ; 13.338 ; 13.338 ;
; ASn          ; CD[1]         ; 13.395 ; 13.395 ; 13.395 ; 13.395 ;
; ASn          ; CD[2]         ; 11.557 ; 11.557 ; 11.557 ; 11.557 ;
; ASn          ; CD[3]         ; 13.538 ; 13.538 ; 13.538 ; 13.538 ;
; ASn          ; CD[4]         ; 14.178 ; 14.178 ; 14.178 ; 14.178 ;
; ASn          ; CD[5]         ; 14.152 ; 14.152 ; 14.152 ; 14.152 ;
; ASn          ; CD[6]         ; 14.180 ; 14.180 ; 14.180 ; 14.180 ;
; ASn          ; CD[7]         ; 11.360 ; 11.360 ; 11.360 ; 11.360 ;
; ASn          ; DATA[0]       ; 13.052 ; 13.108 ; 13.108 ; 13.052 ;
; ASn          ; DATA[1]       ; 13.391 ; 13.391 ; 13.391 ; 13.391 ;
; ASn          ; DATA[2]       ; 13.014 ; 13.009 ; 13.009 ; 13.014 ;
; ASn          ; DATA[3]       ; 13.204 ; 13.276 ; 13.276 ; 13.204 ;
; ASn          ; DATA[4]       ; 12.857 ; 12.857 ; 12.857 ; 12.857 ;
; ASn          ; DATA[5]       ; 13.265 ; 13.265 ; 13.265 ; 13.265 ;
; ASn          ; DATA[6]       ; 12.820 ; 12.820 ; 12.820 ; 12.820 ;
; ASn          ; DATA[7]       ; 12.889 ; 12.950 ; 12.950 ; 12.889 ;
; ASn          ; DATA[8]       ; 13.648 ; 13.648 ; 13.648 ; 13.648 ;
; ASn          ; DATA[9]       ; 13.768 ; 13.649 ; 13.649 ; 13.768 ;
; ASn          ; DATA[10]      ; 13.928 ; 13.848 ; 13.848 ; 13.928 ;
; ASn          ; DATA[11]      ; 13.810 ; 13.790 ; 13.790 ; 13.810 ;
; ASn          ; DATA[12]      ; 13.359 ; 13.446 ; 13.446 ; 13.359 ;
; ASn          ; DATA[13]      ; 13.544 ; 13.627 ; 13.627 ; 13.544 ;
; ASn          ; DATA[14]      ; 14.432 ; 14.432 ; 14.432 ; 14.432 ;
; ASn          ; DATA[15]      ; 14.010 ; 14.010 ; 14.010 ; 14.010 ;
; ASn          ; DTACKn        ; 11.582 ; 11.582 ; 11.582 ; 11.582 ;
; ASn          ; FLASH_CEn     ; 7.260  ;        ;        ; 7.260  ;
; ASn          ; FLASH_OEn     ; 7.469  ;        ;        ; 7.469  ;
; ASn          ; IDE_CS0n      ; 6.658  ;        ;        ; 6.658  ;
; ASn          ; IDE_CS1n      ; 6.283  ;        ;        ; 6.283  ;
; ASn          ; IDE_D_EN_INn  ; 7.626  ;        ;        ; 7.626  ;
; ASn          ; IDE_D_EN_OUTn ; 7.457  ;        ;        ; 7.457  ;
; ASn          ; IDE_IORDn     ; 7.382  ;        ;        ; 7.382  ;
; ASn          ; IDE_IOWRn     ; 7.870  ;        ;        ; 7.870  ;
; ASn          ; JOY_RHn       ; 7.921  ;        ;        ; 7.921  ;
; ASn          ; JOY_RLn       ; 7.592  ;        ;        ; 7.592  ;
; ASn          ; JOY_WEn       ;        ; 7.674  ; 7.674  ;        ;
; ASn          ; JOY_WL        ;        ; 6.811  ; 6.811  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.413  ; 8.413  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.609  ; 7.609  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.085  ; 7.085  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 8.551  ; 8.551  ;        ;
; ASn          ; RAM_CAS1n     ; 7.965  ;        ;        ; 7.965  ;
; ASn          ; RAM_DATA[0]   ; 14.000 ; 14.056 ; 14.056 ; 14.000 ;
; ASn          ; RAM_DATA[1]   ; 14.104 ; 14.104 ; 14.104 ; 14.104 ;
; ASn          ; RAM_DATA[2]   ; 14.143 ; 14.138 ; 14.138 ; 14.143 ;
; ASn          ; RAM_DATA[3]   ; 14.136 ; 14.208 ; 14.208 ; 14.136 ;
; ASn          ; RAM_DATA[4]   ; 14.092 ; 14.092 ; 14.092 ; 14.092 ;
; ASn          ; RAM_DATA[5]   ; 14.205 ; 14.205 ; 14.205 ; 14.205 ;
; ASn          ; RAM_DATA[6]   ; 14.396 ; 14.396 ; 14.396 ; 14.396 ;
; ASn          ; RAM_DATA[7]   ; 14.625 ; 14.686 ; 14.686 ; 14.625 ;
; ASn          ; RAM_DATA[8]   ; 14.693 ; 14.693 ; 14.693 ; 14.693 ;
; ASn          ; RAM_DATA[9]   ; 14.652 ; 14.533 ; 14.533 ; 14.652 ;
; ASn          ; RAM_DATA[10]  ; 14.207 ; 14.127 ; 14.127 ; 14.207 ;
; ASn          ; RAM_DATA[11]  ; 14.310 ; 14.290 ; 14.290 ; 14.310 ;
; ASn          ; RAM_DATA[12]  ; 14.020 ; 14.107 ; 14.107 ; 14.020 ;
; ASn          ; RAM_DATA[13]  ; 13.998 ; 14.081 ; 14.081 ; 13.998 ;
; ASn          ; RAM_DATA[14]  ; 14.520 ; 14.520 ; 14.520 ; 14.520 ;
; ASn          ; RAM_DATA[15]  ; 14.261 ; 14.261 ; 14.261 ; 14.261 ;
; ASn          ; RAM_DQM0H     ;        ; 8.137  ; 8.137  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.230  ; 8.230  ;        ;
; ASn          ; RAM_DQM1H     ; 8.200  ;        ;        ; 8.200  ;
; ASn          ; RAM_DQM1L     ; 8.029  ;        ;        ; 8.029  ;
; ASn          ; RAM_RAS0n     ;        ; 8.506  ; 8.506  ;        ;
; ASn          ; RAM_RAS1n     ; 8.473  ;        ;        ; 8.473  ;
; ASn          ; ROM0n         ; 7.539  ;        ;        ; 7.539  ;
; ASn          ; ROM1n         ; 7.164  ;        ;        ; 7.164  ;
; ASn          ; ROM2n         ; 6.979  ;        ;        ; 6.979  ;
; ASn          ; ROM3n         ; 7.139  ;        ;        ; 7.139  ;
; ASn          ; ROM4n         ; 7.033  ;        ;        ; 7.033  ;
; ASn          ; ROM5n         ; 7.847  ;        ;        ; 7.847  ;
; ASn          ; ROM6n         ; 6.847  ;        ;        ; 6.847  ;
; COM_CTS      ; DATA[2]       ;        ; 9.271  ; 9.271  ;        ;
; COM_CTS      ; DATA[10]      ;        ; 10.282 ; 10.282 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 10.400 ; 10.400 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 10.561 ; 10.561 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.959  ; 9.959  ;        ;
; COM_DCD      ; DATA[9]       ;        ; 9.885  ; 9.885  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.672 ; 10.672 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.769 ; 10.769 ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.078  ; 9.078  ;        ;
; COM_RI       ; DATA[14]      ; 10.954 ; 10.954 ; 10.954 ; 10.954 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.654 ; 10.654 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 11.042 ; 11.042 ; 11.042 ; 11.042 ;
; CONFIG[1]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[1]    ; DATA[15]      ; 11.202 ; 11.202 ; 11.202 ; 11.202 ;
; CONFIG[1]    ; HSYNC         ; 7.120  ; 7.120  ; 7.120  ; 7.120  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.914 ; 11.914 ; 11.914 ; 11.914 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 8.370  ; 8.502  ; 8.502  ; 8.370  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 8.464  ; 8.464  ; 8.464  ; 8.464  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.069  ; 8.184  ; 8.184  ; 8.069  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 11.453 ; 11.453 ; 11.453 ; 11.453 ;
; CONFIG[1]    ; VSYNC         ; 7.191  ; 7.191  ; 7.191  ; 7.191  ;
; CONFIG[2]    ; DATA[7]       ; 10.170 ; 10.170 ; 10.170 ; 10.170 ;
; CONFIG[2]    ; DATA[15]      ; 11.194 ; 11.194 ; 11.194 ; 11.194 ;
; CONFIG[2]    ; HSYNC         ; 7.114  ; 7.114  ; 7.114  ; 7.114  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.906 ; 11.906 ; 11.906 ; 11.906 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 8.490  ; 8.358  ; 8.358  ; 8.490  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.452  ; 8.452  ; 8.452  ; 8.452  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.172  ; 8.057  ; 8.057  ; 8.172  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 11.445 ; 11.445 ; 11.445 ; 11.445 ;
; CONFIG[2]    ; VSYNC         ; 7.182  ; 7.182  ; 7.182  ; 7.182  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.113  ; 8.113  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.229  ; 7.229  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 14.116 ; 14.116 ; 14.116 ; 14.116 ;
; CONFIG[5]    ; ACSI_WRn      ; 14.745 ; 14.745 ; 14.745 ; 14.745 ;
; CONFIG[5]    ; BUTTONn       ; 11.986 ; 11.321 ; 11.321 ; 11.986 ;
; CONFIG[5]    ; CA1_OUT       ; 13.923 ; 13.258 ; 13.258 ; 13.923 ;
; CONFIG[5]    ; CD[0]         ; 17.368 ; 17.368 ; 17.368 ; 17.368 ;
; CONFIG[5]    ; CD[1]         ; 17.425 ; 17.425 ; 17.425 ; 17.425 ;
; CONFIG[5]    ; CD[2]         ; 15.587 ; 15.587 ; 15.587 ; 15.587 ;
; CONFIG[5]    ; CD[3]         ; 17.568 ; 17.568 ; 17.568 ; 17.568 ;
; CONFIG[5]    ; CD[4]         ; 18.208 ; 18.208 ; 18.208 ; 18.208 ;
; CONFIG[5]    ; CD[5]         ; 18.182 ; 18.182 ; 18.182 ; 18.182 ;
; CONFIG[5]    ; CD[6]         ; 18.210 ; 18.210 ; 18.210 ; 18.210 ;
; CONFIG[5]    ; CD[7]         ; 15.390 ; 15.390 ; 15.390 ; 15.390 ;
; CONFIG[5]    ; DATA[0]       ; 15.065 ; 15.157 ; 15.157 ; 15.065 ;
; CONFIG[5]    ; DATA[1]       ; 15.308 ; 15.308 ; 15.308 ; 15.308 ;
; CONFIG[5]    ; DATA[2]       ; 15.123 ; 15.123 ; 15.123 ; 15.123 ;
; CONFIG[5]    ; DATA[3]       ; 15.121 ; 15.193 ; 15.193 ; 15.121 ;
; CONFIG[5]    ; DATA[4]       ; 14.774 ; 14.774 ; 14.774 ; 14.774 ;
; CONFIG[5]    ; DATA[5]       ; 15.182 ; 15.182 ; 15.182 ; 15.182 ;
; CONFIG[5]    ; DATA[6]       ; 15.048 ; 15.048 ; 15.048 ; 15.048 ;
; CONFIG[5]    ; DATA[7]       ; 14.806 ; 14.867 ; 14.867 ; 14.806 ;
; CONFIG[5]    ; DATA[8]       ; 15.674 ; 15.674 ; 15.674 ; 15.674 ;
; CONFIG[5]    ; DATA[9]       ; 15.685 ; 15.566 ; 15.566 ; 15.685 ;
; CONFIG[5]    ; DATA[10]      ; 16.134 ; 16.134 ; 16.134 ; 16.134 ;
; CONFIG[5]    ; DATA[11]      ; 15.736 ; 15.736 ; 15.736 ; 15.736 ;
; CONFIG[5]    ; DATA[12]      ; 15.522 ; 15.471 ; 15.471 ; 15.522 ;
; CONFIG[5]    ; DATA[13]      ; 15.720 ; 15.717 ; 15.717 ; 15.720 ;
; CONFIG[5]    ; DATA[14]      ; 16.349 ; 16.349 ; 16.349 ; 16.349 ;
; CONFIG[5]    ; DATA[15]      ; 15.927 ; 15.927 ; 15.927 ; 15.927 ;
; CONFIG[5]    ; DTACKn        ; 14.362 ; 14.362 ; 14.362 ; 14.362 ;
; CONFIG[5]    ; FLASH_CEn     ; 11.035 ; 10.852 ; 10.852 ; 11.035 ;
; CONFIG[5]    ; FLASH_OEn     ; 11.244 ; 11.061 ; 11.061 ; 11.244 ;
; CONFIG[5]    ; IDE_CS0n      ; 11.457 ; 10.792 ; 10.792 ; 11.457 ;
; CONFIG[5]    ; IDE_CS1n      ; 11.153 ; 10.488 ; 10.488 ; 11.153 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 11.404 ; 10.739 ; 10.739 ; 11.404 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 11.235 ; 10.570 ; 10.570 ; 11.235 ;
; CONFIG[5]    ; IDE_IORDn     ; 11.160 ; 10.495 ; 10.495 ; 11.160 ;
; CONFIG[5]    ; IDE_IOWRn     ; 11.648 ; 10.983 ; 10.983 ; 11.648 ;
; CONFIG[5]    ; JOY_RHn       ; 12.291 ; 11.626 ; 11.626 ; 12.291 ;
; CONFIG[5]    ; JOY_RLn       ; 11.865 ; 11.200 ; 11.200 ; 11.865 ;
; CONFIG[5]    ; JOY_WEn       ; 11.282 ; 11.947 ; 11.947 ; 11.282 ;
; CONFIG[5]    ; JOY_WL        ; 11.667 ; 12.332 ; 12.332 ; 11.667 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 12.663 ; 12.100 ; 12.100 ; 12.663 ;
; CONFIG[5]    ; RAM_BA[0]     ; 11.859 ; 11.296 ; 11.296 ; 11.859 ;
; CONFIG[5]    ; RAM_BA[1]     ; 11.335 ; 10.772 ; 10.772 ; 11.335 ;
; CONFIG[5]    ; RAM_CAS0n     ; 12.801 ; 12.238 ; 12.238 ; 12.801 ;
; CONFIG[5]    ; RAM_CAS1n     ; 11.652 ; 12.215 ; 12.215 ; 11.652 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 16.013 ; 16.105 ; 16.105 ; 16.013 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 16.021 ; 16.021 ; 16.021 ; 16.021 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 16.252 ; 16.252 ; 16.252 ; 16.252 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 16.053 ; 16.125 ; 16.125 ; 16.053 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 16.009 ; 16.009 ; 16.009 ; 16.009 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 16.122 ; 16.122 ; 16.122 ; 16.122 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 16.624 ; 16.624 ; 16.624 ; 16.624 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 16.542 ; 16.603 ; 16.603 ; 16.542 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 16.719 ; 16.719 ; 16.719 ; 16.719 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 16.569 ; 16.450 ; 16.450 ; 16.569 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 16.413 ; 16.413 ; 16.413 ; 16.413 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 16.236 ; 16.236 ; 16.236 ; 16.236 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 16.183 ; 16.132 ; 16.132 ; 16.183 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 16.174 ; 16.171 ; 16.171 ; 16.174 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 16.437 ; 16.437 ; 16.437 ; 16.437 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 16.178 ; 16.178 ; 16.178 ; 16.178 ;
; CONFIG[5]    ; RAM_DQM0H     ; 12.387 ; 11.824 ; 11.824 ; 12.387 ;
; CONFIG[5]    ; RAM_DQM0L     ; 12.480 ; 11.917 ; 11.917 ; 12.480 ;
; CONFIG[5]    ; RAM_DQM1H     ; 11.887 ; 12.450 ; 12.450 ; 11.887 ;
; CONFIG[5]    ; RAM_DQM1L     ; 11.716 ; 12.279 ; 12.279 ; 11.716 ;
; CONFIG[5]    ; RAM_RAS0n     ; 12.756 ; 12.193 ; 12.193 ; 12.756 ;
; CONFIG[5]    ; RAM_RAS1n     ; 12.160 ; 12.723 ; 12.723 ; 12.160 ;
; CONFIG[5]    ; ROM0n         ; 10.815 ; 10.252 ; 10.252 ; 10.815 ;
; CONFIG[5]    ; ROM1n         ; 10.437 ; 9.874  ; 9.874  ; 10.437 ;
; CONFIG[5]    ; ROM2n         ; 10.754 ; 10.571 ; 10.571 ; 10.754 ;
; CONFIG[5]    ; ROM3n         ; 10.467 ; 10.517 ; 10.517 ; 10.467 ;
; CONFIG[5]    ; ROM4n         ; 10.362 ; 10.160 ; 10.160 ; 10.362 ;
; CONFIG[5]    ; ROM5n         ; 10.573 ; 10.704 ; 10.704 ; 10.573 ;
; CONFIG[5]    ; ROM6n         ; 10.177 ; 10.234 ; 10.234 ; 10.177 ;
; CONFIG[6]    ; DATA[0]       ; 11.013 ; 11.013 ; 11.013 ; 11.013 ;
; CONFIG[6]    ; DATA[1]       ; 11.601 ; 11.601 ; 11.601 ; 11.601 ;
; CONFIG[6]    ; DATA[2]       ; 11.161 ; 11.161 ; 11.161 ; 11.161 ;
; CONFIG[6]    ; DATA[3]       ; 11.538 ; 11.538 ; 11.538 ; 11.538 ;
; CONFIG[6]    ; DATA[4]       ; 11.266 ; 11.266 ; 11.266 ; 11.266 ;
; CONFIG[6]    ; DATA[5]       ; 11.270 ; 11.270 ; 11.270 ; 11.270 ;
; CONFIG[6]    ; DATA[6]       ; 10.923 ; 10.923 ; 10.923 ; 10.923 ;
; CONFIG[6]    ; DATA[7]       ; 11.092 ; 11.092 ; 11.092 ; 11.092 ;
; CONFIG[6]    ; DATA[8]       ; 11.656 ; 11.568 ; 11.568 ; 11.656 ;
; CONFIG[6]    ; DATA[9]       ; 11.533 ; 11.533 ; 11.533 ; 11.533 ;
; CONFIG[6]    ; DATA[10]      ; 12.326 ; 12.146 ; 12.146 ; 12.326 ;
; CONFIG[6]    ; DATA[11]      ; 11.890 ; 11.842 ; 11.842 ; 11.890 ;
; CONFIG[6]    ; DATA[12]      ; 11.274 ; 11.498 ; 11.498 ; 11.274 ;
; CONFIG[6]    ; DATA[13]      ; 11.519 ; 11.402 ; 11.402 ; 11.519 ;
; CONFIG[6]    ; DATA[14]      ; 11.268 ; 11.268 ; 11.268 ; 11.268 ;
; CONFIG[6]    ; DATA[15]      ; 10.934 ; 10.934 ; 10.934 ; 10.934 ;
; CONFIG[6]    ; DTACKn        ; 9.685  ; 9.685  ; 9.685  ; 9.685  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.351  ; 7.351  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 6.944  ; 6.944  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 7.995  ; 7.715  ; 7.715  ; 7.995  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.204  ; 7.924  ; 7.924  ; 8.204  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.961 ; 11.961 ; 11.961 ; 11.961 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 12.314 ; 12.314 ; 12.314 ; 12.314 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 12.290 ; 12.290 ; 12.290 ; 12.290 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 12.470 ; 12.470 ; 12.470 ; 12.470 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 12.501 ; 12.501 ; 12.501 ; 12.501 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 12.210 ; 12.210 ; 12.210 ; 12.210 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 12.499 ; 12.499 ; 12.499 ; 12.499 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 12.828 ; 12.828 ; 12.828 ; 12.828 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 12.701 ; 12.613 ; 12.613 ; 12.701 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 12.417 ; 12.417 ; 12.417 ; 12.417 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 12.605 ; 12.425 ; 12.425 ; 12.605 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 12.390 ; 12.342 ; 12.342 ; 12.390 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 11.935 ; 12.159 ; 12.159 ; 11.935 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 11.973 ; 11.856 ; 11.856 ; 11.973 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 11.356 ; 11.356 ; 11.356 ; 11.356 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 11.185 ; 11.185 ; 11.185 ; 11.185 ;
; CONFIG[6]    ; ROM2n         ; 7.714  ; 7.434  ; 7.434  ; 7.714  ;
; CRT_PIN3     ; DATA[7]       ; 7.463  ; 7.463  ; 7.463  ; 7.463  ;
; CRT_PIN3     ; DATA[15]      ; 8.487  ; 8.487  ; 8.487  ; 8.487  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.199  ; 9.199  ; 9.199  ; 9.199  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.829  ; 5.961  ; 5.961  ; 5.829  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.923  ; 5.923  ; 5.923  ; 5.923  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.528  ; 5.643  ; 5.643  ; 5.528  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 8.738  ; 8.738  ; 8.738  ; 8.738  ;
; DATA[0]      ; DATA[0]       ; 8.856  ;        ;        ; 8.856  ;
; DATA[0]      ; RAM_DATA[0]   ; 9.804  ;        ;        ; 9.804  ;
; DATA[1]      ; DATA[1]       ; 9.748  ;        ;        ; 9.748  ;
; DATA[1]      ; RAM_DATA[1]   ; 10.461 ;        ;        ; 10.461 ;
; DATA[2]      ; DATA[2]       ; 8.667  ;        ;        ; 8.667  ;
; DATA[2]      ; RAM_DATA[2]   ; 9.796  ;        ;        ; 9.796  ;
; DATA[3]      ; DATA[3]       ; 9.325  ;        ;        ; 9.325  ;
; DATA[3]      ; RAM_DATA[3]   ; 10.257 ;        ;        ; 10.257 ;
; DATA[4]      ; DATA[4]       ; 8.920  ;        ;        ; 8.920  ;
; DATA[4]      ; RAM_DATA[4]   ; 10.155 ;        ;        ; 10.155 ;
; DATA[5]      ; DATA[5]       ; 8.762  ;        ;        ; 8.762  ;
; DATA[5]      ; RAM_DATA[5]   ; 9.702  ;        ;        ; 9.702  ;
; DATA[6]      ; DATA[6]       ; 8.394  ;        ;        ; 8.394  ;
; DATA[6]      ; RAM_DATA[6]   ; 9.970  ;        ;        ; 9.970  ;
; DATA[7]      ; DATA[7]       ; 8.549  ;        ;        ; 8.549  ;
; DATA[7]      ; RAM_DATA[7]   ; 10.285 ;        ;        ; 10.285 ;
; DATA[8]      ; DATA[8]       ; 9.604  ;        ;        ; 9.604  ;
; DATA[8]      ; RAM_DATA[8]   ; 10.649 ;        ;        ; 10.649 ;
; DATA[9]      ; DATA[9]       ; 9.585  ;        ;        ; 9.585  ;
; DATA[9]      ; RAM_DATA[9]   ; 10.469 ;        ;        ; 10.469 ;
; DATA[10]     ; DATA[10]      ; 9.916  ;        ;        ; 9.916  ;
; DATA[10]     ; RAM_DATA[10]  ; 10.195 ;        ;        ; 10.195 ;
; DATA[11]     ; DATA[11]      ; 9.749  ;        ;        ; 9.749  ;
; DATA[11]     ; RAM_DATA[11]  ; 10.249 ;        ;        ; 10.249 ;
; DATA[12]     ; DATA[12]      ; 9.366  ;        ;        ; 9.366  ;
; DATA[12]     ; RAM_DATA[12]  ; 10.027 ;        ;        ; 10.027 ;
; DATA[13]     ; DATA[13]      ; 9.147  ;        ;        ; 9.147  ;
; DATA[13]     ; RAM_DATA[13]  ; 9.601  ;        ;        ; 9.601  ;
; DATA[14]     ; DATA[14]      ; 7.487  ;        ;        ; 7.487  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.575  ;        ;        ; 7.575  ;
; DATA[15]     ; DATA[15]      ; 7.161  ;        ;        ; 7.161  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.412  ;        ;        ; 7.412  ;
; FC[0]        ; ACSI_RDn      ; 9.243  ; 9.243  ; 9.243  ; 9.243  ;
; FC[0]        ; ACSI_WRn      ; 9.872  ; 9.872  ; 9.872  ; 9.872  ;
; FC[0]        ; BUTTONn       ; 8.110  ; 8.110  ; 8.110  ; 8.110  ;
; FC[0]        ; CA1_OUT       ; 9.050  ; 9.050  ; 9.050  ; 9.050  ;
; FC[0]        ; CD[0]         ; 12.495 ; 12.495 ; 12.495 ; 12.495 ;
; FC[0]        ; CD[1]         ; 12.552 ; 12.552 ; 12.552 ; 12.552 ;
; FC[0]        ; CD[2]         ; 10.714 ; 10.714 ; 10.714 ; 10.714 ;
; FC[0]        ; CD[3]         ; 12.695 ; 12.695 ; 12.695 ; 12.695 ;
; FC[0]        ; CD[4]         ; 13.335 ; 13.335 ; 13.335 ; 13.335 ;
; FC[0]        ; CD[5]         ; 13.309 ; 13.309 ; 13.309 ; 13.309 ;
; FC[0]        ; CD[6]         ; 13.337 ; 13.337 ; 13.337 ; 13.337 ;
; FC[0]        ; CD[7]         ; 10.517 ; 10.517 ; 10.517 ; 10.517 ;
; FC[0]        ; DATA[0]       ; 12.919 ; 12.919 ; 12.919 ; 12.919 ;
; FC[0]        ; DATA[1]       ; 13.344 ; 13.344 ; 13.344 ; 13.344 ;
; FC[0]        ; DATA[2]       ; 12.888 ; 12.888 ; 12.888 ; 12.888 ;
; FC[0]        ; DATA[3]       ; 13.167 ; 13.167 ; 13.167 ; 13.167 ;
; FC[0]        ; DATA[4]       ; 12.791 ; 12.791 ; 12.791 ; 12.791 ;
; FC[0]        ; DATA[5]       ; 13.074 ; 13.074 ; 13.074 ; 13.074 ;
; FC[0]        ; DATA[6]       ; 12.815 ; 12.815 ; 12.815 ; 12.815 ;
; FC[0]        ; DATA[7]       ; 12.561 ; 12.561 ; 12.561 ; 12.561 ;
; FC[0]        ; DATA[8]       ; 13.736 ; 13.736 ; 13.736 ; 13.736 ;
; FC[0]        ; DATA[9]       ; 13.287 ; 13.287 ; 13.287 ; 13.287 ;
; FC[0]        ; DATA[10]      ; 13.899 ; 13.899 ; 13.899 ; 13.899 ;
; FC[0]        ; DATA[11]      ; 13.764 ; 13.764 ; 13.764 ; 13.764 ;
; FC[0]        ; DATA[12]      ; 13.348 ; 13.348 ; 13.348 ; 13.348 ;
; FC[0]        ; DATA[13]      ; 13.557 ; 13.557 ; 13.557 ; 13.557 ;
; FC[0]        ; DATA[14]      ; 14.250 ; 14.250 ; 14.250 ; 14.250 ;
; FC[0]        ; DATA[15]      ; 13.585 ; 13.585 ; 13.585 ; 13.585 ;
; FC[0]        ; DTACKn        ; 11.101 ; 11.101 ; 11.101 ; 11.101 ;
; FC[0]        ; FLASH_CEn     ; 7.851  ; 7.851  ; 7.851  ; 7.851  ;
; FC[0]        ; FLASH_OEn     ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; FC[0]        ; JOY_RHn       ; 8.992  ; 8.992  ; 8.992  ; 8.992  ;
; FC[0]        ; JOY_RLn       ; 8.663  ; 8.663  ; 8.663  ; 8.663  ;
; FC[0]        ; JOY_WEn       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; FC[0]        ; JOY_WL        ; 7.882  ; 7.882  ; 7.882  ; 7.882  ;
; FC[0]        ; RAM_ADR[8]    ; 9.001  ; 9.001  ; 9.001  ; 9.001  ;
; FC[0]        ; RAM_BA[0]     ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; FC[0]        ; RAM_BA[1]     ; 7.673  ; 7.673  ; 7.673  ; 7.673  ;
; FC[0]        ; RAM_CAS0n     ; 9.139  ; 9.139  ; 9.139  ; 9.139  ;
; FC[0]        ; RAM_CAS1n     ; 8.553  ; 8.553  ; 8.553  ; 8.553  ;
; FC[0]        ; RAM_DATA[0]   ; 13.867 ; 13.867 ; 13.867 ; 13.867 ;
; FC[0]        ; RAM_DATA[1]   ; 14.057 ; 14.057 ; 14.057 ; 14.057 ;
; FC[0]        ; RAM_DATA[2]   ; 14.017 ; 14.017 ; 14.017 ; 14.017 ;
; FC[0]        ; RAM_DATA[3]   ; 14.099 ; 14.099 ; 14.099 ; 14.099 ;
; FC[0]        ; RAM_DATA[4]   ; 14.026 ; 14.026 ; 14.026 ; 14.026 ;
; FC[0]        ; RAM_DATA[5]   ; 14.014 ; 14.014 ; 14.014 ; 14.014 ;
; FC[0]        ; RAM_DATA[6]   ; 14.391 ; 14.391 ; 14.391 ; 14.391 ;
; FC[0]        ; RAM_DATA[7]   ; 14.297 ; 14.297 ; 14.297 ; 14.297 ;
; FC[0]        ; RAM_DATA[8]   ; 14.781 ; 14.781 ; 14.781 ; 14.781 ;
; FC[0]        ; RAM_DATA[9]   ; 14.171 ; 14.171 ; 14.171 ; 14.171 ;
; FC[0]        ; RAM_DATA[10]  ; 14.178 ; 14.178 ; 14.178 ; 14.178 ;
; FC[0]        ; RAM_DATA[11]  ; 14.264 ; 14.264 ; 14.264 ; 14.264 ;
; FC[0]        ; RAM_DATA[12]  ; 14.009 ; 14.009 ; 14.009 ; 14.009 ;
; FC[0]        ; RAM_DATA[13]  ; 14.011 ; 14.011 ; 14.011 ; 14.011 ;
; FC[0]        ; RAM_DATA[14]  ; 14.338 ; 14.338 ; 14.338 ; 14.338 ;
; FC[0]        ; RAM_DATA[15]  ; 13.836 ; 13.836 ; 13.836 ; 13.836 ;
; FC[0]        ; RAM_DQM0H     ; 8.725  ; 8.725  ; 8.725  ; 8.725  ;
; FC[0]        ; RAM_DQM0L     ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; FC[0]        ; RAM_DQM1H     ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; FC[0]        ; RAM_DQM1L     ; 8.617  ; 8.617  ; 8.617  ; 8.617  ;
; FC[0]        ; RAM_RAS0n     ; 9.094  ; 9.094  ; 9.094  ; 9.094  ;
; FC[0]        ; RAM_RAS1n     ; 9.061  ; 9.061  ; 9.061  ; 9.061  ;
; FC[0]        ; ROM0n         ; 7.329  ; 7.329  ; 7.329  ; 7.329  ;
; FC[0]        ; ROM1n         ; 6.954  ; 6.954  ; 6.954  ; 6.954  ;
; FC[0]        ; ROM2n         ; 7.570  ; 7.570  ; 7.570  ; 7.570  ;
; FC[0]        ; ROM3n         ; 6.929  ; 6.929  ; 6.929  ; 6.929  ;
; FC[0]        ; ROM4n         ; 6.823  ; 6.823  ; 6.823  ; 6.823  ;
; FC[0]        ; ROM5n         ; 7.637  ; 7.637  ; 7.637  ; 7.637  ;
; FC[0]        ; ROM6n         ; 6.637  ; 6.637  ; 6.637  ; 6.637  ;
; FC[1]        ; ACSI_RDn      ; 9.049  ; 9.049  ; 9.049  ; 9.049  ;
; FC[1]        ; ACSI_WRn      ; 9.678  ; 9.678  ; 9.678  ; 9.678  ;
; FC[1]        ; BUTTONn       ; 8.100  ; 8.100  ; 8.100  ; 8.100  ;
; FC[1]        ; CA1_OUT       ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; FC[1]        ; CD[0]         ; 12.301 ; 12.301 ; 12.301 ; 12.301 ;
; FC[1]        ; CD[1]         ; 12.358 ; 12.358 ; 12.358 ; 12.358 ;
; FC[1]        ; CD[2]         ; 10.520 ; 10.520 ; 10.520 ; 10.520 ;
; FC[1]        ; CD[3]         ; 12.501 ; 12.501 ; 12.501 ; 12.501 ;
; FC[1]        ; CD[4]         ; 13.141 ; 13.141 ; 13.141 ; 13.141 ;
; FC[1]        ; CD[5]         ; 13.115 ; 13.115 ; 13.115 ; 13.115 ;
; FC[1]        ; CD[6]         ; 13.143 ; 13.143 ; 13.143 ; 13.143 ;
; FC[1]        ; CD[7]         ; 10.323 ; 10.323 ; 10.323 ; 10.323 ;
; FC[1]        ; DATA[0]       ; 12.725 ; 12.725 ; 12.725 ; 12.725 ;
; FC[1]        ; DATA[1]       ; 13.150 ; 13.150 ; 13.150 ; 13.150 ;
; FC[1]        ; DATA[2]       ; 12.693 ; 12.693 ; 12.693 ; 12.693 ;
; FC[1]        ; DATA[3]       ; 12.973 ; 12.973 ; 12.973 ; 12.973 ;
; FC[1]        ; DATA[4]       ; 12.597 ; 12.597 ; 12.597 ; 12.597 ;
; FC[1]        ; DATA[5]       ; 12.880 ; 12.880 ; 12.880 ; 12.880 ;
; FC[1]        ; DATA[6]       ; 12.620 ; 12.620 ; 12.620 ; 12.620 ;
; FC[1]        ; DATA[7]       ; 12.390 ; 12.390 ; 12.390 ; 12.390 ;
; FC[1]        ; DATA[8]       ; 13.542 ; 13.542 ; 13.542 ; 13.542 ;
; FC[1]        ; DATA[9]       ; 13.208 ; 13.208 ; 13.208 ; 13.208 ;
; FC[1]        ; DATA[10]      ; 13.704 ; 13.704 ; 13.704 ; 13.704 ;
; FC[1]        ; DATA[11]      ; 13.570 ; 13.570 ; 13.570 ; 13.570 ;
; FC[1]        ; DATA[12]      ; 13.154 ; 13.154 ; 13.154 ; 13.154 ;
; FC[1]        ; DATA[13]      ; 13.363 ; 13.363 ; 13.363 ; 13.363 ;
; FC[1]        ; DATA[14]      ; 14.056 ; 14.056 ; 14.056 ; 14.056 ;
; FC[1]        ; DATA[15]      ; 13.450 ; 13.450 ; 13.450 ; 13.450 ;
; FC[1]        ; DTACKn        ; 11.022 ; 11.022 ; 11.022 ; 11.022 ;
; FC[1]        ; FLASH_CEn     ; 7.841  ; 7.841  ; 7.841  ; 7.841  ;
; FC[1]        ; FLASH_OEn     ; 8.050  ; 8.050  ; 8.050  ; 8.050  ;
; FC[1]        ; JOY_RHn       ; 8.798  ; 8.798  ; 8.798  ; 8.798  ;
; FC[1]        ; JOY_RLn       ; 8.469  ; 8.469  ; 8.469  ; 8.469  ;
; FC[1]        ; JOY_WEn       ; 8.551  ; 8.551  ; 8.551  ; 8.551  ;
; FC[1]        ; JOY_WL        ; 7.688  ; 7.688  ; 7.688  ; 7.688  ;
; FC[1]        ; RAM_ADR[8]    ; 8.991  ; 8.991  ; 8.991  ; 8.991  ;
; FC[1]        ; RAM_BA[0]     ; 8.187  ; 8.187  ; 8.187  ; 8.187  ;
; FC[1]        ; RAM_BA[1]     ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; FC[1]        ; RAM_CAS0n     ; 9.129  ; 9.129  ; 9.129  ; 9.129  ;
; FC[1]        ; RAM_CAS1n     ; 8.543  ; 8.543  ; 8.543  ; 8.543  ;
; FC[1]        ; RAM_DATA[0]   ; 13.673 ; 13.673 ; 13.673 ; 13.673 ;
; FC[1]        ; RAM_DATA[1]   ; 13.863 ; 13.863 ; 13.863 ; 13.863 ;
; FC[1]        ; RAM_DATA[2]   ; 13.822 ; 13.822 ; 13.822 ; 13.822 ;
; FC[1]        ; RAM_DATA[3]   ; 13.905 ; 13.905 ; 13.905 ; 13.905 ;
; FC[1]        ; RAM_DATA[4]   ; 13.832 ; 13.832 ; 13.832 ; 13.832 ;
; FC[1]        ; RAM_DATA[5]   ; 13.820 ; 13.820 ; 13.820 ; 13.820 ;
; FC[1]        ; RAM_DATA[6]   ; 14.196 ; 14.196 ; 14.196 ; 14.196 ;
; FC[1]        ; RAM_DATA[7]   ; 14.126 ; 14.126 ; 14.126 ; 14.126 ;
; FC[1]        ; RAM_DATA[8]   ; 14.587 ; 14.587 ; 14.587 ; 14.587 ;
; FC[1]        ; RAM_DATA[9]   ; 14.092 ; 14.092 ; 14.092 ; 14.092 ;
; FC[1]        ; RAM_DATA[10]  ; 13.983 ; 13.983 ; 13.983 ; 13.983 ;
; FC[1]        ; RAM_DATA[11]  ; 14.070 ; 14.070 ; 14.070 ; 14.070 ;
; FC[1]        ; RAM_DATA[12]  ; 13.815 ; 13.815 ; 13.815 ; 13.815 ;
; FC[1]        ; RAM_DATA[13]  ; 13.817 ; 13.817 ; 13.817 ; 13.817 ;
; FC[1]        ; RAM_DATA[14]  ; 14.144 ; 14.144 ; 14.144 ; 14.144 ;
; FC[1]        ; RAM_DATA[15]  ; 13.701 ; 13.701 ; 13.701 ; 13.701 ;
; FC[1]        ; RAM_DQM0H     ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; FC[1]        ; RAM_DQM0L     ; 8.808  ; 8.808  ; 8.808  ; 8.808  ;
; FC[1]        ; RAM_DQM1H     ; 8.778  ; 8.778  ; 8.778  ; 8.778  ;
; FC[1]        ; RAM_DQM1L     ; 8.607  ; 8.607  ; 8.607  ; 8.607  ;
; FC[1]        ; RAM_RAS0n     ; 9.084  ; 9.084  ; 9.084  ; 9.084  ;
; FC[1]        ; RAM_RAS1n     ; 9.051  ; 9.051  ; 9.051  ; 9.051  ;
; FC[1]        ; ROM0n         ; 7.319  ; 7.319  ; 7.319  ; 7.319  ;
; FC[1]        ; ROM1n         ; 6.944  ; 6.944  ; 6.944  ; 6.944  ;
; FC[1]        ; ROM2n         ; 7.560  ; 7.560  ; 7.560  ; 7.560  ;
; FC[1]        ; ROM3n         ; 6.919  ; 6.919  ; 6.919  ; 6.919  ;
; FC[1]        ; ROM4n         ; 6.813  ; 6.813  ; 6.813  ; 6.813  ;
; FC[1]        ; ROM5n         ; 7.627  ; 7.627  ; 7.627  ; 7.627  ;
; FC[1]        ; ROM6n         ; 6.627  ; 6.627  ; 6.627  ; 6.627  ;
; FC[2]        ; ACSI_RDn      ; 9.139  ; 9.139  ; 9.139  ; 9.139  ;
; FC[2]        ; ACSI_WRn      ; 9.768  ; 9.768  ; 9.768  ; 9.768  ;
; FC[2]        ; CA1_OUT       ;        ; 8.946  ; 8.946  ;        ;
; FC[2]        ; CD[0]         ; 12.391 ; 12.391 ; 12.391 ; 12.391 ;
; FC[2]        ; CD[1]         ; 12.448 ; 12.448 ; 12.448 ; 12.448 ;
; FC[2]        ; CD[2]         ; 10.610 ; 10.610 ; 10.610 ; 10.610 ;
; FC[2]        ; CD[3]         ; 12.591 ; 12.591 ; 12.591 ; 12.591 ;
; FC[2]        ; CD[4]         ; 13.231 ; 13.231 ; 13.231 ; 13.231 ;
; FC[2]        ; CD[5]         ; 13.205 ; 13.205 ; 13.205 ; 13.205 ;
; FC[2]        ; CD[6]         ; 13.233 ; 13.233 ; 13.233 ; 13.233 ;
; FC[2]        ; CD[7]         ; 10.413 ; 10.413 ; 10.413 ; 10.413 ;
; FC[2]        ; DATA[0]       ; 12.815 ; 12.815 ; 12.815 ; 12.815 ;
; FC[2]        ; DATA[1]       ; 13.240 ; 13.240 ; 13.240 ; 13.240 ;
; FC[2]        ; DATA[2]       ; 12.788 ; 12.788 ; 12.788 ; 12.788 ;
; FC[2]        ; DATA[3]       ; 13.063 ; 13.017 ; 13.017 ; 13.063 ;
; FC[2]        ; DATA[4]       ; 12.674 ; 12.687 ; 12.687 ; 12.674 ;
; FC[2]        ; DATA[5]       ; 12.949 ; 12.970 ; 12.970 ; 12.949 ;
; FC[2]        ; DATA[6]       ; 12.715 ; 12.715 ; 12.715 ; 12.715 ;
; FC[2]        ; DATA[7]       ; 12.435 ; 12.457 ; 12.457 ; 12.435 ;
; FC[2]        ; DATA[8]       ; 13.632 ; 13.632 ; 13.632 ; 13.632 ;
; FC[2]        ; DATA[9]       ; 13.166 ; 13.166 ; 13.166 ; 13.166 ;
; FC[2]        ; DATA[10]      ; 13.799 ; 13.799 ; 13.799 ; 13.799 ;
; FC[2]        ; DATA[11]      ; 13.660 ; 13.614 ; 13.614 ; 13.660 ;
; FC[2]        ; DATA[12]      ; 13.231 ; 13.244 ; 13.244 ; 13.231 ;
; FC[2]        ; DATA[13]      ; 13.432 ; 13.453 ; 13.453 ; 13.432 ;
; FC[2]        ; DATA[14]      ; 14.146 ; 14.146 ; 14.146 ; 14.146 ;
; FC[2]        ; DATA[15]      ; 13.481 ; 13.481 ; 13.481 ; 13.481 ;
; FC[2]        ; DTACKn        ; 10.009 ; 10.009 ; 10.009 ; 10.009 ;
; FC[2]        ; JOY_RHn       ;        ; 8.888  ; 8.888  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.559  ; 8.559  ;        ;
; FC[2]        ; JOY_WEn       ; 8.641  ;        ;        ; 8.641  ;
; FC[2]        ; JOY_WL        ; 7.778  ;        ;        ; 7.778  ;
; FC[2]        ; RAM_DATA[0]   ; 13.763 ; 13.763 ; 13.763 ; 13.763 ;
; FC[2]        ; RAM_DATA[1]   ; 13.953 ; 13.953 ; 13.953 ; 13.953 ;
; FC[2]        ; RAM_DATA[2]   ; 13.917 ; 13.917 ; 13.917 ; 13.917 ;
; FC[2]        ; RAM_DATA[3]   ; 13.995 ; 13.949 ; 13.949 ; 13.995 ;
; FC[2]        ; RAM_DATA[4]   ; 13.909 ; 13.922 ; 13.922 ; 13.909 ;
; FC[2]        ; RAM_DATA[5]   ; 13.889 ; 13.910 ; 13.910 ; 13.889 ;
; FC[2]        ; RAM_DATA[6]   ; 14.291 ; 14.291 ; 14.291 ; 14.291 ;
; FC[2]        ; RAM_DATA[7]   ; 14.171 ; 14.193 ; 14.193 ; 14.171 ;
; FC[2]        ; RAM_DATA[8]   ; 14.677 ; 14.677 ; 14.677 ; 14.677 ;
; FC[2]        ; RAM_DATA[9]   ; 14.050 ; 14.050 ; 14.050 ; 14.050 ;
; FC[2]        ; RAM_DATA[10]  ; 14.078 ; 14.078 ; 14.078 ; 14.078 ;
; FC[2]        ; RAM_DATA[11]  ; 14.160 ; 14.114 ; 14.114 ; 14.160 ;
; FC[2]        ; RAM_DATA[12]  ; 13.892 ; 13.905 ; 13.905 ; 13.892 ;
; FC[2]        ; RAM_DATA[13]  ; 13.886 ; 13.907 ; 13.907 ; 13.886 ;
; FC[2]        ; RAM_DATA[14]  ; 14.234 ; 14.234 ; 14.234 ; 14.234 ;
; FC[2]        ; RAM_DATA[15]  ; 13.732 ; 13.732 ; 13.732 ; 13.732 ;
; HDINTn       ; DATA[5]       ; 10.555 ;        ;        ; 10.555 ;
; HDINTn       ; DATA[13]      ; 11.038 ;        ;        ; 11.038 ;
; HDINTn       ; RAM_DATA[5]   ; 11.495 ;        ;        ; 11.495 ;
; HDINTn       ; RAM_DATA[13]  ; 11.492 ;        ;        ; 11.492 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.692 ; 10.692 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 11.175 ; 11.175 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.632 ; 11.632 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 11.629 ; 11.629 ;        ;
; IDE_IORDY    ; DTACKn        ; 9.443  ; 9.443  ; 9.443  ; 9.443  ;
; LDSn         ; ACSI_RDn      ; 8.803  ; 8.803  ; 8.803  ; 8.803  ;
; LDSn         ; ACSI_WRn      ; 9.432  ; 9.432  ; 9.432  ; 9.432  ;
; LDSn         ; BUTTONn       ; 7.446  ;        ;        ; 7.446  ;
; LDSn         ; CA1_OUT       ; 8.610  ;        ;        ; 8.610  ;
; LDSn         ; CD[0]         ; 12.055 ; 12.055 ; 12.055 ; 12.055 ;
; LDSn         ; CD[1]         ; 12.112 ; 12.112 ; 12.112 ; 12.112 ;
; LDSn         ; CD[2]         ; 10.274 ; 10.274 ; 10.274 ; 10.274 ;
; LDSn         ; CD[3]         ; 12.255 ; 12.255 ; 12.255 ; 12.255 ;
; LDSn         ; CD[4]         ; 12.895 ; 12.895 ; 12.895 ; 12.895 ;
; LDSn         ; CD[5]         ; 12.869 ; 12.869 ; 12.869 ; 12.869 ;
; LDSn         ; CD[6]         ; 12.897 ; 12.897 ; 12.897 ; 12.897 ;
; LDSn         ; CD[7]         ; 10.077 ; 10.077 ; 10.077 ; 10.077 ;
; LDSn         ; DATA[0]       ; 12.257 ; 12.313 ; 12.313 ; 12.257 ;
; LDSn         ; DATA[1]       ; 12.596 ; 12.596 ; 12.596 ; 12.596 ;
; LDSn         ; DATA[2]       ; 12.219 ; 12.214 ; 12.214 ; 12.219 ;
; LDSn         ; DATA[3]       ; 12.409 ; 12.481 ; 12.481 ; 12.409 ;
; LDSn         ; DATA[4]       ; 12.062 ; 12.062 ; 12.062 ; 12.062 ;
; LDSn         ; DATA[5]       ; 12.470 ; 12.470 ; 12.470 ; 12.470 ;
; LDSn         ; DATA[6]       ; 12.025 ; 12.025 ; 12.025 ; 12.025 ;
; LDSn         ; DATA[7]       ; 12.094 ; 12.155 ; 12.155 ; 12.094 ;
; LDSn         ; DATA[8]       ; 12.853 ; 12.853 ; 12.853 ; 12.853 ;
; LDSn         ; DATA[9]       ; 12.973 ; 12.854 ; 12.854 ; 12.973 ;
; LDSn         ; DATA[10]      ; 13.133 ; 13.053 ; 13.053 ; 13.133 ;
; LDSn         ; DATA[11]      ; 13.015 ; 12.995 ; 12.995 ; 13.015 ;
; LDSn         ; DATA[12]      ; 12.564 ; 12.651 ; 12.651 ; 12.564 ;
; LDSn         ; DATA[13]      ; 12.749 ; 12.832 ; 12.832 ; 12.749 ;
; LDSn         ; DATA[14]      ; 13.637 ; 13.637 ; 13.637 ; 13.637 ;
; LDSn         ; DATA[15]      ; 13.215 ; 13.215 ; 13.215 ; 13.215 ;
; LDSn         ; DTACKn        ; 10.787 ; 10.787 ; 10.787 ; 10.787 ;
; LDSn         ; IDE_IORDn     ; 6.538  ;        ;        ; 6.538  ;
; LDSn         ; IDE_IOWRn     ; 7.028  ;        ;        ; 7.028  ;
; LDSn         ; JOY_RLn       ; 7.927  ;        ;        ; 7.927  ;
; LDSn         ; JOY_WEn       ;        ; 8.009  ; 8.009  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.860  ; 6.860  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.850  ;        ;        ; 7.850  ;
; LDSn         ; RAM_CAS1n     ; 7.262  ;        ;        ; 7.262  ;
; LDSn         ; RAM_DATA[0]   ; 13.205 ; 13.261 ; 13.261 ; 13.205 ;
; LDSn         ; RAM_DATA[1]   ; 13.309 ; 13.309 ; 13.309 ; 13.309 ;
; LDSn         ; RAM_DATA[2]   ; 13.348 ; 13.343 ; 13.343 ; 13.348 ;
; LDSn         ; RAM_DATA[3]   ; 13.341 ; 13.413 ; 13.413 ; 13.341 ;
; LDSn         ; RAM_DATA[4]   ; 13.297 ; 13.297 ; 13.297 ; 13.297 ;
; LDSn         ; RAM_DATA[5]   ; 13.410 ; 13.410 ; 13.410 ; 13.410 ;
; LDSn         ; RAM_DATA[6]   ; 13.601 ; 13.601 ; 13.601 ; 13.601 ;
; LDSn         ; RAM_DATA[7]   ; 13.830 ; 13.891 ; 13.891 ; 13.830 ;
; LDSn         ; RAM_DATA[8]   ; 13.898 ; 13.898 ; 13.898 ; 13.898 ;
; LDSn         ; RAM_DATA[9]   ; 13.857 ; 13.738 ; 13.738 ; 13.857 ;
; LDSn         ; RAM_DATA[10]  ; 13.412 ; 13.332 ; 13.332 ; 13.412 ;
; LDSn         ; RAM_DATA[11]  ; 13.515 ; 13.495 ; 13.495 ; 13.515 ;
; LDSn         ; RAM_DATA[12]  ; 13.225 ; 13.312 ; 13.312 ; 13.225 ;
; LDSn         ; RAM_DATA[13]  ; 13.203 ; 13.286 ; 13.286 ; 13.203 ;
; LDSn         ; RAM_DATA[14]  ; 13.725 ; 13.725 ; 13.725 ; 13.725 ;
; LDSn         ; RAM_DATA[15]  ; 13.466 ; 13.466 ; 13.466 ; 13.466 ;
; LDSn         ; RAM_DQM0L     ; 7.239  ;        ;        ; 7.239  ;
; LDSn         ; RAM_DQM1L     ; 7.044  ;        ;        ; 7.044  ;
; LPT_BSY      ; DATA[0]       ; 10.282 ;        ;        ; 10.282 ;
; LPT_BSY      ; DATA[8]       ; 11.099 ;        ;        ; 11.099 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.230 ;        ;        ; 11.230 ;
; LPT_BSY      ; RAM_DATA[8]   ; 12.144 ;        ;        ; 12.144 ;
; LPT_D[0]     ; DATA[0]       ; 8.799  ;        ;        ; 8.799  ;
; LPT_D[0]     ; DATA[8]       ; 9.505  ;        ;        ; 9.505  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 9.747  ;        ;        ; 9.747  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.550 ;        ;        ; 10.550 ;
; LPT_D[1]     ; DATA[1]       ; 9.348  ;        ;        ; 9.348  ;
; LPT_D[1]     ; DATA[9]       ; 9.415  ;        ;        ; 9.415  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 10.061 ;        ;        ; 10.061 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.299 ;        ;        ; 10.299 ;
; LPT_D[2]     ; DATA[2]       ; 9.111  ;        ;        ; 9.111  ;
; LPT_D[2]     ; DATA[10]      ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 10.240 ;        ;        ; 10.240 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 10.401 ;        ;        ; 10.401 ;
; LPT_D[3]     ; DATA[3]       ; 9.269  ;        ;        ; 9.269  ;
; LPT_D[3]     ; DATA[11]      ; 9.890  ;        ;        ; 9.890  ;
; LPT_D[3]     ; RAM_DATA[3]   ; 10.201 ;        ;        ; 10.201 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 10.390 ;        ;        ; 10.390 ;
; LPT_D[4]     ; DATA[4]       ; 9.991  ;        ;        ; 9.991  ;
; LPT_D[4]     ; DATA[12]      ; 10.465 ;        ;        ; 10.465 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.226 ;        ;        ; 11.226 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 11.126 ;        ;        ; 11.126 ;
; LPT_D[5]     ; DATA[5]       ; 9.074  ;        ;        ; 9.074  ;
; LPT_D[5]     ; DATA[13]      ; 9.802  ;        ;        ; 9.802  ;
; LPT_D[5]     ; RAM_DATA[5]   ; 10.014 ;        ;        ; 10.014 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.256 ;        ;        ; 10.256 ;
; LPT_D[6]     ; DATA[6]       ; 9.006  ;        ;        ; 9.006  ;
; LPT_D[6]     ; DATA[14]      ; 10.251 ; 10.251 ; 10.251 ; 10.251 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 10.582 ;        ;        ; 10.582 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.339 ; 10.339 ; 10.339 ; 10.339 ;
; LPT_D[7]     ; DATA[7]       ; 9.165  ;        ;        ; 9.165  ;
; LPT_D[7]     ; DATA[15]      ; 10.014 ; 10.014 ; 10.014 ; 10.014 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.901 ;        ;        ; 10.901 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; MIDI_IN      ; MIDI_TLR      ; 4.716  ;        ;        ; 4.716  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.865  ;        ;        ; 9.865  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.813 ;        ;        ; 10.813 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.692 ;        ;        ; 10.692 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 11.405 ;        ;        ; 11.405 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.678 ;        ;        ; 10.678 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 11.807 ;        ;        ; 11.807 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.963  ;        ;        ; 9.963  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.895 ;        ;        ; 10.895 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.697  ;        ;        ; 9.697  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.385 ;        ;        ; 10.385 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.325 ;        ;        ; 11.325 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.820  ;        ;        ; 9.820  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.396 ;        ;        ; 11.396 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.099 ;        ;        ; 10.099 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.835 ;        ;        ; 11.835 ;
; RAM_DATA[8]  ; DATA[8]       ; 11.045 ;        ;        ; 11.045 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 12.090 ;        ;        ; 12.090 ;
; RAM_DATA[9]  ; DATA[9]       ; 10.424 ;        ;        ; 10.424 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.308 ;        ;        ; 11.308 ;
; RAM_DATA[10] ; DATA[10]      ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 11.211 ;        ;        ; 11.211 ;
; RAM_DATA[11] ; DATA[11]      ; 10.739 ;        ;        ; 10.739 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 11.239 ;        ;        ; 11.239 ;
; RAM_DATA[12] ; DATA[12]      ; 10.066 ;        ;        ; 10.066 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 10.727 ;        ;        ; 10.727 ;
; RAM_DATA[13] ; DATA[13]      ; 10.635 ;        ;        ; 10.635 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 11.089 ;        ;        ; 11.089 ;
; RAM_DATA[14] ; DATA[14]      ; 10.811 ; 10.811 ; 10.811 ; 10.811 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.899 ; 10.899 ; 10.899 ; 10.899 ;
; RAM_DATA[15] ; DATA[15]      ; 11.044 ; 11.044 ; 11.044 ; 11.044 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 11.295 ; 11.295 ; 11.295 ; 11.295 ;
; RWn          ; ACSI_RDn      ; 8.785  ; 8.785  ; 8.785  ; 8.785  ;
; RWn          ; ACSI_WRn      ; 9.414  ; 9.414  ; 9.414  ; 9.414  ;
; RWn          ; BUTTONn       ;        ; 7.486  ; 7.486  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.592  ; 8.592  ;        ;
; RWn          ; CD[0]         ; 12.037 ; 12.037 ; 12.037 ; 12.037 ;
; RWn          ; CD[1]         ; 12.094 ; 12.094 ; 12.094 ; 12.094 ;
; RWn          ; CD[2]         ; 10.256 ; 10.256 ; 10.256 ; 10.256 ;
; RWn          ; CD[3]         ; 12.237 ; 12.237 ; 12.237 ; 12.237 ;
; RWn          ; CD[4]         ; 12.877 ; 12.877 ; 12.877 ; 12.877 ;
; RWn          ; CD[5]         ; 12.851 ; 12.851 ; 12.851 ; 12.851 ;
; RWn          ; CD[6]         ; 12.879 ; 12.879 ; 12.879 ; 12.879 ;
; RWn          ; CD[7]         ; 10.059 ; 10.059 ; 10.059 ; 10.059 ;
; RWn          ; DATA[0]       ; 12.461 ; 12.461 ; 12.461 ; 12.461 ;
; RWn          ; DATA[1]       ; 12.886 ; 12.886 ; 12.886 ; 12.886 ;
; RWn          ; DATA[2]       ; 12.429 ; 12.429 ; 12.429 ; 12.429 ;
; RWn          ; DATA[3]       ; 12.709 ; 12.663 ; 12.663 ; 12.709 ;
; RWn          ; DATA[4]       ; 12.320 ; 12.333 ; 12.333 ; 12.320 ;
; RWn          ; DATA[5]       ; 12.595 ; 12.616 ; 12.616 ; 12.595 ;
; RWn          ; DATA[6]       ; 12.356 ; 12.356 ; 12.356 ; 12.356 ;
; RWn          ; DATA[7]       ; 12.081 ; 12.103 ; 12.103 ; 12.081 ;
; RWn          ; DATA[8]       ; 13.278 ; 13.278 ; 13.278 ; 13.278 ;
; RWn          ; DATA[9]       ; 12.812 ; 12.812 ; 12.812 ; 12.812 ;
; RWn          ; DATA[10]      ; 13.440 ; 13.440 ; 13.440 ; 13.440 ;
; RWn          ; DATA[11]      ; 13.306 ; 13.260 ; 13.260 ; 13.306 ;
; RWn          ; DATA[12]      ; 12.877 ; 12.890 ; 12.890 ; 12.877 ;
; RWn          ; DATA[13]      ; 13.078 ; 13.099 ; 13.099 ; 13.078 ;
; RWn          ; DATA[14]      ; 13.792 ; 13.792 ; 13.792 ; 13.792 ;
; RWn          ; DATA[15]      ; 13.127 ; 13.127 ; 13.127 ; 13.127 ;
; RWn          ; DTACKn        ; 10.532 ; 10.532 ; 10.532 ; 10.532 ;
; RWn          ; FLASH_CEn     ;        ; 7.094  ; 7.094  ;        ;
; RWn          ; FLASH_OEn     ;        ; 7.303  ; 7.303  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.192  ; 7.192  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.436  ;        ;        ; 6.436  ;
; RWn          ; IDE_IORDn     ;        ; 6.489  ; 6.489  ;        ;
; RWn          ; IDE_IOWRn     ; 6.977  ;        ;        ; 6.977  ;
; RWn          ; JOY_RHn       ;        ; 8.534  ; 8.534  ;        ;
; RWn          ; JOY_RLn       ;        ; 8.205  ; 8.205  ;        ;
; RWn          ; JOY_WEn       ; 8.287  ;        ;        ; 8.287  ;
; RWn          ; JOY_WL        ; 7.424  ; 6.804  ; 6.804  ; 7.424  ;
; RWn          ; RAM_DATA[0]   ; 13.409 ; 13.409 ; 13.409 ; 13.409 ;
; RWn          ; RAM_DATA[1]   ; 13.599 ; 13.599 ; 13.599 ; 13.599 ;
; RWn          ; RAM_DATA[2]   ; 13.558 ; 13.558 ; 13.558 ; 13.558 ;
; RWn          ; RAM_DATA[3]   ; 13.641 ; 13.595 ; 13.595 ; 13.641 ;
; RWn          ; RAM_DATA[4]   ; 13.555 ; 13.568 ; 13.568 ; 13.555 ;
; RWn          ; RAM_DATA[5]   ; 13.535 ; 13.556 ; 13.556 ; 13.535 ;
; RWn          ; RAM_DATA[6]   ; 13.932 ; 13.932 ; 13.932 ; 13.932 ;
; RWn          ; RAM_DATA[7]   ; 13.817 ; 13.839 ; 13.839 ; 13.817 ;
; RWn          ; RAM_DATA[8]   ; 14.323 ; 14.323 ; 14.323 ; 14.323 ;
; RWn          ; RAM_DATA[9]   ; 13.696 ; 13.696 ; 13.696 ; 13.696 ;
; RWn          ; RAM_DATA[10]  ; 13.719 ; 13.719 ; 13.719 ; 13.719 ;
; RWn          ; RAM_DATA[11]  ; 13.806 ; 13.760 ; 13.760 ; 13.806 ;
; RWn          ; RAM_DATA[12]  ; 13.538 ; 13.551 ; 13.551 ; 13.538 ;
; RWn          ; RAM_DATA[13]  ; 13.532 ; 13.553 ; 13.553 ; 13.532 ;
; RWn          ; RAM_DATA[14]  ; 13.880 ; 13.880 ; 13.880 ; 13.880 ;
; RWn          ; RAM_DATA[15]  ; 13.378 ; 13.378 ; 13.378 ; 13.378 ;
; RWn          ; RAM_WEn       ; 7.215  ;        ;        ; 7.215  ;
; RWn          ; ROM0n         ;        ; 7.133  ; 7.133  ;        ;
; RWn          ; ROM1n         ;        ; 6.758  ; 6.758  ;        ;
; RWn          ; ROM2n         ;        ; 6.813  ; 6.813  ;        ;
; RWn          ; ROM3n         ;        ; 6.733  ; 6.733  ;        ;
; RWn          ; ROM4n         ;        ; 6.627  ; 6.627  ;        ;
; RWn          ; ROM5n         ;        ; 7.441  ; 7.441  ;        ;
; RWn          ; ROM6n         ;        ; 6.441  ; 6.441  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.502  ; 7.502  ; 7.502  ; 7.502  ;
; SCSI_ATNn    ; CD[1]         ; 8.338  ; 8.338  ; 8.338  ; 8.338  ;
; SCSI_BSYn    ; CD[6]         ; 10.200 ; 10.200 ; 10.200 ; 10.200 ;
; SCSI_D[0]    ; CD[0]         ; 7.818  ; 7.818  ; 7.818  ; 7.818  ;
; SCSI_D[1]    ; CD[1]         ; 7.467  ; 7.467  ; 7.467  ; 7.467  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.645  ; 7.645  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.458  ; 7.458  ; 7.458  ; 7.458  ;
; SCSI_D[4]    ; CD[4]         ; 10.375 ; 10.375 ; 10.375 ; 10.375 ;
; SCSI_D[5]    ; CD[5]         ; 10.138 ; 10.138 ; 10.138 ; 10.138 ;
; SCSI_D[6]    ; CD[6]         ; 10.212 ; 10.212 ; 10.212 ; 10.212 ;
; SCSI_D[7]    ; CD[7]         ; 8.008  ; 8.008  ; 8.008  ; 8.008  ;
; SCSI_DCn     ; CD[3]         ; 8.212  ; 8.212  ; 8.212  ; 8.212  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.758  ; 7.758  ; 7.758  ; 7.758  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_DP       ; 7.214  ; 7.214  ; 7.214  ; 7.214  ;
; SCSI_DP      ; CD[0]         ; 7.345  ; 7.345  ; 7.345  ; 7.345  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.002  ; 6.002  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.217  ;        ;        ; 6.217  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.034  ; 6.034  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.118  ;        ;        ; 6.118  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.290  ; 6.290  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.098  ;        ;        ; 6.098  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.578  ; 6.578  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.278  ;        ;        ; 6.278  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.744  ; 6.744  ; 6.744  ; 6.744  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.746  ; 5.746  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.996  ; 5.996  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.776  ;        ;        ; 5.776  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.885  ;        ;        ; 5.885  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.036  ; 6.036  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 5.880  ; 5.880  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.044  ;        ;        ; 6.044  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.492  ; 6.492  ; 6.492  ; 6.492  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.042  ; 6.042  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.291  ; 6.291  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.069  ; 6.069  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.179  ; 6.179  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.170  ;        ;        ; 6.170  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.623  ;        ;        ; 6.623  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.789  ; 6.789  ; 6.789  ; 6.789  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.849  ; 7.849  ;        ;
; SCSI_IOn     ; CD[3]         ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 7.460  ; 7.460  ; 7.460  ; 7.460  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.906  ; 6.906  ; 6.906  ; 6.906  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.906  ; 6.906  ; 6.906  ; 6.906  ;
; SCSI_IOn     ; SCSI_D[2]     ; 6.705  ; 6.705  ; 6.705  ; 6.705  ;
; SCSI_IOn     ; SCSI_D[3]     ; 6.705  ; 6.705  ; 6.705  ; 6.705  ;
; SCSI_IOn     ; SCSI_D[4]     ; 6.825  ; 6.825  ; 6.825  ; 6.825  ;
; SCSI_IOn     ; SCSI_D[5]     ; 6.825  ; 6.825  ; 6.825  ; 6.825  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.929  ; 6.929  ; 6.929  ; 6.929  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.929  ; 6.929  ; 6.929  ; 6.929  ;
; SCSI_IOn     ; SCSI_DP       ; 6.916  ; 6.916  ; 6.916  ; 6.916  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.523  ;        ;        ; 6.523  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.463  ; 6.463  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.066  ; 8.066  ; 8.066  ; 8.066  ;
; SCSI_MSGn    ; CD[4]         ; 9.988  ; 9.988  ; 9.988  ; 9.988  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.612  ; 7.612  ; 7.612  ; 7.612  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.068  ; 7.068  ; 7.068  ; 7.068  ;
; SCSI_REQn    ; CD[3]         ; 8.082  ; 8.082  ; 8.082  ; 8.082  ;
; SCSI_REQn    ; CD[5]         ; 9.873  ; 9.873  ; 9.873  ; 9.873  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.628  ;        ;        ; 7.628  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[2]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[3]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[4]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[5]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_DP       ; 7.084  ; 7.084  ; 7.084  ; 7.084  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.248  ; 8.248  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.409  ; 7.409  ; 7.409  ; 7.409  ;
; SD_AVR_ENn   ; RESETn        ;        ; 8.539  ; 8.539  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.467  ; 6.467  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 5.432  ; 5.432  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.457  ;        ;        ; 6.457  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.305  ;        ;        ; 6.305  ;
; SD_RESETn    ; ACSI_RDn      ; 9.922  ; 9.922  ; 9.922  ; 9.922  ;
; SD_RESETn    ; ACSI_WRn      ; 10.551 ; 10.551 ; 10.551 ; 10.551 ;
; SD_RESETn    ; CA1_OUT       ; 9.729  ;        ;        ; 9.729  ;
; SD_RESETn    ; CD[0]         ; 13.174 ; 13.174 ; 13.174 ; 13.174 ;
; SD_RESETn    ; CD[1]         ; 13.231 ; 13.231 ; 13.231 ; 13.231 ;
; SD_RESETn    ; CD[2]         ; 11.393 ; 11.393 ; 11.393 ; 11.393 ;
; SD_RESETn    ; CD[3]         ; 13.374 ; 13.374 ; 13.374 ; 13.374 ;
; SD_RESETn    ; CD[4]         ; 14.014 ; 14.014 ; 14.014 ; 14.014 ;
; SD_RESETn    ; CD[5]         ; 13.988 ; 13.988 ; 13.988 ; 13.988 ;
; SD_RESETn    ; CD[6]         ; 14.016 ; 14.016 ; 14.016 ; 14.016 ;
; SD_RESETn    ; CD[7]         ; 11.196 ; 11.196 ; 11.196 ; 11.196 ;
; SD_RESETn    ; COM_TxD       ; 8.602  ; 8.602  ; 8.602  ; 8.602  ;
; SD_RESETn    ; DATA[0]       ; 11.757 ; 11.867 ; 11.867 ; 11.757 ;
; SD_RESETn    ; DATA[1]       ; 11.956 ; 11.956 ; 11.956 ; 11.956 ;
; SD_RESETn    ; DATA[2]       ; 11.390 ; 11.390 ; 11.390 ; 11.390 ;
; SD_RESETn    ; DATA[3]       ; 11.734 ; 11.734 ; 11.734 ; 11.734 ;
; SD_RESETn    ; DATA[4]       ; 11.648 ; 11.648 ; 11.648 ; 11.648 ;
; SD_RESETn    ; DATA[5]       ; 11.610 ; 11.610 ; 11.610 ; 11.610 ;
; SD_RESETn    ; DATA[6]       ; 11.474 ; 11.474 ; 11.474 ; 11.474 ;
; SD_RESETn    ; DATA[7]       ; 11.688 ; 11.688 ; 11.688 ; 11.688 ;
; SD_RESETn    ; DATA[8]       ; 12.492 ; 12.602 ; 12.602 ; 12.492 ;
; SD_RESETn    ; DATA[9]       ; 12.331 ; 12.331 ; 12.331 ; 12.331 ;
; SD_RESETn    ; DATA[10]      ; 12.511 ; 12.511 ; 12.511 ; 12.511 ;
; SD_RESETn    ; DATA[11]      ; 12.311 ; 12.311 ; 12.311 ; 12.311 ;
; SD_RESETn    ; DATA[12]      ; 12.033 ; 12.033 ; 12.033 ; 12.033 ;
; SD_RESETn    ; DATA[13]      ; 11.982 ; 11.982 ; 11.982 ; 11.982 ;
; SD_RESETn    ; DATA[14]      ; 13.009 ; 13.009 ; 13.009 ; 13.009 ;
; SD_RESETn    ; DATA[15]      ; 12.616 ; 12.616 ; 12.616 ; 12.616 ;
; SD_RESETn    ; DTACKn        ; 8.763  ; 8.763  ; 8.763  ; 8.763  ;
; SD_RESETn    ; RAM_DATA[0]   ; 12.705 ; 12.815 ; 12.815 ; 12.705 ;
; SD_RESETn    ; RAM_DATA[1]   ; 12.669 ; 12.669 ; 12.669 ; 12.669 ;
; SD_RESETn    ; RAM_DATA[2]   ; 12.519 ; 12.519 ; 12.519 ; 12.519 ;
; SD_RESETn    ; RAM_DATA[3]   ; 12.666 ; 12.666 ; 12.666 ; 12.666 ;
; SD_RESETn    ; RAM_DATA[4]   ; 12.883 ; 12.883 ; 12.883 ; 12.883 ;
; SD_RESETn    ; RAM_DATA[5]   ; 12.550 ; 12.550 ; 12.550 ; 12.550 ;
; SD_RESETn    ; RAM_DATA[6]   ; 13.050 ; 13.050 ; 13.050 ; 13.050 ;
; SD_RESETn    ; RAM_DATA[7]   ; 13.424 ; 13.424 ; 13.424 ; 13.424 ;
; SD_RESETn    ; RAM_DATA[8]   ; 13.537 ; 13.647 ; 13.647 ; 13.537 ;
; SD_RESETn    ; RAM_DATA[9]   ; 13.215 ; 13.215 ; 13.215 ; 13.215 ;
; SD_RESETn    ; RAM_DATA[10]  ; 12.790 ; 12.790 ; 12.790 ; 12.790 ;
; SD_RESETn    ; RAM_DATA[11]  ; 12.811 ; 12.811 ; 12.811 ; 12.811 ;
; SD_RESETn    ; RAM_DATA[12]  ; 12.694 ; 12.694 ; 12.694 ; 12.694 ;
; SD_RESETn    ; RAM_DATA[13]  ; 12.436 ; 12.436 ; 12.436 ; 12.436 ;
; SD_RESETn    ; RAM_DATA[14]  ; 13.097 ; 13.097 ; 13.097 ; 13.097 ;
; SD_RESETn    ; RAM_DATA[15]  ; 12.867 ; 12.867 ; 12.867 ; 12.867 ;
; UDSn         ; ACSI_RDn      ; 9.556  ; 9.556  ; 9.556  ; 9.556  ;
; UDSn         ; ACSI_WRn      ; 10.185 ; 10.185 ; 10.185 ; 10.185 ;
; UDSn         ; CA1_OUT       ; 9.363  ;        ;        ; 9.363  ;
; UDSn         ; CD[0]         ; 12.808 ; 12.808 ; 12.808 ; 12.808 ;
; UDSn         ; CD[1]         ; 12.865 ; 12.865 ; 12.865 ; 12.865 ;
; UDSn         ; CD[2]         ; 11.027 ; 11.027 ; 11.027 ; 11.027 ;
; UDSn         ; CD[3]         ; 13.008 ; 13.008 ; 13.008 ; 13.008 ;
; UDSn         ; CD[4]         ; 13.648 ; 13.648 ; 13.648 ; 13.648 ;
; UDSn         ; CD[5]         ; 13.622 ; 13.622 ; 13.622 ; 13.622 ;
; UDSn         ; CD[6]         ; 13.650 ; 13.650 ; 13.650 ; 13.650 ;
; UDSn         ; CD[7]         ; 10.830 ; 10.830 ; 10.830 ; 10.830 ;
; UDSn         ; DATA[0]       ; 12.522 ; 12.578 ; 12.578 ; 12.522 ;
; UDSn         ; DATA[1]       ; 12.861 ; 12.861 ; 12.861 ; 12.861 ;
; UDSn         ; DATA[2]       ; 12.484 ; 12.479 ; 12.479 ; 12.484 ;
; UDSn         ; DATA[3]       ; 12.674 ; 12.746 ; 12.746 ; 12.674 ;
; UDSn         ; DATA[4]       ; 12.327 ; 12.327 ; 12.327 ; 12.327 ;
; UDSn         ; DATA[5]       ; 12.735 ; 12.735 ; 12.735 ; 12.735 ;
; UDSn         ; DATA[6]       ; 12.290 ; 12.290 ; 12.290 ; 12.290 ;
; UDSn         ; DATA[7]       ; 12.359 ; 12.420 ; 12.420 ; 12.359 ;
; UDSn         ; DATA[8]       ; 13.118 ; 13.118 ; 13.118 ; 13.118 ;
; UDSn         ; DATA[9]       ; 13.238 ; 13.119 ; 13.119 ; 13.238 ;
; UDSn         ; DATA[10]      ; 13.398 ; 13.318 ; 13.318 ; 13.398 ;
; UDSn         ; DATA[11]      ; 13.280 ; 13.260 ; 13.260 ; 13.280 ;
; UDSn         ; DATA[12]      ; 12.829 ; 12.916 ; 12.916 ; 12.829 ;
; UDSn         ; DATA[13]      ; 13.014 ; 13.097 ; 13.097 ; 13.014 ;
; UDSn         ; DATA[14]      ; 13.902 ; 13.902 ; 13.902 ; 13.902 ;
; UDSn         ; DATA[15]      ; 13.480 ; 13.480 ; 13.480 ; 13.480 ;
; UDSn         ; DTACKn        ; 11.052 ; 11.052 ; 11.052 ; 11.052 ;
; UDSn         ; JOY_RHn       ; 7.055  ;        ;        ; 7.055  ;
; UDSn         ; RAM_CAS0n     ; 7.564  ;        ;        ; 7.564  ;
; UDSn         ; RAM_CAS1n     ; 6.976  ;        ;        ; 6.976  ;
; UDSn         ; RAM_DATA[0]   ; 13.470 ; 13.526 ; 13.526 ; 13.470 ;
; UDSn         ; RAM_DATA[1]   ; 13.574 ; 13.574 ; 13.574 ; 13.574 ;
; UDSn         ; RAM_DATA[2]   ; 13.613 ; 13.608 ; 13.608 ; 13.613 ;
; UDSn         ; RAM_DATA[3]   ; 13.606 ; 13.678 ; 13.678 ; 13.606 ;
; UDSn         ; RAM_DATA[4]   ; 13.562 ; 13.562 ; 13.562 ; 13.562 ;
; UDSn         ; RAM_DATA[5]   ; 13.675 ; 13.675 ; 13.675 ; 13.675 ;
; UDSn         ; RAM_DATA[6]   ; 13.866 ; 13.866 ; 13.866 ; 13.866 ;
; UDSn         ; RAM_DATA[7]   ; 14.095 ; 14.156 ; 14.156 ; 14.095 ;
; UDSn         ; RAM_DATA[8]   ; 14.163 ; 14.163 ; 14.163 ; 14.163 ;
; UDSn         ; RAM_DATA[9]   ; 14.122 ; 14.003 ; 14.003 ; 14.122 ;
; UDSn         ; RAM_DATA[10]  ; 13.677 ; 13.597 ; 13.597 ; 13.677 ;
; UDSn         ; RAM_DATA[11]  ; 13.780 ; 13.760 ; 13.760 ; 13.780 ;
; UDSn         ; RAM_DATA[12]  ; 13.490 ; 13.577 ; 13.577 ; 13.490 ;
; UDSn         ; RAM_DATA[13]  ; 13.468 ; 13.551 ; 13.551 ; 13.468 ;
; UDSn         ; RAM_DATA[14]  ; 13.990 ; 13.990 ; 13.990 ; 13.990 ;
; UDSn         ; RAM_DATA[15]  ; 13.731 ; 13.731 ; 13.731 ; 13.731 ;
; UDSn         ; RAM_DQM0H     ; 6.854  ;        ;        ; 6.854  ;
; UDSn         ; RAM_DQM1H     ; 6.925  ;        ;        ; 6.925  ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 9.340  ; 9.340  ; 9.340  ; 9.340  ;
; ASn          ; ACSI_WRn      ; 9.969  ; 9.969  ; 9.969  ; 9.969  ;
; ASn          ; BUTTONn       ; 7.765  ;        ;        ; 7.765  ;
; ASn          ; CA1_OUT       ; 9.893  ;        ;        ; 9.893  ;
; ASn          ; CD[0]         ; 10.218 ; 10.218 ; 10.218 ; 10.218 ;
; ASn          ; CD[1]         ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; ASn          ; CD[2]         ; 9.743  ; 9.701  ; 9.701  ; 9.743  ;
; ASn          ; CD[3]         ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; ASn          ; CD[4]         ; 9.861  ; 9.861  ; 9.861  ; 9.861  ;
; ASn          ; CD[5]         ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; ASn          ; CD[6]         ; 10.029 ; 10.029 ; 10.029 ; 10.029 ;
; ASn          ; CD[7]         ; 9.549  ; 9.549  ; 9.549  ; 9.549  ;
; ASn          ; DATA[0]       ; 8.511  ; 8.700  ; 8.700  ; 8.511  ;
; ASn          ; DATA[1]       ; 8.831  ; 8.831  ; 8.831  ; 8.831  ;
; ASn          ; DATA[2]       ; 8.488  ; 8.262  ; 8.262  ; 8.488  ;
; ASn          ; DATA[3]       ; 8.876  ; 8.764  ; 8.764  ; 8.876  ;
; ASn          ; DATA[4]       ; 8.416  ; 8.416  ; 8.416  ; 8.416  ;
; ASn          ; DATA[5]       ; 8.520  ; 8.520  ; 8.520  ; 8.520  ;
; ASn          ; DATA[6]       ; 8.231  ; 8.231  ; 8.231  ; 8.231  ;
; ASn          ; DATA[7]       ; 8.651  ; 8.483  ; 8.483  ; 8.651  ;
; ASn          ; DATA[8]       ; 8.876  ; 8.876  ; 8.876  ; 8.876  ;
; ASn          ; DATA[9]       ; 8.876  ; 8.876  ; 8.876  ; 8.876  ;
; ASn          ; DATA[10]      ; 9.012  ; 9.012  ; 9.012  ; 9.012  ;
; ASn          ; DATA[11]      ; 9.012  ; 9.012  ; 9.012  ; 9.012  ;
; ASn          ; DATA[12]      ; 8.797  ; 8.797  ; 8.797  ; 8.797  ;
; ASn          ; DATA[13]      ; 8.917  ; 8.917  ; 8.917  ; 8.917  ;
; ASn          ; DATA[14]      ; 9.060  ; 9.060  ; 9.060  ; 9.060  ;
; ASn          ; DATA[15]      ; 9.050  ; 9.050  ; 9.050  ; 9.050  ;
; ASn          ; DTACKn        ; 8.121  ; 8.121  ; 8.121  ; 8.121  ;
; ASn          ; FLASH_CEn     ; 7.260  ;        ;        ; 7.260  ;
; ASn          ; FLASH_OEn     ; 7.469  ;        ;        ; 7.469  ;
; ASn          ; IDE_CS0n      ; 6.658  ;        ;        ; 6.658  ;
; ASn          ; IDE_CS1n      ; 6.283  ;        ;        ; 6.283  ;
; ASn          ; IDE_D_EN_INn  ; 7.626  ;        ;        ; 7.626  ;
; ASn          ; IDE_D_EN_OUTn ; 7.457  ;        ;        ; 7.457  ;
; ASn          ; IDE_IORDn     ; 7.382  ;        ;        ; 7.382  ;
; ASn          ; IDE_IOWRn     ; 7.870  ;        ;        ; 7.870  ;
; ASn          ; JOY_RHn       ; 7.921  ;        ;        ; 7.921  ;
; ASn          ; JOY_RLn       ; 7.592  ;        ;        ; 7.592  ;
; ASn          ; JOY_WEn       ;        ; 7.674  ; 7.674  ;        ;
; ASn          ; JOY_WL        ;        ; 6.811  ; 6.811  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.413  ; 8.413  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.609  ; 7.609  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.085  ; 7.085  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 8.551  ; 8.551  ;        ;
; ASn          ; RAM_CAS1n     ; 7.965  ;        ;        ; 7.965  ;
; ASn          ; RAM_DATA[0]   ; 9.459  ; 9.648  ; 9.648  ; 9.459  ;
; ASn          ; RAM_DATA[1]   ; 9.544  ; 9.544  ; 9.544  ; 9.544  ;
; ASn          ; RAM_DATA[2]   ; 9.617  ; 9.391  ; 9.391  ; 9.617  ;
; ASn          ; RAM_DATA[3]   ; 9.861  ; 9.696  ; 9.696  ; 9.861  ;
; ASn          ; RAM_DATA[4]   ; 9.651  ; 9.651  ; 9.651  ; 9.651  ;
; ASn          ; RAM_DATA[5]   ; 9.460  ; 9.460  ; 9.460  ; 9.460  ;
; ASn          ; RAM_DATA[6]   ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; ASn          ; RAM_DATA[7]   ; 10.387 ; 10.219 ; 10.219 ; 10.387 ;
; ASn          ; RAM_DATA[8]   ; 10.129 ; 10.480 ; 10.480 ; 10.129 ;
; ASn          ; RAM_DATA[9]   ; 9.957  ; 9.957  ; 9.957  ; 9.957  ;
; ASn          ; RAM_DATA[10]  ; 9.613  ; 9.613  ; 9.613  ; 9.613  ;
; ASn          ; RAM_DATA[11]  ; 9.789  ; 9.789  ; 9.789  ; 9.789  ;
; ASn          ; RAM_DATA[12]  ; 9.458  ; 9.458  ; 9.458  ; 9.458  ;
; ASn          ; RAM_DATA[13]  ; 9.371  ; 9.371  ; 9.371  ; 9.371  ;
; ASn          ; RAM_DATA[14]  ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; ASn          ; RAM_DATA[15]  ; 9.743  ; 9.743  ; 9.743  ; 9.743  ;
; ASn          ; RAM_DQM0H     ;        ; 8.137  ; 8.137  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.230  ; 8.230  ;        ;
; ASn          ; RAM_DQM1H     ; 8.200  ;        ;        ; 8.200  ;
; ASn          ; RAM_DQM1L     ; 8.029  ;        ;        ; 8.029  ;
; ASn          ; RAM_RAS0n     ;        ; 8.506  ; 8.506  ;        ;
; ASn          ; RAM_RAS1n     ; 8.473  ;        ;        ; 8.473  ;
; ASn          ; ROM0n         ; 7.539  ;        ;        ; 7.539  ;
; ASn          ; ROM1n         ; 7.164  ;        ;        ; 7.164  ;
; ASn          ; ROM2n         ; 6.979  ;        ;        ; 6.979  ;
; ASn          ; ROM3n         ; 7.139  ;        ;        ; 7.139  ;
; ASn          ; ROM4n         ; 7.033  ;        ;        ; 7.033  ;
; ASn          ; ROM5n         ; 7.847  ;        ;        ; 7.847  ;
; ASn          ; ROM6n         ; 6.847  ;        ;        ; 6.847  ;
; COM_CTS      ; DATA[2]       ;        ; 9.271  ; 9.271  ;        ;
; COM_CTS      ; DATA[10]      ;        ; 10.282 ; 10.282 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 10.400 ; 10.400 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 10.561 ; 10.561 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.959  ; 9.959  ;        ;
; COM_DCD      ; DATA[9]       ;        ; 9.885  ; 9.885  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.672 ; 10.672 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.769 ; 10.769 ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.078  ; 9.078  ;        ;
; COM_RI       ; DATA[14]      ; 10.954 ; 10.954 ; 10.954 ; 10.954 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.654 ; 10.654 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 11.042 ; 11.042 ; 11.042 ; 11.042 ;
; CONFIG[1]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[1]    ; DATA[15]      ; 11.202 ; 11.202 ; 11.202 ; 11.202 ;
; CONFIG[1]    ; HSYNC         ; 7.120  ; 7.120  ; 7.120  ; 7.120  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.914 ; 11.914 ; 11.914 ; 11.914 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 8.370  ; 8.502  ; 8.502  ; 8.370  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 8.464  ; 8.464  ; 8.464  ; 8.464  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.069  ; 8.184  ; 8.184  ; 8.069  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 8.179  ; 8.190  ; 8.190  ; 8.179  ;
; CONFIG[1]    ; VSYNC         ; 7.191  ; 7.191  ; 7.191  ; 7.191  ;
; CONFIG[2]    ; DATA[7]       ; 10.170 ; 10.170 ; 10.170 ; 10.170 ;
; CONFIG[2]    ; DATA[15]      ; 11.194 ; 11.194 ; 11.194 ; 11.194 ;
; CONFIG[2]    ; HSYNC         ; 7.114  ; 7.114  ; 7.114  ; 7.114  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.906 ; 11.906 ; 11.906 ; 11.906 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 8.490  ; 8.358  ; 8.358  ; 8.490  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.452  ; 8.452  ; 8.452  ; 8.452  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.172  ; 8.057  ; 8.057  ; 8.172  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 8.178  ; 8.167  ; 8.167  ; 8.178  ;
; CONFIG[2]    ; VSYNC         ; 7.182  ; 7.182  ; 7.182  ; 7.182  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.113  ; 8.113  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.229  ; 7.229  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 12.513 ; 12.513 ; 12.513 ; 12.513 ;
; CONFIG[5]    ; ACSI_WRn      ; 13.142 ; 13.142 ; 13.142 ; 13.142 ;
; CONFIG[5]    ; BUTTONn       ; 11.244 ; 11.129 ; 11.129 ; 11.244 ;
; CONFIG[5]    ; CA1_OUT       ; 13.181 ; 13.066 ; 13.066 ; 13.181 ;
; CONFIG[5]    ; CD[0]         ; 13.391 ; 13.391 ; 13.391 ; 13.391 ;
; CONFIG[5]    ; CD[1]         ; 13.274 ; 13.274 ; 13.274 ; 13.274 ;
; CONFIG[5]    ; CD[2]         ; 12.874 ; 12.916 ; 12.916 ; 12.874 ;
; CONFIG[5]    ; CD[3]         ; 13.274 ; 13.274 ; 13.274 ; 13.274 ;
; CONFIG[5]    ; CD[4]         ; 13.034 ; 13.034 ; 13.034 ; 13.034 ;
; CONFIG[5]    ; CD[5]         ; 13.243 ; 13.243 ; 13.243 ; 13.243 ;
; CONFIG[5]    ; CD[6]         ; 13.202 ; 13.202 ; 13.202 ; 13.202 ;
; CONFIG[5]    ; CD[7]         ; 12.722 ; 12.722 ; 12.722 ; 12.722 ;
; CONFIG[5]    ; DATA[0]       ; 10.915 ; 10.915 ; 10.915 ; 10.915 ;
; CONFIG[5]    ; DATA[1]       ; 10.915 ; 10.915 ; 10.915 ; 10.915 ;
; CONFIG[5]    ; DATA[2]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[3]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[4]       ; 10.769 ; 10.769 ; 10.769 ; 10.769 ;
; CONFIG[5]    ; DATA[5]       ; 10.769 ; 10.769 ; 10.769 ; 10.769 ;
; CONFIG[5]    ; DATA[6]       ; 10.624 ; 10.624 ; 10.624 ; 10.624 ;
; CONFIG[5]    ; DATA[7]       ; 10.614 ; 10.614 ; 10.614 ; 10.614 ;
; CONFIG[5]    ; DATA[8]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[9]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[10]      ; 10.913 ; 10.913 ; 10.913 ; 10.913 ;
; CONFIG[5]    ; DATA[11]      ; 10.913 ; 10.913 ; 10.913 ; 10.913 ;
; CONFIG[5]    ; DATA[12]      ; 10.955 ; 10.955 ; 10.955 ; 10.955 ;
; CONFIG[5]    ; DATA[13]      ; 10.955 ; 10.955 ; 10.955 ; 10.955 ;
; CONFIG[5]    ; DATA[14]      ; 10.961 ; 10.961 ; 10.961 ; 10.961 ;
; CONFIG[5]    ; DATA[15]      ; 10.951 ; 10.951 ; 10.951 ; 10.951 ;
; CONFIG[5]    ; DTACKn        ; 11.294 ; 11.294 ; 11.294 ; 11.294 ;
; CONFIG[5]    ; FLASH_CEn     ; 9.604  ; 9.719  ; 9.719  ; 9.604  ;
; CONFIG[5]    ; FLASH_OEn     ; 9.813  ; 9.928  ; 9.928  ; 9.813  ;
; CONFIG[5]    ; IDE_CS0n      ; 10.620 ; 10.471 ; 10.471 ; 10.620 ;
; CONFIG[5]    ; IDE_CS1n      ; 10.316 ; 10.167 ; 10.167 ; 10.316 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 10.566 ; 10.417 ; 10.417 ; 10.566 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 10.397 ; 10.248 ; 10.248 ; 10.397 ;
; CONFIG[5]    ; IDE_IORDn     ; 10.322 ; 10.173 ; 10.173 ; 10.322 ;
; CONFIG[5]    ; IDE_IOWRn     ; 10.810 ; 10.661 ; 10.661 ; 10.810 ;
; CONFIG[5]    ; JOY_RHn       ; 11.549 ; 11.434 ; 11.434 ; 11.549 ;
; CONFIG[5]    ; JOY_RLn       ; 11.123 ; 11.008 ; 11.008 ; 11.123 ;
; CONFIG[5]    ; JOY_WEn       ; 11.090 ; 11.205 ; 11.205 ; 11.090 ;
; CONFIG[5]    ; JOY_WL        ; 11.475 ; 11.590 ; 11.590 ; 11.475 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 10.896 ; 10.008 ; 10.008 ; 10.896 ;
; CONFIG[5]    ; RAM_BA[0]     ; 10.092 ; 9.204  ; 9.204  ; 10.092 ;
; CONFIG[5]    ; RAM_BA[1]     ; 9.434  ; 8.680  ; 8.680  ; 9.434  ;
; CONFIG[5]    ; RAM_CAS0n     ; 10.662 ; 10.146 ; 10.146 ; 10.662 ;
; CONFIG[5]    ; RAM_CAS1n     ; 9.560  ; 10.105 ; 10.105 ; 9.560  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 12.226 ; 12.186 ; 12.186 ; 12.226 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 12.295 ; 12.255 ; 12.255 ; 12.295 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 12.361 ; 12.510 ; 12.510 ; 12.361 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 12.591 ; 12.551 ; 12.551 ; 12.591 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 12.570 ; 12.530 ; 12.530 ; 12.570 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 12.430 ; 12.430 ; 12.430 ; 12.430 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 12.777 ; 12.777 ; 12.777 ; 12.777 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 12.647 ; 12.687 ; 12.687 ; 12.647 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 13.178 ; 13.099 ; 13.099 ; 13.178 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 12.757 ; 12.717 ; 12.717 ; 12.757 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 12.184 ; 12.224 ; 12.224 ; 12.184 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 12.339 ; 12.379 ; 12.379 ; 12.339 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 12.428 ; 12.428 ; 12.428 ; 12.428 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 12.213 ; 12.253 ; 12.253 ; 12.213 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 11.950 ; 11.950 ; 11.950 ; 11.950 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 11.912 ; 11.912 ; 11.912 ; 11.912 ;
; CONFIG[5]    ; RAM_DQM0H     ; 10.248 ; 9.732  ; 9.732  ; 10.248 ;
; CONFIG[5]    ; RAM_DQM0L     ; 10.341 ; 9.825  ; 9.825  ; 10.341 ;
; CONFIG[5]    ; RAM_DQM1H     ; 9.795  ; 10.340 ; 10.340 ; 9.795  ;
; CONFIG[5]    ; RAM_DQM1L     ; 9.624  ; 10.169 ; 10.169 ; 9.624  ;
; CONFIG[5]    ; RAM_RAS0n     ; 10.645 ; 10.101 ; 10.101 ; 10.645 ;
; CONFIG[5]    ; RAM_RAS1n     ; 10.068 ; 10.612 ; 10.612 ; 10.068 ;
; CONFIG[5]    ; ROM0n         ; 9.092  ; 8.977  ; 8.977  ; 9.092  ;
; CONFIG[5]    ; ROM1n         ; 9.369  ; 9.254  ; 9.254  ; 9.369  ;
; CONFIG[5]    ; ROM2n         ; 9.323  ; 9.438  ; 9.438  ; 9.323  ;
; CONFIG[5]    ; ROM3n         ; 9.563  ; 9.448  ; 9.448  ; 9.563  ;
; CONFIG[5]    ; ROM4n         ; 9.303  ; 9.347  ; 9.347  ; 9.303  ;
; CONFIG[5]    ; ROM5n         ; 9.372  ; 9.372  ; 9.372  ; 9.372  ;
; CONFIG[5]    ; ROM6n         ; 9.276  ; 9.161  ; 9.161  ; 9.276  ;
; CONFIG[6]    ; DATA[0]       ; 10.733 ; 10.733 ; 10.733 ; 10.733 ;
; CONFIG[6]    ; DATA[1]       ; 11.321 ; 11.321 ; 11.321 ; 11.321 ;
; CONFIG[6]    ; DATA[2]       ; 10.881 ; 10.881 ; 10.881 ; 10.881 ;
; CONFIG[6]    ; DATA[3]       ; 11.258 ; 11.258 ; 11.258 ; 11.258 ;
; CONFIG[6]    ; DATA[4]       ; 10.986 ; 10.986 ; 10.986 ; 10.986 ;
; CONFIG[6]    ; DATA[5]       ; 10.990 ; 10.990 ; 10.990 ; 10.990 ;
; CONFIG[6]    ; DATA[6]       ; 10.643 ; 10.643 ; 10.643 ; 10.643 ;
; CONFIG[6]    ; DATA[7]       ; 10.812 ; 10.812 ; 10.812 ; 10.812 ;
; CONFIG[6]    ; DATA[8]       ; 11.288 ; 11.376 ; 11.376 ; 11.288 ;
; CONFIG[6]    ; DATA[9]       ; 11.253 ; 11.253 ; 11.253 ; 11.253 ;
; CONFIG[6]    ; DATA[10]      ; 11.866 ; 12.046 ; 12.046 ; 11.866 ;
; CONFIG[6]    ; DATA[11]      ; 11.562 ; 11.610 ; 11.610 ; 11.562 ;
; CONFIG[6]    ; DATA[12]      ; 11.218 ; 10.994 ; 10.994 ; 11.218 ;
; CONFIG[6]    ; DATA[13]      ; 11.122 ; 11.239 ; 11.239 ; 11.122 ;
; CONFIG[6]    ; DATA[14]      ; 10.988 ; 10.988 ; 10.988 ; 10.988 ;
; CONFIG[6]    ; DATA[15]      ; 10.654 ; 10.654 ; 10.654 ; 10.654 ;
; CONFIG[6]    ; DTACKn        ; 9.405  ; 9.405  ; 9.405  ; 9.405  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.351  ; 7.351  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 6.944  ; 6.944  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 7.995  ; 7.715  ; 7.715  ; 7.995  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.204  ; 7.924  ; 7.924  ; 8.204  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.681 ; 11.681 ; 11.681 ; 11.681 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 12.034 ; 12.034 ; 12.034 ; 12.034 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 12.010 ; 12.010 ; 12.010 ; 12.010 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 12.190 ; 12.190 ; 12.190 ; 12.190 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 12.221 ; 12.221 ; 12.221 ; 12.221 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 11.930 ; 11.930 ; 11.930 ; 11.930 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 12.219 ; 12.219 ; 12.219 ; 12.219 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 12.548 ; 12.548 ; 12.548 ; 12.548 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 12.333 ; 12.421 ; 12.421 ; 12.333 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 12.137 ; 12.137 ; 12.137 ; 12.137 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 12.145 ; 12.325 ; 12.325 ; 12.145 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 12.062 ; 12.110 ; 12.110 ; 12.062 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 11.879 ; 11.655 ; 11.655 ; 11.879 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 11.576 ; 11.693 ; 11.693 ; 11.576 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 11.076 ; 11.076 ; 11.076 ; 11.076 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.905 ; 10.905 ; 10.905 ; 10.905 ;
; CONFIG[6]    ; ROM2n         ; 7.714  ; 7.434  ; 7.434  ; 7.714  ;
; CRT_PIN3     ; DATA[7]       ; 7.463  ; 7.463  ; 7.463  ; 7.463  ;
; CRT_PIN3     ; DATA[15]      ; 8.487  ; 8.487  ; 8.487  ; 8.487  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.199  ; 9.199  ; 9.199  ; 9.199  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.829  ; 5.961  ; 5.961  ; 5.829  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.923  ; 5.923  ; 5.923  ; 5.923  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.528  ; 5.643  ; 5.643  ; 5.528  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 5.638  ; 5.649  ; 5.649  ; 5.638  ;
; DATA[0]      ; DATA[0]       ; 7.528  ;        ;        ; 7.528  ;
; DATA[0]      ; RAM_DATA[0]   ; 8.476  ;        ;        ; 8.476  ;
; DATA[1]      ; DATA[1]       ; 7.334  ;        ;        ; 7.334  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.047  ;        ;        ; 8.047  ;
; DATA[2]      ; DATA[2]       ; 6.949  ;        ;        ; 6.949  ;
; DATA[2]      ; RAM_DATA[2]   ; 8.078  ;        ;        ; 8.078  ;
; DATA[3]      ; DATA[3]       ; 6.857  ;        ;        ; 6.857  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.789  ;        ;        ; 7.789  ;
; DATA[4]      ; DATA[4]       ; 7.492  ;        ;        ; 7.492  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.727  ;        ;        ; 8.727  ;
; DATA[5]      ; DATA[5]       ; 7.742  ;        ;        ; 7.742  ;
; DATA[5]      ; RAM_DATA[5]   ; 8.682  ;        ;        ; 8.682  ;
; DATA[6]      ; DATA[6]       ; 6.534  ;        ;        ; 6.534  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.110  ;        ;        ; 8.110  ;
; DATA[7]      ; DATA[7]       ; 6.472  ;        ;        ; 6.472  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.208  ;        ;        ; 8.208  ;
; DATA[8]      ; DATA[8]       ; 7.874  ;        ;        ; 7.874  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.919  ;        ;        ; 8.919  ;
; DATA[9]      ; DATA[9]       ; 7.217  ;        ;        ; 7.217  ;
; DATA[9]      ; RAM_DATA[9]   ; 8.101  ;        ;        ; 8.101  ;
; DATA[10]     ; DATA[10]      ; 7.572  ;        ;        ; 7.572  ;
; DATA[10]     ; RAM_DATA[10]  ; 7.851  ;        ;        ; 7.851  ;
; DATA[11]     ; DATA[11]      ; 7.385  ;        ;        ; 7.385  ;
; DATA[11]     ; RAM_DATA[11]  ; 7.885  ;        ;        ; 7.885  ;
; DATA[12]     ; DATA[12]      ; 7.060  ;        ;        ; 7.060  ;
; DATA[12]     ; RAM_DATA[12]  ; 7.721  ;        ;        ; 7.721  ;
; DATA[13]     ; DATA[13]      ; 7.172  ;        ;        ; 7.172  ;
; DATA[13]     ; RAM_DATA[13]  ; 7.626  ;        ;        ; 7.626  ;
; DATA[14]     ; DATA[14]      ; 7.487  ;        ;        ; 7.487  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.575  ;        ;        ; 7.575  ;
; DATA[15]     ; DATA[15]      ; 7.161  ;        ;        ; 7.161  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.412  ;        ;        ; 7.412  ;
; FC[0]        ; ACSI_RDn      ; 8.497  ; 8.497  ; 8.497  ; 8.497  ;
; FC[0]        ; ACSI_WRn      ; 9.126  ; 9.126  ; 9.126  ; 9.126  ;
; FC[0]        ; BUTTONn       ; 8.110  ; 8.110  ; 8.110  ; 8.110  ;
; FC[0]        ; CA1_OUT       ; 9.050  ; 9.050  ; 9.050  ; 9.050  ;
; FC[0]        ; CD[0]         ; 9.375  ; 9.375  ; 9.375  ; 9.375  ;
; FC[0]        ; CD[1]         ; 9.258  ; 9.258  ; 9.258  ; 9.258  ;
; FC[0]        ; CD[2]         ; 8.858  ; 8.858  ; 8.858  ; 8.858  ;
; FC[0]        ; CD[3]         ; 9.258  ; 9.258  ; 9.258  ; 9.258  ;
; FC[0]        ; CD[4]         ; 9.018  ; 9.018  ; 9.018  ; 9.018  ;
; FC[0]        ; CD[5]         ; 9.227  ; 9.227  ; 9.227  ; 9.227  ;
; FC[0]        ; CD[6]         ; 9.186  ; 9.186  ; 9.186  ; 9.186  ;
; FC[0]        ; CD[7]         ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; FC[0]        ; DATA[0]       ; 8.883  ; 8.883  ; 8.883  ; 8.883  ;
; FC[0]        ; DATA[1]       ; 8.944  ; 8.944  ; 8.944  ; 8.944  ;
; FC[0]        ; DATA[2]       ; 8.413  ; 8.413  ; 8.413  ; 8.413  ;
; FC[0]        ; DATA[3]       ; 8.515  ; 8.515  ; 8.515  ; 8.515  ;
; FC[0]        ; DATA[4]       ; 8.468  ; 8.468  ; 8.468  ; 8.468  ;
; FC[0]        ; DATA[5]       ; 8.797  ; 8.797  ; 8.797  ; 8.797  ;
; FC[0]        ; DATA[6]       ; 8.258  ; 8.258  ; 8.258  ; 8.258  ;
; FC[0]        ; DATA[7]       ; 8.361  ; 8.361  ; 8.361  ; 8.361  ;
; FC[0]        ; DATA[8]       ; 9.370  ; 9.370  ; 9.370  ; 9.370  ;
; FC[0]        ; DATA[9]       ; 9.132  ; 9.132  ; 9.132  ; 9.132  ;
; FC[0]        ; DATA[10]      ; 9.476  ; 9.476  ; 9.476  ; 9.476  ;
; FC[0]        ; DATA[11]      ; 9.169  ; 9.169  ; 9.169  ; 9.169  ;
; FC[0]        ; DATA[12]      ; 8.890  ; 8.890  ; 8.890  ; 8.890  ;
; FC[0]        ; DATA[13]      ; 9.006  ; 9.006  ; 9.006  ; 9.006  ;
; FC[0]        ; DATA[14]      ; 9.588  ; 9.588  ; 9.588  ; 9.588  ;
; FC[0]        ; DATA[15]      ; 9.261  ; 9.261  ; 9.261  ; 9.261  ;
; FC[0]        ; DTACKn        ; 7.938  ; 7.938  ; 7.938  ; 7.938  ;
; FC[0]        ; FLASH_CEn     ; 7.851  ; 7.851  ; 7.851  ; 7.851  ;
; FC[0]        ; FLASH_OEn     ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; FC[0]        ; JOY_RHn       ; 8.992  ; 8.992  ; 8.992  ; 8.992  ;
; FC[0]        ; JOY_RLn       ; 8.663  ; 8.663  ; 8.663  ; 8.663  ;
; FC[0]        ; JOY_WEn       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; FC[0]        ; JOY_WL        ; 7.882  ; 7.882  ; 7.882  ; 7.882  ;
; FC[0]        ; RAM_ADR[8]    ; 9.001  ; 9.001  ; 9.001  ; 9.001  ;
; FC[0]        ; RAM_BA[0]     ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; FC[0]        ; RAM_BA[1]     ; 7.673  ; 7.673  ; 7.673  ; 7.673  ;
; FC[0]        ; RAM_CAS0n     ; 9.139  ; 9.139  ; 9.139  ; 9.139  ;
; FC[0]        ; RAM_CAS1n     ; 8.553  ; 8.553  ; 8.553  ; 8.553  ;
; FC[0]        ; RAM_DATA[0]   ; 9.831  ; 9.831  ; 9.831  ; 9.831  ;
; FC[0]        ; RAM_DATA[1]   ; 9.657  ; 9.657  ; 9.657  ; 9.657  ;
; FC[0]        ; RAM_DATA[2]   ; 9.542  ; 9.542  ; 9.542  ; 9.542  ;
; FC[0]        ; RAM_DATA[3]   ; 9.447  ; 9.447  ; 9.447  ; 9.447  ;
; FC[0]        ; RAM_DATA[4]   ; 9.703  ; 9.703  ; 9.703  ; 9.703  ;
; FC[0]        ; RAM_DATA[5]   ; 9.737  ; 9.737  ; 9.737  ; 9.737  ;
; FC[0]        ; RAM_DATA[6]   ; 9.834  ; 9.834  ; 9.834  ; 9.834  ;
; FC[0]        ; RAM_DATA[7]   ; 10.097 ; 10.097 ; 10.097 ; 10.097 ;
; FC[0]        ; RAM_DATA[8]   ; 10.415 ; 10.415 ; 10.415 ; 10.415 ;
; FC[0]        ; RAM_DATA[9]   ; 10.016 ; 10.016 ; 10.016 ; 10.016 ;
; FC[0]        ; RAM_DATA[10]  ; 9.755  ; 9.755  ; 9.755  ; 9.755  ;
; FC[0]        ; RAM_DATA[11]  ; 9.669  ; 9.669  ; 9.669  ; 9.669  ;
; FC[0]        ; RAM_DATA[12]  ; 9.551  ; 9.551  ; 9.551  ; 9.551  ;
; FC[0]        ; RAM_DATA[13]  ; 9.460  ; 9.460  ; 9.460  ; 9.460  ;
; FC[0]        ; RAM_DATA[14]  ; 9.676  ; 9.676  ; 9.676  ; 9.676  ;
; FC[0]        ; RAM_DATA[15]  ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[0]        ; RAM_DQM0H     ; 8.725  ; 8.725  ; 8.725  ; 8.725  ;
; FC[0]        ; RAM_DQM0L     ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; FC[0]        ; RAM_DQM1H     ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; FC[0]        ; RAM_DQM1L     ; 8.617  ; 8.617  ; 8.617  ; 8.617  ;
; FC[0]        ; RAM_RAS0n     ; 9.094  ; 9.094  ; 9.094  ; 9.094  ;
; FC[0]        ; RAM_RAS1n     ; 9.061  ; 9.061  ; 9.061  ; 9.061  ;
; FC[0]        ; ROM0n         ; 7.329  ; 7.329  ; 7.329  ; 7.329  ;
; FC[0]        ; ROM1n         ; 6.954  ; 6.954  ; 6.954  ; 6.954  ;
; FC[0]        ; ROM2n         ; 7.570  ; 7.570  ; 7.570  ; 7.570  ;
; FC[0]        ; ROM3n         ; 6.929  ; 6.929  ; 6.929  ; 6.929  ;
; FC[0]        ; ROM4n         ; 6.823  ; 6.823  ; 6.823  ; 6.823  ;
; FC[0]        ; ROM5n         ; 7.637  ; 7.637  ; 7.637  ; 7.637  ;
; FC[0]        ; ROM6n         ; 6.637  ; 6.637  ; 6.637  ; 6.637  ;
; FC[1]        ; ACSI_RDn      ; 8.303  ; 8.303  ; 8.303  ; 8.303  ;
; FC[1]        ; ACSI_WRn      ; 8.932  ; 8.932  ; 8.932  ; 8.932  ;
; FC[1]        ; BUTTONn       ; 8.100  ; 8.100  ; 8.100  ; 8.100  ;
; FC[1]        ; CA1_OUT       ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; FC[1]        ; CD[0]         ; 9.181  ; 9.181  ; 9.181  ; 9.181  ;
; FC[1]        ; CD[1]         ; 9.064  ; 9.064  ; 9.064  ; 9.064  ;
; FC[1]        ; CD[2]         ; 8.664  ; 8.664  ; 8.664  ; 8.664  ;
; FC[1]        ; CD[3]         ; 9.064  ; 9.064  ; 9.064  ; 9.064  ;
; FC[1]        ; CD[4]         ; 8.824  ; 8.824  ; 8.824  ; 8.824  ;
; FC[1]        ; CD[5]         ; 9.033  ; 9.033  ; 9.033  ; 9.033  ;
; FC[1]        ; CD[6]         ; 8.992  ; 8.992  ; 8.992  ; 8.992  ;
; FC[1]        ; CD[7]         ; 8.512  ; 8.512  ; 8.512  ; 8.512  ;
; FC[1]        ; DATA[0]       ; 8.689  ; 8.689  ; 8.689  ; 8.689  ;
; FC[1]        ; DATA[1]       ; 8.750  ; 8.750  ; 8.750  ; 8.750  ;
; FC[1]        ; DATA[2]       ; 8.219  ; 8.219  ; 8.219  ; 8.219  ;
; FC[1]        ; DATA[3]       ; 8.321  ; 8.321  ; 8.321  ; 8.321  ;
; FC[1]        ; DATA[4]       ; 8.274  ; 8.274  ; 8.274  ; 8.274  ;
; FC[1]        ; DATA[5]       ; 8.603  ; 8.603  ; 8.603  ; 8.603  ;
; FC[1]        ; DATA[6]       ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; FC[1]        ; DATA[7]       ; 8.167  ; 8.167  ; 8.167  ; 8.167  ;
; FC[1]        ; DATA[8]       ; 9.176  ; 9.176  ; 9.176  ; 9.176  ;
; FC[1]        ; DATA[9]       ; 8.938  ; 8.938  ; 8.938  ; 8.938  ;
; FC[1]        ; DATA[10]      ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; FC[1]        ; DATA[11]      ; 8.975  ; 8.975  ; 8.975  ; 8.975  ;
; FC[1]        ; DATA[12]      ; 8.696  ; 8.696  ; 8.696  ; 8.696  ;
; FC[1]        ; DATA[13]      ; 8.812  ; 8.812  ; 8.812  ; 8.812  ;
; FC[1]        ; DATA[14]      ; 9.394  ; 9.394  ; 9.394  ; 9.394  ;
; FC[1]        ; DATA[15]      ; 9.067  ; 9.067  ; 9.067  ; 9.067  ;
; FC[1]        ; DTACKn        ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; FC[1]        ; FLASH_CEn     ; 7.841  ; 7.841  ; 7.841  ; 7.841  ;
; FC[1]        ; FLASH_OEn     ; 8.050  ; 8.050  ; 8.050  ; 8.050  ;
; FC[1]        ; JOY_RHn       ; 8.798  ; 8.798  ; 8.798  ; 8.798  ;
; FC[1]        ; JOY_RLn       ; 8.469  ; 8.469  ; 8.469  ; 8.469  ;
; FC[1]        ; JOY_WEn       ; 8.551  ; 8.551  ; 8.551  ; 8.551  ;
; FC[1]        ; JOY_WL        ; 7.688  ; 7.688  ; 7.688  ; 7.688  ;
; FC[1]        ; RAM_ADR[8]    ; 8.991  ; 8.991  ; 8.991  ; 8.991  ;
; FC[1]        ; RAM_BA[0]     ; 8.187  ; 8.187  ; 8.187  ; 8.187  ;
; FC[1]        ; RAM_BA[1]     ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; FC[1]        ; RAM_CAS0n     ; 9.129  ; 9.129  ; 9.129  ; 9.129  ;
; FC[1]        ; RAM_CAS1n     ; 8.543  ; 8.543  ; 8.543  ; 8.543  ;
; FC[1]        ; RAM_DATA[0]   ; 9.637  ; 9.637  ; 9.637  ; 9.637  ;
; FC[1]        ; RAM_DATA[1]   ; 9.463  ; 9.463  ; 9.463  ; 9.463  ;
; FC[1]        ; RAM_DATA[2]   ; 9.348  ; 9.348  ; 9.348  ; 9.348  ;
; FC[1]        ; RAM_DATA[3]   ; 9.253  ; 9.253  ; 9.253  ; 9.253  ;
; FC[1]        ; RAM_DATA[4]   ; 9.509  ; 9.509  ; 9.509  ; 9.509  ;
; FC[1]        ; RAM_DATA[5]   ; 9.543  ; 9.543  ; 9.543  ; 9.543  ;
; FC[1]        ; RAM_DATA[6]   ; 9.640  ; 9.640  ; 9.640  ; 9.640  ;
; FC[1]        ; RAM_DATA[7]   ; 9.903  ; 9.903  ; 9.903  ; 9.903  ;
; FC[1]        ; RAM_DATA[8]   ; 10.221 ; 10.221 ; 10.221 ; 10.221 ;
; FC[1]        ; RAM_DATA[9]   ; 9.822  ; 9.822  ; 9.822  ; 9.822  ;
; FC[1]        ; RAM_DATA[10]  ; 9.561  ; 9.561  ; 9.561  ; 9.561  ;
; FC[1]        ; RAM_DATA[11]  ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[1]        ; RAM_DATA[12]  ; 9.357  ; 9.357  ; 9.357  ; 9.357  ;
; FC[1]        ; RAM_DATA[13]  ; 9.266  ; 9.266  ; 9.266  ; 9.266  ;
; FC[1]        ; RAM_DATA[14]  ; 9.482  ; 9.482  ; 9.482  ; 9.482  ;
; FC[1]        ; RAM_DATA[15]  ; 9.318  ; 9.318  ; 9.318  ; 9.318  ;
; FC[1]        ; RAM_DQM0H     ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; FC[1]        ; RAM_DQM0L     ; 8.808  ; 8.808  ; 8.808  ; 8.808  ;
; FC[1]        ; RAM_DQM1H     ; 8.778  ; 8.778  ; 8.778  ; 8.778  ;
; FC[1]        ; RAM_DQM1L     ; 8.607  ; 8.607  ; 8.607  ; 8.607  ;
; FC[1]        ; RAM_RAS0n     ; 9.084  ; 9.084  ; 9.084  ; 9.084  ;
; FC[1]        ; RAM_RAS1n     ; 9.051  ; 9.051  ; 9.051  ; 9.051  ;
; FC[1]        ; ROM0n         ; 7.319  ; 7.319  ; 7.319  ; 7.319  ;
; FC[1]        ; ROM1n         ; 6.944  ; 6.944  ; 6.944  ; 6.944  ;
; FC[1]        ; ROM2n         ; 7.560  ; 7.560  ; 7.560  ; 7.560  ;
; FC[1]        ; ROM3n         ; 6.919  ; 6.919  ; 6.919  ; 6.919  ;
; FC[1]        ; ROM4n         ; 6.813  ; 6.813  ; 6.813  ; 6.813  ;
; FC[1]        ; ROM5n         ; 7.627  ; 7.627  ; 7.627  ; 7.627  ;
; FC[1]        ; ROM6n         ; 6.627  ; 6.627  ; 6.627  ; 6.627  ;
; FC[2]        ; ACSI_RDn      ; 8.393  ; 8.393  ; 8.393  ; 8.393  ;
; FC[2]        ; ACSI_WRn      ; 9.022  ; 9.022  ; 9.022  ; 9.022  ;
; FC[2]        ; CA1_OUT       ;        ; 8.946  ; 8.946  ;        ;
; FC[2]        ; CD[0]         ; 9.271  ; 9.271  ; 9.271  ; 9.271  ;
; FC[2]        ; CD[1]         ; 9.154  ; 9.154  ; 9.154  ; 9.154  ;
; FC[2]        ; CD[2]         ; 8.754  ; 8.796  ; 8.796  ; 8.754  ;
; FC[2]        ; CD[3]         ; 9.154  ; 9.154  ; 9.154  ; 9.154  ;
; FC[2]        ; CD[4]         ; 8.914  ; 8.914  ; 8.914  ; 8.914  ;
; FC[2]        ; CD[5]         ; 9.123  ; 9.123  ; 9.123  ; 9.123  ;
; FC[2]        ; CD[6]         ; 9.082  ; 9.082  ; 9.082  ; 9.082  ;
; FC[2]        ; CD[7]         ; 8.602  ; 8.602  ; 8.602  ; 8.602  ;
; FC[2]        ; DATA[0]       ; 8.960  ; 8.846  ; 8.846  ; 8.960  ;
; FC[2]        ; DATA[1]       ; 8.958  ; 8.907  ; 8.907  ; 8.958  ;
; FC[2]        ; DATA[2]       ; 8.792  ; 8.792  ; 8.792  ; 8.792  ;
; FC[2]        ; DATA[3]       ; 9.406  ; 8.905  ; 8.905  ; 9.406  ;
; FC[2]        ; DATA[4]       ; 8.949  ; 8.638  ; 8.638  ; 8.949  ;
; FC[2]        ; DATA[5]       ; 9.288  ; 9.077  ; 9.077  ; 9.288  ;
; FC[2]        ; DATA[6]       ; 8.777  ; 8.648  ; 8.648  ; 8.777  ;
; FC[2]        ; DATA[7]       ; 8.922  ; 8.581  ; 8.581  ; 8.922  ;
; FC[2]        ; DATA[8]       ; 10.649 ; 9.436  ; 9.436  ; 10.649 ;
; FC[2]        ; DATA[9]       ; 10.287 ; 9.176  ; 9.176  ; 10.287 ;
; FC[2]        ; DATA[10]      ; 10.548 ; 9.798  ; 9.798  ; 10.548 ;
; FC[2]        ; DATA[11]      ; 10.513 ; 9.525  ; 9.525  ; 10.513 ;
; FC[2]        ; DATA[12]      ; 10.011 ; 9.345  ; 9.345  ; 10.011 ;
; FC[2]        ; DATA[13]      ; 10.131 ; 9.457  ; 9.457  ; 10.131 ;
; FC[2]        ; DATA[14]      ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[2]        ; DATA[15]      ; 9.526  ; 9.526  ; 9.526  ; 9.526  ;
; FC[2]        ; DTACKn        ; 7.834  ; 7.834  ; 7.834  ; 7.834  ;
; FC[2]        ; JOY_RHn       ;        ; 8.888  ; 8.888  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.559  ; 8.559  ;        ;
; FC[2]        ; JOY_WEn       ; 8.641  ;        ;        ; 8.641  ;
; FC[2]        ; JOY_WL        ; 7.778  ;        ;        ; 7.778  ;
; FC[2]        ; RAM_DATA[0]   ; 9.908  ; 9.794  ; 9.794  ; 9.908  ;
; FC[2]        ; RAM_DATA[1]   ; 9.671  ; 9.620  ; 9.620  ; 9.671  ;
; FC[2]        ; RAM_DATA[2]   ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; FC[2]        ; RAM_DATA[3]   ; 10.338 ; 9.837  ; 9.837  ; 10.338 ;
; FC[2]        ; RAM_DATA[4]   ; 10.184 ; 9.873  ; 9.873  ; 10.184 ;
; FC[2]        ; RAM_DATA[5]   ; 10.228 ; 10.017 ; 10.017 ; 10.228 ;
; FC[2]        ; RAM_DATA[6]   ; 10.353 ; 10.224 ; 10.224 ; 10.353 ;
; FC[2]        ; RAM_DATA[7]   ; 10.658 ; 10.317 ; 10.317 ; 10.658 ;
; FC[2]        ; RAM_DATA[8]   ; 11.694 ; 10.481 ; 10.481 ; 11.694 ;
; FC[2]        ; RAM_DATA[9]   ; 11.171 ; 10.060 ; 10.060 ; 11.171 ;
; FC[2]        ; RAM_DATA[10]  ; 10.827 ; 10.077 ; 10.077 ; 10.827 ;
; FC[2]        ; RAM_DATA[11]  ; 11.013 ; 10.025 ; 10.025 ; 11.013 ;
; FC[2]        ; RAM_DATA[12]  ; 10.672 ; 10.006 ; 10.006 ; 10.672 ;
; FC[2]        ; RAM_DATA[13]  ; 10.585 ; 9.911  ; 9.911  ; 10.585 ;
; FC[2]        ; RAM_DATA[14]  ; 9.798  ; 9.798  ; 9.798  ; 9.798  ;
; FC[2]        ; RAM_DATA[15]  ; 9.777  ; 9.777  ; 9.777  ; 9.777  ;
; HDINTn       ; DATA[5]       ; 10.555 ;        ;        ; 10.555 ;
; HDINTn       ; DATA[13]      ; 11.038 ;        ;        ; 11.038 ;
; HDINTn       ; RAM_DATA[5]   ; 11.495 ;        ;        ; 11.495 ;
; HDINTn       ; RAM_DATA[13]  ; 11.492 ;        ;        ; 11.492 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.692 ; 10.692 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 11.175 ; 11.175 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.632 ; 11.632 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 11.629 ; 11.629 ;        ;
; IDE_IORDY    ; DTACKn        ; 9.443  ; 9.443  ; 9.443  ; 9.443  ;
; LDSn         ; ACSI_RDn      ; 8.057  ; 8.057  ; 8.057  ; 8.057  ;
; LDSn         ; ACSI_WRn      ; 8.686  ; 8.686  ; 8.686  ; 8.686  ;
; LDSn         ; BUTTONn       ; 7.446  ;        ;        ; 7.446  ;
; LDSn         ; CA1_OUT       ; 8.610  ;        ;        ; 8.610  ;
; LDSn         ; CD[0]         ; 8.935  ; 8.935  ; 8.935  ; 8.935  ;
; LDSn         ; CD[1]         ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; LDSn         ; CD[2]         ; 8.460  ; 8.418  ; 8.418  ; 8.460  ;
; LDSn         ; CD[3]         ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; LDSn         ; CD[4]         ; 8.578  ; 8.578  ; 8.578  ; 8.578  ;
; LDSn         ; CD[5]         ; 8.787  ; 8.787  ; 8.787  ; 8.787  ;
; LDSn         ; CD[6]         ; 8.746  ; 8.746  ; 8.746  ; 8.746  ;
; LDSn         ; CD[7]         ; 8.266  ; 8.266  ; 8.266  ; 8.266  ;
; LDSn         ; DATA[0]       ; 8.423  ; 8.612  ; 8.612  ; 8.423  ;
; LDSn         ; DATA[1]       ; 8.743  ; 8.743  ; 8.743  ; 8.743  ;
; LDSn         ; DATA[2]       ; 8.400  ; 8.174  ; 8.174  ; 8.400  ;
; LDSn         ; DATA[3]       ; 8.648  ; 8.611  ; 8.611  ; 8.648  ;
; LDSn         ; DATA[4]       ; 8.328  ; 8.328  ; 8.328  ; 8.328  ;
; LDSn         ; DATA[5]       ; 8.432  ; 8.432  ; 8.432  ; 8.432  ;
; LDSn         ; DATA[6]       ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; LDSn         ; DATA[7]       ; 8.489  ; 8.294  ; 8.294  ; 8.489  ;
; LDSn         ; DATA[8]       ; 8.652  ; 8.652  ; 8.652  ; 8.652  ;
; LDSn         ; DATA[9]       ; 8.652  ; 8.652  ; 8.652  ; 8.652  ;
; LDSn         ; DATA[10]      ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; LDSn         ; DATA[11]      ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; LDSn         ; DATA[12]      ; 8.709  ; 8.709  ; 8.709  ; 8.709  ;
; LDSn         ; DATA[13]      ; 8.829  ; 8.829  ; 8.829  ; 8.829  ;
; LDSn         ; DATA[14]      ; 8.836  ; 8.836  ; 8.836  ; 8.836  ;
; LDSn         ; DATA[15]      ; 8.826  ; 8.826  ; 8.826  ; 8.826  ;
; LDSn         ; DTACKn        ; 7.621  ; 7.621  ; 7.621  ; 7.621  ;
; LDSn         ; IDE_IORDn     ; 6.538  ;        ;        ; 6.538  ;
; LDSn         ; IDE_IOWRn     ; 7.028  ;        ;        ; 7.028  ;
; LDSn         ; JOY_RLn       ; 7.927  ;        ;        ; 7.927  ;
; LDSn         ; JOY_WEn       ;        ; 8.009  ; 8.009  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.860  ; 6.860  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.850  ;        ;        ; 7.850  ;
; LDSn         ; RAM_CAS1n     ; 7.262  ;        ;        ; 7.262  ;
; LDSn         ; RAM_DATA[0]   ; 9.371  ; 9.560  ; 9.560  ; 9.371  ;
; LDSn         ; RAM_DATA[1]   ; 9.456  ; 9.456  ; 9.456  ; 9.456  ;
; LDSn         ; RAM_DATA[2]   ; 9.529  ; 9.303  ; 9.303  ; 9.529  ;
; LDSn         ; RAM_DATA[3]   ; 9.580  ; 9.543  ; 9.543  ; 9.580  ;
; LDSn         ; RAM_DATA[4]   ; 9.563  ; 9.563  ; 9.563  ; 9.563  ;
; LDSn         ; RAM_DATA[5]   ; 9.372  ; 9.372  ; 9.372  ; 9.372  ;
; LDSn         ; RAM_DATA[6]   ; 9.719  ; 9.719  ; 9.719  ; 9.719  ;
; LDSn         ; RAM_DATA[7]   ; 10.276 ; 10.030 ; 10.030 ; 10.276 ;
; LDSn         ; RAM_DATA[8]   ; 10.041 ; 10.371 ; 10.371 ; 10.041 ;
; LDSn         ; RAM_DATA[9]   ; 9.869  ; 9.869  ; 9.869  ; 9.869  ;
; LDSn         ; RAM_DATA[10]  ; 9.525  ; 9.525  ; 9.525  ; 9.525  ;
; LDSn         ; RAM_DATA[11]  ; 9.565  ; 9.565  ; 9.565  ; 9.565  ;
; LDSn         ; RAM_DATA[12]  ; 9.370  ; 9.370  ; 9.370  ; 9.370  ;
; LDSn         ; RAM_DATA[13]  ; 9.283  ; 9.283  ; 9.283  ; 9.283  ;
; LDSn         ; RAM_DATA[14]  ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; LDSn         ; RAM_DATA[15]  ; 9.438  ; 9.438  ; 9.438  ; 9.438  ;
; LDSn         ; RAM_DQM0L     ; 7.239  ;        ;        ; 7.239  ;
; LDSn         ; RAM_DQM1L     ; 7.044  ;        ;        ; 7.044  ;
; LPT_BSY      ; DATA[0]       ; 10.282 ;        ;        ; 10.282 ;
; LPT_BSY      ; DATA[8]       ; 11.099 ;        ;        ; 11.099 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.230 ;        ;        ; 11.230 ;
; LPT_BSY      ; RAM_DATA[8]   ; 12.144 ;        ;        ; 12.144 ;
; LPT_D[0]     ; DATA[0]       ; 8.799  ;        ;        ; 8.799  ;
; LPT_D[0]     ; DATA[8]       ; 9.505  ;        ;        ; 9.505  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 9.747  ;        ;        ; 9.747  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.550 ;        ;        ; 10.550 ;
; LPT_D[1]     ; DATA[1]       ; 9.348  ;        ;        ; 9.348  ;
; LPT_D[1]     ; DATA[9]       ; 9.415  ;        ;        ; 9.415  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 10.061 ;        ;        ; 10.061 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.299 ;        ;        ; 10.299 ;
; LPT_D[2]     ; DATA[2]       ; 9.111  ;        ;        ; 9.111  ;
; LPT_D[2]     ; DATA[10]      ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 10.240 ;        ;        ; 10.240 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 10.401 ;        ;        ; 10.401 ;
; LPT_D[3]     ; DATA[3]       ; 9.269  ;        ;        ; 9.269  ;
; LPT_D[3]     ; DATA[11]      ; 9.890  ;        ;        ; 9.890  ;
; LPT_D[3]     ; RAM_DATA[3]   ; 10.201 ;        ;        ; 10.201 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 10.390 ;        ;        ; 10.390 ;
; LPT_D[4]     ; DATA[4]       ; 9.991  ;        ;        ; 9.991  ;
; LPT_D[4]     ; DATA[12]      ; 10.465 ;        ;        ; 10.465 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.226 ;        ;        ; 11.226 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 11.126 ;        ;        ; 11.126 ;
; LPT_D[5]     ; DATA[5]       ; 9.074  ;        ;        ; 9.074  ;
; LPT_D[5]     ; DATA[13]      ; 9.802  ;        ;        ; 9.802  ;
; LPT_D[5]     ; RAM_DATA[5]   ; 10.014 ;        ;        ; 10.014 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.256 ;        ;        ; 10.256 ;
; LPT_D[6]     ; DATA[6]       ; 9.006  ;        ;        ; 9.006  ;
; LPT_D[6]     ; DATA[14]      ; 10.251 ; 10.251 ; 10.251 ; 10.251 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 10.582 ;        ;        ; 10.582 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.339 ; 10.339 ; 10.339 ; 10.339 ;
; LPT_D[7]     ; DATA[7]       ; 9.165  ;        ;        ; 9.165  ;
; LPT_D[7]     ; DATA[15]      ; 10.014 ; 10.014 ; 10.014 ; 10.014 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.901 ;        ;        ; 10.901 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; MIDI_IN      ; MIDI_TLR      ; 4.716  ;        ;        ; 4.716  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.865  ;        ;        ; 9.865  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.813 ;        ;        ; 10.813 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.692 ;        ;        ; 10.692 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 11.405 ;        ;        ; 11.405 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.678 ;        ;        ; 10.678 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 11.807 ;        ;        ; 11.807 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.963  ;        ;        ; 9.963  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.895 ;        ;        ; 10.895 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.697  ;        ;        ; 9.697  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.385 ;        ;        ; 10.385 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.325 ;        ;        ; 11.325 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.820  ;        ;        ; 9.820  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.396 ;        ;        ; 11.396 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.099 ;        ;        ; 10.099 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.835 ;        ;        ; 11.835 ;
; RAM_DATA[8]  ; DATA[8]       ; 11.045 ;        ;        ; 11.045 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 12.090 ;        ;        ; 12.090 ;
; RAM_DATA[9]  ; DATA[9]       ; 10.424 ;        ;        ; 10.424 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.308 ;        ;        ; 11.308 ;
; RAM_DATA[10] ; DATA[10]      ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 11.211 ;        ;        ; 11.211 ;
; RAM_DATA[11] ; DATA[11]      ; 10.739 ;        ;        ; 10.739 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 11.239 ;        ;        ; 11.239 ;
; RAM_DATA[12] ; DATA[12]      ; 10.066 ;        ;        ; 10.066 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 10.727 ;        ;        ; 10.727 ;
; RAM_DATA[13] ; DATA[13]      ; 10.635 ;        ;        ; 10.635 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 11.089 ;        ;        ; 11.089 ;
; RAM_DATA[14] ; DATA[14]      ; 10.811 ; 10.811 ; 10.811 ; 10.811 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.899 ; 10.899 ; 10.899 ; 10.899 ;
; RAM_DATA[15] ; DATA[15]      ; 11.044 ; 11.044 ; 11.044 ; 11.044 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 11.295 ; 11.295 ; 11.295 ; 11.295 ;
; RWn          ; ACSI_RDn      ; 8.039  ; 7.063  ; 7.063  ; 8.039  ;
; RWn          ; ACSI_WRn      ; 7.692  ; 8.668  ; 8.668  ; 7.692  ;
; RWn          ; BUTTONn       ;        ; 7.486  ; 7.486  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.592  ; 8.592  ;        ;
; RWn          ; CD[0]         ; 7.780  ; 7.780  ; 7.780  ; 7.780  ;
; RWn          ; CD[1]         ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; RWn          ; CD[2]         ; 7.191  ; 7.149  ; 7.149  ; 7.191  ;
; RWn          ; CD[3]         ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; RWn          ; CD[4]         ; 7.309  ; 7.309  ; 7.309  ; 7.309  ;
; RWn          ; CD[5]         ; 7.518  ; 7.518  ; 7.518  ; 7.518  ;
; RWn          ; CD[6]         ; 7.477  ; 7.477  ; 7.477  ; 7.477  ;
; RWn          ; CD[7]         ; 7.034  ; 7.034  ; 7.034  ; 7.034  ;
; RWn          ; DATA[0]       ; 7.969  ; 7.969  ; 7.969  ; 7.969  ;
; RWn          ; DATA[1]       ; 8.385  ; 8.338  ; 8.338  ; 8.385  ;
; RWn          ; DATA[2]       ; 7.653  ; 7.591  ; 7.591  ; 7.653  ;
; RWn          ; DATA[3]       ; 8.052  ; 7.693  ; 7.693  ; 8.052  ;
; RWn          ; DATA[4]       ; 7.899  ; 7.646  ; 7.646  ; 7.899  ;
; RWn          ; DATA[5]       ; 8.246  ; 7.975  ; 7.975  ; 8.246  ;
; RWn          ; DATA[6]       ; 7.934  ; 7.436  ; 7.436  ; 7.934  ;
; RWn          ; DATA[7]       ; 7.747  ; 7.539  ; 7.539  ; 7.747  ;
; RWn          ; DATA[8]       ; 8.706  ; 8.548  ; 8.548  ; 8.706  ;
; RWn          ; DATA[9]       ; 8.689  ; 8.310  ; 8.310  ; 8.689  ;
; RWn          ; DATA[10]      ; 8.719  ; 8.654  ; 8.654  ; 8.719  ;
; RWn          ; DATA[11]      ; 8.842  ; 8.347  ; 8.347  ; 8.842  ;
; RWn          ; DATA[12]      ; 8.625  ; 8.277  ; 8.277  ; 8.625  ;
; RWn          ; DATA[13]      ; 8.618  ; 8.393  ; 8.393  ; 8.618  ;
; RWn          ; DATA[14]      ; 8.477  ; 8.477  ; 8.477  ; 8.477  ;
; RWn          ; DATA[15]      ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; RWn          ; DTACKn        ; 7.480  ; 7.480  ; 7.480  ; 7.480  ;
; RWn          ; FLASH_CEn     ;        ; 7.094  ; 7.094  ;        ;
; RWn          ; FLASH_OEn     ;        ; 7.303  ; 7.303  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.192  ; 7.192  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.436  ;        ;        ; 6.436  ;
; RWn          ; IDE_IORDn     ;        ; 6.489  ; 6.489  ;        ;
; RWn          ; IDE_IOWRn     ; 6.977  ;        ;        ; 6.977  ;
; RWn          ; JOY_RHn       ;        ; 7.159  ; 7.159  ;        ;
; RWn          ; JOY_RLn       ;        ; 7.674  ; 7.674  ;        ;
; RWn          ; JOY_WEn       ; 7.756  ;        ;        ; 7.756  ;
; RWn          ; JOY_WL        ; 7.424  ; 6.804  ; 6.804  ; 7.424  ;
; RWn          ; RAM_DATA[0]   ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; RWn          ; RAM_DATA[1]   ; 7.060  ; 7.060  ; 7.060  ; 7.060  ;
; RWn          ; RAM_DATA[2]   ; 7.507  ; 7.507  ; 7.507  ; 7.507  ;
; RWn          ; RAM_DATA[3]   ; 7.326  ; 7.326  ; 7.326  ; 7.326  ;
; RWn          ; RAM_DATA[4]   ; 7.420  ; 7.420  ; 7.420  ; 7.420  ;
; RWn          ; RAM_DATA[5]   ; 7.537  ; 7.537  ; 7.537  ; 7.537  ;
; RWn          ; RAM_DATA[6]   ; 7.585  ; 7.585  ; 7.585  ; 7.585  ;
; RWn          ; RAM_DATA[7]   ; 7.572  ; 7.572  ; 7.572  ; 7.572  ;
; RWn          ; RAM_DATA[8]   ; 7.495  ; 7.495  ; 7.495  ; 7.495  ;
; RWn          ; RAM_DATA[9]   ; 7.541  ; 7.541  ; 7.541  ; 7.541  ;
; RWn          ; RAM_DATA[10]  ; 7.111  ; 7.187  ; 7.187  ; 7.111  ;
; RWn          ; RAM_DATA[11]  ; 7.015  ; 7.087  ; 7.087  ; 7.015  ;
; RWn          ; RAM_DATA[12]  ; 7.312  ; 7.312  ; 7.312  ; 7.312  ;
; RWn          ; RAM_DATA[13]  ; 6.967  ; 6.967  ; 6.967  ; 6.967  ;
; RWn          ; RAM_DATA[14]  ; 6.992  ; 6.992  ; 6.992  ; 6.992  ;
; RWn          ; RAM_DATA[15]  ; 7.118  ; 7.118  ; 7.118  ; 7.118  ;
; RWn          ; RAM_WEn       ; 7.215  ;        ;        ; 7.215  ;
; RWn          ; ROM0n         ;        ; 7.133  ; 7.133  ;        ;
; RWn          ; ROM1n         ;        ; 6.758  ; 6.758  ;        ;
; RWn          ; ROM2n         ;        ; 6.813  ; 6.813  ;        ;
; RWn          ; ROM3n         ;        ; 6.733  ; 6.733  ;        ;
; RWn          ; ROM4n         ;        ; 6.627  ; 6.627  ;        ;
; RWn          ; ROM5n         ;        ; 7.441  ; 7.441  ;        ;
; RWn          ; ROM6n         ;        ; 6.441  ; 6.441  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.502  ; 7.502  ; 7.502  ; 7.502  ;
; SCSI_ATNn    ; CD[1]         ; 8.338  ; 8.338  ; 8.338  ; 8.338  ;
; SCSI_BSYn    ; CD[6]         ; 10.200 ; 10.200 ; 10.200 ; 10.200 ;
; SCSI_D[0]    ; CD[0]         ; 7.818  ; 7.818  ; 7.818  ; 7.818  ;
; SCSI_D[1]    ; CD[1]         ; 7.467  ; 7.467  ; 7.467  ; 7.467  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.645  ; 7.645  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.458  ; 7.458  ; 7.458  ; 7.458  ;
; SCSI_D[4]    ; CD[4]         ; 10.375 ; 10.375 ; 10.375 ; 10.375 ;
; SCSI_D[5]    ; CD[5]         ; 10.138 ; 10.138 ; 10.138 ; 10.138 ;
; SCSI_D[6]    ; CD[6]         ; 10.212 ; 10.212 ; 10.212 ; 10.212 ;
; SCSI_D[7]    ; CD[7]         ; 8.008  ; 8.008  ; 8.008  ; 8.008  ;
; SCSI_DCn     ; CD[3]         ; 7.703  ; 7.703  ; 7.703  ; 7.703  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.758  ; 7.758  ; 7.758  ; 7.758  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_DP       ; 7.214  ; 7.214  ; 7.214  ; 7.214  ;
; SCSI_DP      ; CD[0]         ; 7.345  ; 7.345  ; 7.345  ; 7.345  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.002  ; 6.002  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.217  ;        ;        ; 6.217  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.034  ; 6.034  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.118  ;        ;        ; 6.118  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.290  ; 6.290  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.098  ;        ;        ; 6.098  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.578  ; 6.578  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.278  ;        ;        ; 6.278  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.282  ; 6.282  ; 6.282  ; 6.282  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.746  ; 5.746  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.996  ; 5.996  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.776  ;        ;        ; 5.776  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.885  ;        ;        ; 5.885  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.036  ; 6.036  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 5.880  ; 5.880  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.044  ;        ;        ; 6.044  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.061  ; 6.061  ; 6.061  ; 6.061  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.042  ; 6.042  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.291  ; 6.291  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.069  ; 6.069  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.179  ; 6.179  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.170  ;        ;        ; 6.170  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.623  ;        ;        ; 6.623  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.849  ; 7.849  ;        ;
; SCSI_IOn     ; CD[3]         ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.577  ; 7.460  ; 7.460  ; 6.577  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.023  ; 6.023  ; 6.023  ; 6.023  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.023  ; 6.023  ; 6.023  ; 6.023  ;
; SCSI_IOn     ; SCSI_D[2]     ; 5.822  ; 5.822  ; 5.822  ; 5.822  ;
; SCSI_IOn     ; SCSI_D[3]     ; 5.822  ; 5.822  ; 5.822  ; 5.822  ;
; SCSI_IOn     ; SCSI_D[4]     ; 5.942  ; 5.942  ; 5.942  ; 5.942  ;
; SCSI_IOn     ; SCSI_D[5]     ; 5.942  ; 5.942  ; 5.942  ; 5.942  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.046  ; 6.046  ; 6.046  ; 6.046  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.046  ; 6.046  ; 6.046  ; 6.046  ;
; SCSI_IOn     ; SCSI_DP       ; 6.033  ; 6.033  ; 6.033  ; 6.033  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.523  ;        ;        ; 6.523  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.463  ; 6.463  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.066  ; 8.066  ; 8.066  ; 8.066  ;
; SCSI_MSGn    ; CD[4]         ; 9.988  ; 9.988  ; 9.988  ; 9.988  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.612  ; 7.612  ; 7.612  ; 7.612  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.068  ; 7.068  ; 7.068  ; 7.068  ;
; SCSI_REQn    ; CD[3]         ; 8.082  ; 8.082  ; 8.082  ; 8.082  ;
; SCSI_REQn    ; CD[5]         ; 9.873  ; 9.873  ; 9.873  ; 9.873  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.628  ;        ;        ; 7.628  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[2]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[3]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[4]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[5]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_DP       ; 7.084  ; 7.084  ; 7.084  ; 7.084  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.248  ; 8.248  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.409  ; 7.409  ; 7.409  ; 7.409  ;
; SD_AVR_ENn   ; RESETn        ;        ; 8.539  ; 8.539  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.467  ; 6.467  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 5.432  ; 5.432  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.457  ;        ;        ; 6.457  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.305  ;        ;        ; 6.305  ;
; SD_RESETn    ; ACSI_RDn      ; 9.176  ; 9.176  ; 9.176  ; 9.176  ;
; SD_RESETn    ; ACSI_WRn      ; 9.805  ; 9.805  ; 9.805  ; 9.805  ;
; SD_RESETn    ; CA1_OUT       ; 9.729  ;        ;        ; 9.729  ;
; SD_RESETn    ; CD[0]         ; 10.054 ; 10.054 ; 10.054 ; 10.054 ;
; SD_RESETn    ; CD[1]         ; 9.937  ; 9.937  ; 9.937  ; 9.937  ;
; SD_RESETn    ; CD[2]         ; 9.579  ; 9.537  ; 9.537  ; 9.579  ;
; SD_RESETn    ; CD[3]         ; 9.937  ; 9.937  ; 9.937  ; 9.937  ;
; SD_RESETn    ; CD[4]         ; 9.697  ; 9.697  ; 9.697  ; 9.697  ;
; SD_RESETn    ; CD[5]         ; 9.906  ; 9.906  ; 9.906  ; 9.906  ;
; SD_RESETn    ; CD[6]         ; 9.865  ; 9.865  ; 9.865  ; 9.865  ;
; SD_RESETn    ; CD[7]         ; 9.385  ; 9.385  ; 9.385  ; 9.385  ;
; SD_RESETn    ; COM_TxD       ; 8.602  ; 8.602  ; 8.602  ; 8.602  ;
; SD_RESETn    ; DATA[0]       ; 9.699  ; 9.741  ; 9.741  ; 9.699  ;
; SD_RESETn    ; DATA[1]       ; 10.019 ; 10.019 ; 10.019 ; 10.019 ;
; SD_RESETn    ; DATA[2]       ; 9.573  ; 9.450  ; 9.450  ; 9.573  ;
; SD_RESETn    ; DATA[3]       ; 10.117 ; 9.952  ; 9.952  ; 10.117 ;
; SD_RESETn    ; DATA[4]       ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; SD_RESETn    ; DATA[5]       ; 9.708  ; 9.708  ; 9.708  ; 9.708  ;
; SD_RESETn    ; DATA[6]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; SD_RESETn    ; DATA[7]       ; 9.839  ; 9.630  ; 9.630  ; 9.839  ;
; SD_RESETn    ; DATA[8]       ; 10.272 ; 10.623 ; 10.623 ; 10.272 ;
; SD_RESETn    ; DATA[9]       ; 10.232 ; 10.261 ; 10.261 ; 10.232 ;
; SD_RESETn    ; DATA[10]      ; 10.522 ; 10.522 ; 10.522 ; 10.522 ;
; SD_RESETn    ; DATA[11]      ; 10.487 ; 10.487 ; 10.487 ; 10.487 ;
; SD_RESETn    ; DATA[12]      ; 9.985  ; 9.985  ; 9.985  ; 9.985  ;
; SD_RESETn    ; DATA[13]      ; 10.105 ; 10.105 ; 10.105 ; 10.105 ;
; SD_RESETn    ; DATA[14]      ; 10.641 ; 10.641 ; 10.641 ; 10.641 ;
; SD_RESETn    ; DATA[15]      ; 10.307 ; 10.307 ; 10.307 ; 10.307 ;
; SD_RESETn    ; DTACKn        ; 8.740  ; 8.740  ; 8.740  ; 8.740  ;
; SD_RESETn    ; RAM_DATA[0]   ; 10.647 ; 10.689 ; 10.689 ; 10.647 ;
; SD_RESETn    ; RAM_DATA[1]   ; 10.732 ; 10.732 ; 10.732 ; 10.732 ;
; SD_RESETn    ; RAM_DATA[2]   ; 10.702 ; 10.579 ; 10.579 ; 10.702 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.049 ; 10.884 ; 10.884 ; 11.049 ;
; SD_RESETn    ; RAM_DATA[4]   ; 10.839 ; 10.839 ; 10.839 ; 10.839 ;
; SD_RESETn    ; RAM_DATA[5]   ; 10.648 ; 10.648 ; 10.648 ; 10.648 ;
; SD_RESETn    ; RAM_DATA[6]   ; 10.995 ; 10.995 ; 10.995 ; 10.995 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.575 ; 11.366 ; 11.366 ; 11.575 ;
; SD_RESETn    ; RAM_DATA[8]   ; 11.317 ; 11.668 ; 11.668 ; 11.317 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.116 ; 11.145 ; 11.145 ; 11.116 ;
; SD_RESETn    ; RAM_DATA[10]  ; 10.801 ; 10.801 ; 10.801 ; 10.801 ;
; SD_RESETn    ; RAM_DATA[11]  ; 10.987 ; 10.987 ; 10.987 ; 10.987 ;
; SD_RESETn    ; RAM_DATA[12]  ; 10.646 ; 10.646 ; 10.646 ; 10.646 ;
; SD_RESETn    ; RAM_DATA[13]  ; 10.559 ; 10.559 ; 10.559 ; 10.559 ;
; SD_RESETn    ; RAM_DATA[14]  ; 10.729 ; 10.729 ; 10.729 ; 10.729 ;
; SD_RESETn    ; RAM_DATA[15]  ; 10.558 ; 10.558 ; 10.558 ; 10.558 ;
; UDSn         ; ACSI_RDn      ; 8.810  ; 8.810  ; 8.810  ; 8.810  ;
; UDSn         ; ACSI_WRn      ; 9.439  ; 9.439  ; 9.439  ; 9.439  ;
; UDSn         ; CA1_OUT       ; 9.363  ;        ;        ; 9.363  ;
; UDSn         ; CD[0]         ; 9.688  ; 9.688  ; 9.688  ; 9.688  ;
; UDSn         ; CD[1]         ; 9.571  ; 9.571  ; 9.571  ; 9.571  ;
; UDSn         ; CD[2]         ; 9.213  ; 9.171  ; 9.171  ; 9.213  ;
; UDSn         ; CD[3]         ; 9.571  ; 9.571  ; 9.571  ; 9.571  ;
; UDSn         ; CD[4]         ; 9.331  ; 9.331  ; 9.331  ; 9.331  ;
; UDSn         ; CD[5]         ; 9.540  ; 9.540  ; 9.540  ; 9.540  ;
; UDSn         ; CD[6]         ; 9.499  ; 9.499  ; 9.499  ; 9.499  ;
; UDSn         ; CD[7]         ; 9.019  ; 9.019  ; 9.019  ; 9.019  ;
; UDSn         ; DATA[0]       ; 8.734  ; 8.734  ; 8.734  ; 8.734  ;
; UDSn         ; DATA[1]       ; 8.722  ; 8.734  ; 8.734  ; 8.722  ;
; UDSn         ; DATA[2]       ; 8.568  ; 8.596  ; 8.596  ; 8.568  ;
; UDSn         ; DATA[3]       ; 8.596  ; 8.555  ; 8.555  ; 8.596  ;
; UDSn         ; DATA[4]       ; 8.528  ; 8.588  ; 8.588  ; 8.528  ;
; UDSn         ; DATA[5]       ; 8.588  ; 8.588  ; 8.588  ; 8.588  ;
; UDSn         ; DATA[6]       ; 8.380  ; 8.443  ; 8.443  ; 8.380  ;
; UDSn         ; DATA[7]       ; 8.433  ; 8.433  ; 8.433  ; 8.433  ;
; UDSn         ; DATA[8]       ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; UDSn         ; DATA[9]       ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; UDSn         ; DATA[10]      ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; UDSn         ; DATA[11]      ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; UDSn         ; DATA[12]      ; 8.774  ; 8.774  ; 8.774  ; 8.774  ;
; UDSn         ; DATA[13]      ; 8.774  ; 8.774  ; 8.774  ; 8.774  ;
; UDSn         ; DATA[14]      ; 8.780  ; 8.780  ; 8.780  ; 8.780  ;
; UDSn         ; DATA[15]      ; 8.770  ; 8.770  ; 8.770  ; 8.770  ;
; UDSn         ; DTACKn        ; 7.904  ; 7.904  ; 7.904  ; 7.904  ;
; UDSn         ; JOY_RHn       ; 7.055  ;        ;        ; 7.055  ;
; UDSn         ; RAM_CAS0n     ; 7.564  ;        ;        ; 7.564  ;
; UDSn         ; RAM_CAS1n     ; 6.976  ;        ;        ; 6.976  ;
; UDSn         ; RAM_DATA[0]   ; 9.975  ; 9.933  ; 9.933  ; 9.975  ;
; UDSn         ; RAM_DATA[1]   ; 9.435  ; 9.580  ; 9.580  ; 9.435  ;
; UDSn         ; RAM_DATA[2]   ; 9.697  ; 9.974  ; 9.974  ; 9.697  ;
; UDSn         ; RAM_DATA[3]   ; 9.617  ; 9.487  ; 9.487  ; 9.617  ;
; UDSn         ; RAM_DATA[4]   ; 9.763  ; 9.869  ; 9.869  ; 9.763  ;
; UDSn         ; RAM_DATA[5]   ; 9.853  ; 9.872  ; 9.872  ; 9.853  ;
; UDSn         ; RAM_DATA[6]   ; 9.956  ; 10.049 ; 10.049 ; 9.956  ;
; UDSn         ; RAM_DATA[7]   ; 10.220 ; 10.310 ; 10.310 ; 10.220 ;
; UDSn         ; RAM_DATA[8]   ; 10.502 ; 10.555 ; 10.555 ; 10.502 ;
; UDSn         ; RAM_DATA[9]   ; 10.404 ; 10.432 ; 10.432 ; 10.404 ;
; UDSn         ; RAM_DATA[10]  ; 9.663  ; 9.663  ; 9.663  ; 9.663  ;
; UDSn         ; RAM_DATA[11]  ; 9.509  ; 9.509  ; 9.509  ; 9.509  ;
; UDSn         ; RAM_DATA[12]  ; 9.886  ; 9.922  ; 9.922  ; 9.886  ;
; UDSn         ; RAM_DATA[13]  ; 9.713  ; 9.642  ; 9.642  ; 9.713  ;
; UDSn         ; RAM_DATA[14]  ; 9.226  ; 9.226  ; 9.226  ; 9.226  ;
; UDSn         ; RAM_DATA[15]  ; 9.296  ; 9.296  ; 9.296  ; 9.296  ;
; UDSn         ; RAM_DQM0H     ; 6.854  ;        ;        ; 6.854  ;
; UDSn         ; RAM_DQM1H     ; 6.925  ;        ;        ; 6.925  ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 8.389  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.664  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 8.547  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 8.389  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 8.547  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 8.521  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 8.521  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 8.508  ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 8.508  ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.630  ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.791  ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.651  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 5.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 5.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 5.546  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 5.536  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 5.657  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 5.647  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.633  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.888  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 14.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.743 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 14.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 14.600 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 14.600 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 14.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 14.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.858  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 12.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 12.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 12.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 12.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 12.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 12.387 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 12.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 12.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 12.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 12.718 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 12.718 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 12.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 12.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.602  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 14.275 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.930  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.930  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.344  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 4.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.591  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.591  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.466 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.800 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.988 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.800 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.188 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.416 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 4.208  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.444  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.219  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.394  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.810  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.810  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.465  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.465  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.713  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 4.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.214  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.525  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.525  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.523  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.220  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.220  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.418  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.408  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.529  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.519  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.621  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.621  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.401  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.495  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.505  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 9.200  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 9.475  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 9.200  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 9.332  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 9.332  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 9.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 9.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 7.499  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 7.800  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 7.800  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 7.654  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 7.654  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 7.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 7.499  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 7.798  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 7.798  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 7.840  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 7.840  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 7.846  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 7.836  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 9.007  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 7.184  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 7.019  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 7.019  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 7.212  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 7.212  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 7.518  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 7.706  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 7.518  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 6.906  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 7.134  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.653  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.651  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.641  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 5.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 5.348  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 5.546  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 5.536  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 5.657  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 5.647  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.749  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.623  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.633  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.418  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.888  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 14.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.743 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 14.468 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.626 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 14.600 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 14.600 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 14.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 14.587 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.858  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 12.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 12.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 12.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 12.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 12.532 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 12.387 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 12.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 12.540 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 12.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 12.676 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 12.718 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 12.718 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 12.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 12.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.602  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 14.275 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.930  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.930  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.973  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.344  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 4.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.281  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.591  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.591  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.702  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.466 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.800 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.988 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.800 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.188 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.178 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.422 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.416 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 4.208  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.444  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.219  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.394  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.810  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.810  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.609  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.729  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.465  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.820  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.019  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.455  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.465  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.713  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 4.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.838  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.214  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.525  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.525  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.523  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.513  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.079  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.220  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.220  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.418  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.408  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.529  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.519  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.621  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.621  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.401  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.495  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.505  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.290  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.200  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.475  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.200  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.358  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.332  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.332  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.319  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 7.499  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.800  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.800  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.654  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.654  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 7.509  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 7.499  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.662  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.798  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.798  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.840  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.840  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.846  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.836  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 9.007  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 7.184  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 7.019  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 7.019  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 7.212  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 7.212  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 7.518  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 7.706  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 7.518  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 6.906  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 6.896  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 7.140  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 7.134  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.953  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 6.592  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 6.867  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 6.750  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 6.592  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 6.750  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 6.724  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 6.724  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 6.711  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 6.711  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.260  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.260  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.303  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.303  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.358  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.558  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.786  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.538  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.630  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.405  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.012  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.012  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.035  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.035  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 4.022  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.899  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.498  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.953  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.592  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.867  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.750  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.592  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.750  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.724  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.724  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.711  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.711  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.833  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.321  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.260  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.260  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.303  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.303  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.836  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.671  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.358  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.170  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.558  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.548  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.792  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.786  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.538  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.630  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.405  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.580  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.012  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.012  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.811  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.035  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.035  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.022  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.251  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.687  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.697  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.899  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.498  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 5.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 5.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 5.044  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 5.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 5.454  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise  ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 7.807 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.082 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 7.965 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 7.807 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 7.965 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 7.939 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 7.939 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 7.926 ;      ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 7.926 ;      ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.630 ;      ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.768 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.499 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.196 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.196 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.394 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.384 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.495 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 2.981 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.256 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 2.981 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 2.927 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 2.792 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 3.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 3.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 2.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 2.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 2.792 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 3.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 3.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 3.133 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 3.133 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 3.129 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.476 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 3.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.344 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.868 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.591 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.591 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.836 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.836 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.751 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.586 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.586 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.779 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.779 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.273 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.473 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.701 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.906 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.219 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.394 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 2.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 2.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.465 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 2.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.455 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.465 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 2.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.763 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.868 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.721 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.214 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.523 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.220 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.220 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.418 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.408 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.519 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.621 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.621 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.401 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.495 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.505 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.323 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.180 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.180 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.167 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.167 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 4.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 4.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 4.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.310 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.310 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.352 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.352 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.348 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 5.009 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.751 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.586 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.586 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.779 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.779 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.085 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.085 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.473 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.501 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.499 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.055 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.196 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.196 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.394 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.384 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.505 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.495 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.597 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.377 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.481 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.266 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 2.981 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.256 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 2.981 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.113 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 2.927 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 2.792 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 3.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 3.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 2.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 2.947 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 2.802 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 2.792 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 2.955 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 3.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 3.091 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 3.133 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 3.133 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 3.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 3.129 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.476 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.742 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.628 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.344 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.868 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.281 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.591 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.591 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.836 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.836 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.702 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.751 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.586 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.586 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.779 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.779 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.273 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.085 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.473 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.707 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.701 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.906 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.494 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.219 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.394 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 2.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 2.714 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.513 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.737 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.465 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 2.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.455 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.465 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 2.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.763 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.868 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.721 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.214 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.525 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.523 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.513 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.079 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.220 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.220 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.418 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.408 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.519 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.621 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.621 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.401 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.495 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.505 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.290 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.323 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.048 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.206 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.180 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.180 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.167 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.167 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 4.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.312 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 4.021 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 4.011 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.174 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.310 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.310 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.352 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.352 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.358 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.348 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.009 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.751 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.586 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.586 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.779 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.779 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.085 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.085 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.473 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.463 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.707 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.701 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 3.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.102 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 3.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 3.959 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 3.959 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.187 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.325 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.260 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.260 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.303 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.303 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.188 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.710 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 3.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.138 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.538 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.398 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.766 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.766 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.776 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.849 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.806 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.498 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.953 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.102 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.959 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.959 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.946 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.187 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.325 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.260 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.260 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.303 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.303 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.188 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.216 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.710 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 3.910 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.900 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.144 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.138 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.538 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.398 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.766 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.766 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.565 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.685 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.776 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.242 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.678 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.688 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.849 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.806 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.500 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.498 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 4.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 4.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 4.156 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 4.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 4.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 8.389     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.664     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 8.547     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 8.389     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 8.547     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 8.521     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 8.521     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 8.508     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 8.508     ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.630     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.791     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.651     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 5.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 5.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 5.546     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 5.536     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 5.657     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 5.647     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.888     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 14.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.743    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 14.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 14.600    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 14.600    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 14.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 14.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.858     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 12.377    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 12.678    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 12.678    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 12.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 12.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 12.387    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 12.377    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 12.676    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 12.676    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 12.718    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 12.718    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 12.724    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 12.714    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 14.275    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.930     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.930     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 4.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 11.466    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 11.301    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 11.301    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.494    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.494    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.800    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.988    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.800    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.188    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 11.416    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 4.208     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.219     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.810     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.810     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 4.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.523     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.418     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.519     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.495     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.505     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 9.200     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 9.475     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 9.200     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 9.332     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 9.332     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 9.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 9.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 7.499     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 7.800     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 7.800     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 7.654     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 7.654     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 7.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 7.499     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 7.798     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 7.798     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 7.840     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 7.840     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 7.846     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 7.836     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 9.007     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 7.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 7.019     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 7.019     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 7.212     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 7.212     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 7.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 7.706     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 7.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 6.906     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 7.134     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.653     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.651     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.641     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 5.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 5.348     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 5.546     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 5.536     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 5.657     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 5.647     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.749     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.623     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.418     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.888     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 14.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.743    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 14.468    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.626    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 14.600    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 14.600    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 14.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 14.587    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.858     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 12.377    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 12.678    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 12.678    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 12.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 12.532    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 12.387    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 12.377    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 12.540    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 12.676    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 12.676    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 12.718    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 12.718    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 12.724    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 12.714    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 14.275    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.930     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.930     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.973     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 4.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 11.466    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 11.301    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 11.301    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.494    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.494    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.800    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.988    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.800    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.188    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 11.178    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 11.422    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 11.416    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 4.208     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.219     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.810     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.810     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.609     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.729     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.820     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.713     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 4.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.838     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.523     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.418     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.519     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.495     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.505     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.200     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.475     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.200     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.332     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.332     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.319     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 7.499     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.800     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.800     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.654     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.654     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 7.509     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 7.499     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.662     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.798     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.798     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.840     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.840     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.846     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.836     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 9.007     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 7.184     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 7.019     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 7.019     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 7.212     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 7.212     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 7.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 7.706     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 7.518     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 6.906     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 6.896     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 7.140     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 7.134     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.953     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 6.592     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 6.867     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 6.750     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 6.592     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 6.750     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 6.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 6.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 6.711     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 6.711     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 5.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 5.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 5.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 5.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 5.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 6.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 6.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 6.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 5.558     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 5.786     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.538     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.630     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.405     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.012     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.012     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.035     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.035     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 4.022     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.899     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.498     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.953     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.592     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.867     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.750     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.592     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.750     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.711     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.711     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.833     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.321     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 5.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 5.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 5.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 5.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 5.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 6.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 6.358     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 6.170     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 5.558     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 5.548     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 5.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 5.786     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.538     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.630     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.405     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.580     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.012     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.012     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.811     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.035     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.035     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.022     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.251     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.687     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.697     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.899     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.498     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 5.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 5.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 5.044     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 5.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 5.454     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; CD[*]         ; CLK_PLL1      ; 7.807     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]        ; CLK_PLL1      ; 8.082     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]        ; CLK_PLL1      ; 7.965     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]        ; CLK_PLL1      ; 7.807     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]        ; CLK_PLL1      ; 7.965     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]        ; CLK_PLL1      ; 7.939     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]        ; CLK_PLL1      ; 7.939     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]        ; CLK_PLL1      ; 7.926     ;           ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]        ; CLK_PLL1      ; 7.926     ;           ; Rise       ; CLK_PLL1                                                   ;
; COM_TxD       ; CLK_PLL1      ; 6.630     ;           ; Rise       ; CLK_PLL1                                                   ;
; DTACKn        ; CLK_PLL1      ; 6.768     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.499     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.384     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.495     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.471     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 2.981     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.256     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 2.981     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 2.927     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 2.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 3.093     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 3.093     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 2.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 2.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 2.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 3.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 3.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 3.133     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 3.133     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 3.129     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 3.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 3.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC         ; CLK_PLL1      ; 3.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.586     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.586     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.779     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.779     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.273     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.701     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.219     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 2.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 2.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 2.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 2.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 2.737     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 2.737     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 2.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn     ; CLK_PLL1      ; 2.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.763     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.721     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC         ; CLK_PLL1      ; 3.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.523     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 3.418     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 3.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.519     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 3.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.495     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.505     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 6.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 6.323     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 6.206     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 6.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 6.206     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 6.180     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 6.180     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 6.167     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 6.167     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 4.011     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 4.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 4.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 4.021     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 4.011     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 4.310     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 4.310     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 4.352     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 4.352     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 4.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 4.348     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 5.009     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.586     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.586     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.779     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.779     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 5.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.473     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.701     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.501     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.499     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.489     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.055     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.196     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.384     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.505     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.495     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.597     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.377     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.471     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.481     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.266     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 2.981     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.256     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 2.981     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.113     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 2.927     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 2.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 3.093     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 3.093     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 2.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 2.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 2.802     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 2.792     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 2.955     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 3.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 3.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 3.133     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 3.133     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 3.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 3.129     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 3.476     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 3.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.671     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 3.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.281     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.591     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 3.836     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 3.702     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.586     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.586     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.779     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.779     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.273     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.085     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.473     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.701     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.906     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.219     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.394     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 2.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 2.714     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 2.513     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 2.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 2.633     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 2.737     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 2.737     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 2.724     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.019     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.455     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.465     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 2.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.763     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.868     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.721     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.214     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.525     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.523     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.513     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.079     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.220     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 3.418     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 3.408     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.519     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.621     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 3.401     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.495     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.505     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.290     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 6.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 6.323     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 6.206     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 6.048     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 6.206     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 6.180     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 6.180     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 6.167     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 6.167     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 4.011     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 4.312     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 4.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 4.166     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 4.021     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 4.011     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 4.174     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 4.310     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 4.310     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 4.352     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 4.352     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 4.358     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 4.348     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 5.009     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.586     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.586     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.779     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.779     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 5.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.085     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.473     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.463     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.707     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.701     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 2.953     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 3.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 4.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 3.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 3.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 3.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.187     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.325     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.188     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.023     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.023     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.216     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.216     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.522     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.710     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.522     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 3.910     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.138     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 3.538     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn     ; CLK_PLL1      ; 3.537     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ATNn     ; CLK_PLL1      ; 4.398     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_BSYn     ; CLK_PLL1      ; 3.573     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DCn      ; CLK_PLL1      ; 3.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_DP       ; CLK_PLL1      ; 3.776     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_IOn      ; CLK_PLL1      ; 3.242     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_MSGn     ; CLK_PLL1      ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_REQn     ; CLK_PLL1      ; 3.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn     ; CLK_PLL1      ; 3.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn     ; CLK_PLL1      ; 3.806     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 7.498     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 2.953     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 4.102     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.827     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.959     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.946     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.187     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.325     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.260     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.303     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.188     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.023     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.023     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.216     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.216     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.522     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.710     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.522     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 3.910     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.900     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.144     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.138     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.538     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 3.537     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 4.398     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 3.573     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.565     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.685     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 3.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.776     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 3.242     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 3.678     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 3.688     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn     ; CRT_PIN4_CLK1 ; 3.849     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 3.806     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 7.498     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]      ; CLK_PLL1      ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]     ; CLK_PLL1      ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]     ; CLK_PLL1      ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]     ; CLK_PLL1      ; 4.353     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]     ; CLK_PLL1      ; 4.353     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 4.156     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 4.353     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 4.353     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                        ;
+-------------------------------------------------------------+-----------+-------+----------+---------+---------------------+
; Clock                                                       ; Setup     ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------+-----------+-------+----------+---------+---------------------+
; Worst-case Slack                                            ; -18.401   ; 0.093 ; 21.278   ; 0.981   ; 7.852               ;
;  CLK_PLL1                                                   ; 55.840    ; 0.240 ; N/A      ; N/A     ; 30.139              ;
;  CLK_PLL2                                                   ; N/A       ; N/A   ; N/A      ; N/A     ; 31.250              ;
;  CODEC_SCLK                                                 ; 30.595    ; 0.110 ; 78.638   ; 1.150   ; 38.136              ;
;  CRT_PIN4_CLK1                                              ; N/A       ; N/A   ; N/A      ; N/A     ; 31.250              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -18.401   ; 0.093 ; 21.278   ; 1.171   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -18.401   ; 0.093 ; 21.278   ; 1.171   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -15.544   ; 0.215 ; 21.278   ; 0.981   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -15.544   ; 0.215 ; 21.278   ; 0.981   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -13.239   ; 0.215 ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -13.239   ; 0.215 ; N/A      ; N/A     ; 7.852               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 38.203    ; 0.215 ; N/A      ; N/A     ; 18.420              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 23.014    ; 0.215 ; N/A      ; N/A     ; 11.584              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 60.574    ; 0.215 ; N/A      ; N/A     ; 30.139              ;
; Design-wide TNS                                             ; -20920.2  ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_PLL1                                                   ; 0.000     ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  CLK_PLL2                                                   ; N/A       ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  CODEC_SCLK                                                 ; 0.000     ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  CRT_PIN4_CLK1                                              ; N/A       ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -7932.130 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -7932.130 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -2130.320 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -2130.320 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; -397.650  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; -397.650  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 0.000     ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.000     ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.000     ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+-------------------------------------------------------------+-----------+-------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.939  ; 0.939  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; 10.048 ; 10.048 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.390  ; 0.390  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; 12.086 ; 12.086 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; 30.620 ; 30.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.191  ; 7.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 12.705 ; 12.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.081  ; 7.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 9.111  ; 9.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 9.487  ; 9.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 9.338  ; 9.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.447  ; 9.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 10.385 ; 10.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.943 ; 18.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.597 ; 19.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 21.774 ; 21.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 22.256 ; 22.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 23.796 ; 23.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 17.388 ; 17.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 16.751 ; 16.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.250 ; 16.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.606 ; 16.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 18.119 ; 18.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 15.555 ; 15.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.643 ; 16.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 17.139 ; 17.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.408 ; 17.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 17.985 ; 17.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.930 ; 17.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 18.277 ; 18.277 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 17.774 ; 17.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 16.764 ; 16.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 12.427 ; 12.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 11.607 ; 11.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.757  ; 8.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 29.746 ; 29.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 30.045 ; 30.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 13.736 ; 13.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; 11.292 ; 11.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 16.983 ; 16.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 10.193 ; 10.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 21.471 ; 21.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 21.910 ; 21.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 28.679 ; 28.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 21.129 ; 21.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.922 ; 16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.657 ; 17.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.929 ; 17.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 18.294 ; 18.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.178 ; 18.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 19.713 ; 19.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.145 ; 19.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 6.244  ; 6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; 4.992  ; 4.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; 5.116  ; 5.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; 4.954  ; 4.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; 4.497  ; 4.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 18.861 ; 18.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.677 ; 19.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.667 ; 18.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 19.300 ; 19.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 20.176 ; 20.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 20.904 ; 20.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 20.980 ; 20.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 20.113 ; 20.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 20.357 ; 20.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 20.842 ; 20.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 19.523 ; 19.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.977 ; 20.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 29.173 ; 29.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.664  ; 8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 9.557  ; 9.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 9.262  ; 9.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.062  ; 9.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 9.542  ; 9.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 9.091  ; 9.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 9.406  ; 9.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.470 ; 11.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 11.599 ; 11.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 11.714 ; 11.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.685  ; 9.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.850 ; 14.850 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 6.940  ; 6.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 14.006 ; 14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 27.043 ; 27.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 7.696  ; 7.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 10.163 ; 10.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 8.921  ; 8.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.611  ; 8.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 10.680 ; 10.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 9.526  ; 9.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 29.405 ; 29.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 9.688  ; 9.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 8.618  ; 8.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 28.121 ; 28.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 8.832  ; 8.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.627  ; 8.627  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 6.855  ; 6.855  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; 18.539 ; 18.539 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.139 ; 19.139 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 19.239 ; 19.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 20.574 ; 20.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 20.676 ; 20.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; 23.545 ; 23.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; 15.808 ; 15.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 15.171 ; 15.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.241 ; 15.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.610 ; 16.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 18.011 ; 18.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.323 ; 16.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 14.915 ; 14.915 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 16.335 ; 16.335 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.783 ; 16.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 16.206 ; 16.206 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.433 ; 16.433 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.526 ; 17.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 17.451 ; 17.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.534 ; 16.534 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.286 ; 15.286 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 9.892  ; 9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 9.382  ; 9.382  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 16.277 ; 16.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; 3.026  ; 3.026  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; 4.113  ; 4.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; 3.520  ; 3.520  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 27.494 ; 27.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 27.793 ; 27.793 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.593  ; 7.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.993 ; 19.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 8.398  ; 8.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 26.180 ; 26.180 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 19.927 ; 19.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 15.720 ; 15.720 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.199 ; 17.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.525 ; 17.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.699 ; 17.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.700 ; 16.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 17.683 ; 17.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.108 ; 18.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 17.852 ; 17.852 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 20.804 ; 20.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.569 ; 19.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.265 ; 18.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.660 ; 18.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 20.548 ; 20.548 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.778 ; 19.778 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.561 ; 18.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 19.953 ; 19.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 20.016 ; 20.016 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 18.283 ; 18.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 19.079 ; 19.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 18.442 ; 18.442 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 19.256 ; 19.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 26.921 ; 26.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; 7.502  ; 7.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; 7.412  ; 7.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 26.906 ; 26.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; 30.620 ; 30.620 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.191  ; 7.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 12.705 ; 12.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.081  ; 7.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.215  ; 9.215  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.111  ; 9.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.487  ; 9.487  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 9.338  ; 9.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.447  ; 9.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 10.385 ; 10.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.390 ; 10.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.943 ; 18.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.597 ; 19.597 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 21.774 ; 21.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 11.327 ; 11.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 22.154 ; 22.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 22.256 ; 22.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 35.296 ; 35.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 23.796 ; 23.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 17.388 ; 17.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 16.751 ; 16.751 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.250 ; 16.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.705 ; 18.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.606 ; 16.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 18.119 ; 18.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.555 ; 15.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.643 ; 16.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.139 ; 17.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.408 ; 17.408 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 17.985 ; 17.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.930 ; 17.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 18.277 ; 18.277 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.774 ; 17.774 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.764 ; 16.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 12.427 ; 12.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 11.607 ; 11.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.757  ; 8.757  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 30.202 ; 30.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 29.746 ; 29.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 30.045 ; 30.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 13.736 ; 13.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.575  ; 6.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; 11.292 ; 11.292 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 16.983 ; 16.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 8.162  ; 8.162  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 10.193 ; 10.193 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 21.471 ; 21.471 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.964  ; 9.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 21.910 ; 21.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.629  ; 7.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 28.679 ; 28.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 21.129 ; 21.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.922 ; 16.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.657 ; 17.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.929 ; 17.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 18.294 ; 18.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.178 ; 18.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 19.713 ; 19.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.145 ; 19.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 6.244  ; 6.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.992  ; 4.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.385  ; 4.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 5.116  ; 5.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 4.954  ; 4.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 4.497  ; 4.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 18.861 ; 18.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 21.658 ; 21.658 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.677 ; 19.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.667 ; 18.667 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 19.300 ; 19.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 20.176 ; 20.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.904 ; 20.904 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 20.980 ; 20.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 20.113 ; 20.113 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 20.357 ; 20.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 20.842 ; 20.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 19.523 ; 19.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 20.557 ; 20.557 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.977 ; 20.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.481 ; 21.481 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 3.891  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 29.173 ; 29.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.724 ; 10.724 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.664  ; 8.664  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.631 ; 10.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 9.557  ; 9.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 9.262  ; 9.262  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.062  ; 9.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 9.542  ; 9.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 9.187  ; 9.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 9.091  ; 9.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 9.406  ; 9.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 11.932 ; 11.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.470 ; 11.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 11.599 ; 11.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 11.714 ; 11.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.685  ; 9.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.850 ; 14.850 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 6.940  ; 6.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 14.006 ; 14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 27.043 ; 27.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 7.696  ; 7.696  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 10.163 ; 10.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 8.921  ; 8.921  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.074  ; 9.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.611  ; 8.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 10.680 ; 10.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 9.526  ; 9.526  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 29.405 ; 29.405 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 9.688  ; 9.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 8.618  ; 8.618  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 28.121 ; 28.121 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 8.832  ; 8.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.627  ; 8.627  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 6.855  ; 6.855  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 18.539 ; 18.539 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.139 ; 19.139 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 19.239 ; 19.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 20.574 ; 20.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 20.676 ; 20.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 33.266 ; 33.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 23.545 ; 23.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 15.808 ; 15.808 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 15.171 ; 15.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.241 ; 15.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.247 ; 18.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.610 ; 16.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 18.011 ; 18.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.323 ; 16.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.915 ; 14.915 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 16.335 ; 16.335 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.783 ; 16.783 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.206 ; 16.206 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.433 ; 16.433 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.526 ; 17.526 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 17.451 ; 17.451 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.534 ; 16.534 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.286 ; 15.286 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 9.892  ; 9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 9.382  ; 9.382  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 16.277 ; 16.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; 3.026  ; 3.026  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; 4.113  ; 4.113  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; 3.520  ; 3.520  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 27.950 ; 27.950 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 27.494 ; 27.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 27.793 ; 27.793 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.593  ; 7.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.993 ; 19.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 8.398  ; 8.398  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.432 ; 20.432 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 26.180 ; 26.180 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 19.927 ; 19.927 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 15.720 ; 15.720 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.199 ; 17.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.525 ; 17.525 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.699 ; 17.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 19.308 ; 19.308 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.700 ; 16.700 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 17.683 ; 17.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.108 ; 18.108 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 17.852 ; 17.852 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 20.804 ; 20.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 21.662 ; 21.662 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.569 ; 19.569 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.265 ; 18.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.660 ; 18.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 19.868 ; 19.868 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 20.548 ; 20.548 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.778 ; 19.778 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.561 ; 18.561 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 19.953 ; 19.953 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 20.016 ; 20.016 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 18.283 ; 18.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 19.079 ; 19.079 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 18.442 ; 18.442 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 19.256 ; 19.256 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 26.921 ; 26.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; 7.502  ; 7.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; 7.412  ; 7.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 26.906 ; 26.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; 26.078 ; 26.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; 16.281 ; 16.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 17.464 ; 17.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 15.897 ; 15.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.531 ; 18.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.633 ; 18.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; 12.126 ; 12.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; 21.357 ; 21.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.765 ; 13.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.128 ; 13.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 14.235 ; 14.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 14.464 ; 14.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 15.663 ; 15.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 14.886 ; 14.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 13.101 ; 13.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 14.740 ; 14.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 14.531 ; 14.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; 9.383  ; 9.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 25.677 ; 25.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 25.976 ; 25.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 17.627 ; 17.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 18.066 ; 18.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 24.137 ; 24.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 14.045 ; 14.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.524 ; 15.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.266 ; 15.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 15.351 ; 15.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 13.720 ; 13.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 15.505 ; 15.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.065 ; 16.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.129 ; 19.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.221 ; 17.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.828 ; 16.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.690 ; 17.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 18.505 ; 18.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.103 ; 18.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 14.260 ; 14.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.165 ; 14.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.307 ; 15.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 15.706 ; 15.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 15.063 ; 15.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 22.920 ; 22.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 24.863 ; 24.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 15.245 ; 15.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 14.651 ; 14.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 14.677 ; 14.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 13.067 ; 13.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 14.796 ; 14.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; 26.078 ; 26.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.281 ; 16.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 17.464 ; 17.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 15.897 ; 15.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.531 ; 18.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.633 ; 18.633 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 31.088 ; 31.088 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 21.357 ; 21.357 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.765 ; 13.765 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.128 ; 13.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.235 ; 14.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.572 ; 16.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.464 ; 14.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.663 ; 15.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 14.886 ; 14.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.101 ; 13.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.740 ; 14.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 14.531 ; 14.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 9.383  ; 9.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.133 ; 26.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.677 ; 25.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 25.976 ; 25.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 17.627 ; 17.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 18.066 ; 18.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.137 ; 24.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.252 ; 18.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 14.045 ; 14.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.524 ; 15.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.266 ; 15.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 15.351 ; 15.351 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.739 ; 17.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 13.720 ; 13.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 15.505 ; 15.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.065 ; 16.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.129 ; 19.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.516 ; 19.516 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.221 ; 17.221 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.828 ; 16.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.690 ; 17.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 18.505 ; 18.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.103 ; 18.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 14.260 ; 14.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.165 ; 14.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.307 ; 15.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 15.706 ; 15.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 15.063 ; 15.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.293 ; 16.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.920 ; 22.920 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 24.863 ; 24.863 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 15.245 ; 15.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 21.497 ; 21.497 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.651 ; 14.651 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.677 ; 14.677 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.982 ; 14.982 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.067 ; 13.067 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 14.796 ; 14.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; 26.646 ; 26.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; 16.547 ; 16.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; 17.647 ; 17.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; 17.800 ; 17.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; 21.540 ; 21.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; 13.843 ; 13.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; 13.206 ; 13.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 14.075 ; 14.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 14.730 ; 14.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 15.589 ; 15.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 13.207 ; 13.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 13.778 ; 13.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 14.951 ; 14.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 14.560 ; 14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.453  ; 8.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; 25.860 ; 25.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; 26.159 ; 26.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; 18.700 ; 18.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; 19.139 ; 19.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; 24.705 ; 24.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; 17.740 ; 17.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; 15.707 ; 15.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 16.076 ; 16.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 16.300 ; 16.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 16.240 ; 16.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; 16.027 ; 16.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.686 ; 16.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.312 ; 19.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.147 ; 17.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 14.872 ; 14.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 16.952 ; 16.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.534 ; 17.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 18.467 ; 18.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.350 ; 17.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.079 ; 17.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.114 ; 17.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 17.125 ; 17.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 16.585 ; 16.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 17.003 ; 17.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 17.936 ; 17.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; 25.287 ; 25.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; 23.069 ; 23.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; 25.431 ; 25.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; 26.646 ; 26.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; 16.547 ; 16.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 17.647 ; 17.647 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 17.800 ; 17.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 18.609 ; 18.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.711 ; 18.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 31.322 ; 31.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; 21.540 ; 21.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; 13.843 ; 13.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; 13.206 ; 13.206 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.075 ; 14.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.755 ; 16.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 14.730 ; 14.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.589 ; 15.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.930 ; 12.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 13.207 ; 13.207 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.001 ; 14.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 14.702 ; 14.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 13.778 ; 13.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.951 ; 14.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.687 ; 14.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.560 ; 14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.993 ; 13.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.453  ; 8.453  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 26.316 ; 26.316 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 25.860 ; 25.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 26.159 ; 26.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 18.700 ; 18.700 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 19.139 ; 19.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 24.705 ; 24.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.740 ; 17.740 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 15.707 ; 15.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 16.076 ; 16.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 17.610 ; 17.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 16.300 ; 16.300 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 16.240 ; 16.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 16.027 ; 16.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.686 ; 16.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.312 ; 19.312 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.782 ; 19.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.147 ; 17.147 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 14.872 ; 14.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 16.952 ; 16.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.534 ; 17.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 18.467 ; 18.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.350 ; 17.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.079 ; 17.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.114 ; 17.114 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 17.125 ; 17.125 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 16.585 ; 16.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 17.003 ; 17.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 17.936 ; 17.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 25.287 ; 25.287 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 23.069 ; 23.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 25.431 ; 25.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.071  ; 0.071  ; Rise       ; CLK_PLL1                                                   ;
; SD_RESETn      ; CODEC_SCLK    ; -4.120 ; -4.120 ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SDIN     ; CODEC_SCLK    ; 0.033  ; 0.033  ; Fall       ; CODEC_SCLK                                                 ;
; SD_RESETn      ; CODEC_SCLK    ; -4.849 ; -4.849 ; Fall       ; CODEC_SCLK                                                 ;
; ASn            ; CLK_PLL1      ; -3.678 ; -3.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.457 ; -3.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.702 ; -3.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.627 ; -3.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.511 ; -3.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.576 ; -3.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.505 ; -3.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.726 ; -3.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -3.685 ; -3.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -3.695 ; -3.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -4.241 ; -4.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.156 ; -5.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.494 ; -7.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -5.023 ; -5.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.449 ; -2.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.176 ; -2.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.573 ; -4.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.624 ; -4.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.404 ; -4.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.837 ; -4.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.733 ; -4.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.304 ; -4.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.146 ; -4.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.276 ; -4.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.186 ; -4.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.040 ; -4.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.134 ; -4.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.018 ; -4.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.736 ; -3.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.998 ; -4.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.894 ; -4.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -4.205 ; -4.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.346 ; -1.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TYPE       ; CLK_PLL1      ; -4.466 ; -4.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -3.729 ; -3.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.021 ; -5.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; -4.189 ; -4.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.158 ; -5.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.984 ; -3.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -4.255 ; -4.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.344 ; -6.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.566 ; -6.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.336 ; -7.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.065 ; -6.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.776 ; -6.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.576 ; -6.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.334 ; -3.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Xn         ; CLK_PLL1      ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD0Yn         ; CLK_PLL1      ; -1.441 ; -1.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Xn         ; CLK_PLL1      ; -1.796 ; -1.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PAD1Yn         ; CLK_PLL1      ; -1.671 ; -1.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PENn           ; CLK_PLL1      ; -1.686 ; -1.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.224 ; -4.224 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.318 ; -4.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -5.017 ; -5.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.145 ; -4.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.246 ; -4.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.148 ; -4.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.310 ; -4.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.961 ; -3.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.755 ; -1.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -4.355 ; -4.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.202 ; -4.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.403 ; -3.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.400 ; -3.400 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.542 ; -3.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.530 ; -3.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.622 ; -3.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.552 ; -3.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -3.779 ; -3.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -3.561 ; -3.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -3.739 ; -3.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.890 ; -3.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.240 ; -4.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -3.640 ; -3.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.289 ; -4.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -3.936 ; -3.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.913 ; -4.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -3.922 ; -3.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -4.123 ; -4.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -5.154 ; -5.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -3.810 ; -3.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -4.780 ; -4.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; -4.011 ; -4.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -5.529 ; -5.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.603 ; -3.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -4.431 ; -4.431 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -4.316 ; -4.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.607 ; -3.607 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_CTS        ; CLK_PLL1      ; -6.823 ; -6.823 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -6.790 ; -6.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -7.326 ; -7.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.608 ; -7.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.600 ; -7.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.866 ; -7.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.620 ; -4.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.932 ; -4.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.276 ; -4.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.034 ; -4.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.305 ; -4.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -5.183 ; -5.183 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -5.105 ; -5.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.782 ; -4.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.567 ; -4.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -4.764 ; -4.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.122 ; -4.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.362 ; -4.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.229 ; -4.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.241 ; -4.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.126 ; -4.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.239 ; -4.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -3.899 ; -3.899 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT3n         ; CLK_PLL1      ; -1.279 ; -1.279 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT5n         ; CLK_PLL1      ; -1.473 ; -1.473 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; EINT7n         ; CLK_PLL1      ; -1.479 ; -1.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.457 ; -5.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -4.245 ; -4.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.940 ; -3.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -7.918 ; -7.918 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -4.367 ; -4.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -8.055 ; -8.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.848 ; -4.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -7.686 ; -7.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.663 ; -6.663 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.734 ; -6.734 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.646 ; -7.646 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.437 ; -6.437 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.003 ; -7.003 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.595 ; -6.595 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.269 ; -7.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.938 ; -7.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.230 ; -8.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.599 ; -7.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.388 ; -7.388 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.748 ; -7.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.068 ; -8.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.529 ; -7.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.935 ; -7.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.329 ; -7.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.722 ; -7.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.583 ; -7.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.589 ; -7.589 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.563 ; -7.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.698 ; -7.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.092 ; -4.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.942 ; -5.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_CTSn ; CLK_PLL1      ; -3.983 ; -3.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_DCDn ; CLK_PLL1      ; -3.892 ; -3.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.699 ; -5.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.678 ; -3.678 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.457 ; -3.457 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.702 ; -3.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.627 ; -3.627 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.511 ; -3.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.576 ; -3.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.505 ; -3.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.548 ; -3.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.463 ; -3.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.768 ; -3.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.726 ; -3.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -3.685 ; -3.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -3.695 ; -3.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -3.521 ; -3.521 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -4.241 ; -4.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.921 ; -4.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.156 ; -5.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.494 ; -7.494 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -5.023 ; -5.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.449 ; -2.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.176 ; -2.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.573 ; -4.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.624 ; -4.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.404 ; -4.404 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.837 ; -4.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.733 ; -4.733 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.304 ; -4.304 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.213 ; -4.213 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.146 ; -4.146 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.276 ; -4.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.186 ; -4.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.040 ; -4.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.134 ; -4.134 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.018 ; -4.018 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.723 ; -3.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -4.554 ; -4.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.736 ; -3.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.998 ; -4.998 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.804 ; -4.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.894 ; -4.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -4.205 ; -4.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.346 ; -1.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TYPE       ; CRT_PIN4_CLK1 ; -4.466 ; -4.466 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -3.729 ; -3.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.914 ; -3.914 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.021 ; -5.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; -4.189 ; -4.189 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.158 ; -5.158 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.984 ; -3.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -3.708 ; -3.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -4.255 ; -4.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.844 ; -5.844 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.344 ; -6.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.566 ; -6.566 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.336 ; -7.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.065 ; -6.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.776 ; -6.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.576 ; -6.576 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.334 ; -3.334 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.699 ; -1.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.441 ; -1.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.796 ; -1.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -1.671 ; -1.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -1.686 ; -1.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.224 ; -4.224 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.318 ; -4.318 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -5.017 ; -5.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.145 ; -4.145 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.555 ; -4.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.246 ; -4.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.148 ; -4.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.310 ; -4.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.388 ; -4.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.961 ; -3.961 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.755 ; -1.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -4.355 ; -4.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.780 ; -3.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.202 ; -4.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.732 ; -3.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.444 ; -3.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.403 ; -3.403 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.384 ; -3.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.400 ; -3.400 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.542 ; -3.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.530 ; -3.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.622 ; -3.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.552 ; -3.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -3.779 ; -3.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -3.561 ; -3.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -3.739 ; -3.739 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.890 ; -3.890 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.240 ; -4.240 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -3.640 ; -3.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.394 ; -4.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.289 ; -4.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -3.936 ; -3.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.913 ; -4.913 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -3.882 ; -3.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -3.922 ; -3.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -3.969 ; -3.969 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -4.123 ; -4.123 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -5.154 ; -5.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -4.685 ; -4.685 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -3.810 ; -3.810 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -4.780 ; -4.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; -4.011 ; -4.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.529 ; -5.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.603 ; -3.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -4.431 ; -4.431 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -4.316 ; -4.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.607 ; -3.607 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.823 ; -6.823 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.790 ; -6.790 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.326 ; -7.326 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.608 ; -7.608 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.600 ; -7.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.866 ; -7.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.942 ; -4.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.620 ; -4.620 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.932 ; -4.932 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.276 ; -4.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.034 ; -4.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.305 ; -4.305 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -5.183 ; -5.183 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -5.105 ; -5.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.567 ; -4.567 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.764 ; -4.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.122 ; -4.122 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.362 ; -4.362 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.229 ; -4.229 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.241 ; -4.241 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.126 ; -4.126 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.239 ; -4.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.815 ; -3.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -3.899 ; -3.899 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT3n         ; CRT_PIN4_CLK1 ; -1.279 ; -1.279 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT5n         ; CRT_PIN4_CLK1 ; -1.473 ; -1.473 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; EINT7n         ; CRT_PIN4_CLK1 ; -1.479 ; -1.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.371 ; -5.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.352 ; -5.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.457 ; -5.457 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -4.245 ; -4.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.940 ; -3.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.918 ; -7.918 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -4.367 ; -4.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -8.055 ; -8.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.848 ; -4.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.686 ; -7.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.203 ; -6.203 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.663 ; -6.663 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.734 ; -6.734 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.646 ; -7.646 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.437 ; -6.437 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.003 ; -7.003 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.595 ; -6.595 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.269 ; -7.269 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.938 ; -7.938 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.230 ; -8.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.599 ; -7.599 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.388 ; -7.388 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.748 ; -7.748 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.068 ; -8.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.529 ; -7.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.935 ; -7.935 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.329 ; -7.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.722 ; -7.722 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.583 ; -7.583 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.247 ; -7.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.589 ; -7.589 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.563 ; -7.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.698 ; -7.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.092 ; -4.092 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.942 ; -5.942 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_CTSn ; CRT_PIN4_CLK1 ; -3.983 ; -3.983 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_DCDn ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.699 ; -5.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CLK_PLL1      ; -4.017 ; -4.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_CTS        ; CLK_PLL1      ; -6.571 ; -6.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -6.854 ; -6.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -6.698 ; -6.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[4]     ; CLK_PLL1      ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[6]     ; CLK_PLL1      ; -4.881 ; -4.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN3       ; CLK_PLL1      ; -2.948 ; -2.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -2.668 ; -2.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.559 ; -4.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -4.229 ; -4.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -4.249 ; -4.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -4.657 ; -4.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -4.303 ; -4.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.154 ; -4.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn         ; CLK_PLL1      ; -4.256 ; -4.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.102 ; -5.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -5.002 ; -5.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.116 ; -7.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.253 ; -7.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.416 ; -4.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -7.313 ; -7.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.830 ; -5.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.243 ; -6.243 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.411 ; -6.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.156 ; -7.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.626 ; -6.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.039 ; -4.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -3.980 ; -3.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.057 ; -4.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.185 ; -4.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.275 ; -4.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.044 ; -4.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.973 ; -3.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.083 ; -4.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -3.866 ; -3.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.960 ; -3.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.037 ; -4.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.799 ; -3.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.786 ; -3.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -3.483 ; -3.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.530 ; -5.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.283 ; -5.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -5.037 ; -5.037 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -5.940 ; -5.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -6.026 ; -6.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.901 ; -4.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -5.489 ; -5.489 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CRT_PIN4_CLK1 ; -4.017 ; -4.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.571 ; -6.571 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.854 ; -6.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.698 ; -6.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[4]     ; CRT_PIN4_CLK1 ; -5.098 ; -5.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.186 ; -6.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -4.881 ; -4.881 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -2.948 ; -2.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -2.668 ; -2.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.559 ; -4.559 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.229 ; -4.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.249 ; -4.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.009 ; -4.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.657 ; -4.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.303 ; -4.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.154 ; -4.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -3.789 ; -3.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.699 ; -4.699 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.256 ; -4.256 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.102 ; -5.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.907 ; -4.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.002 ; -5.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.116 ; -7.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.253 ; -7.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.416 ; -4.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.313 ; -7.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.830 ; -5.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.243 ; -6.243 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.411 ; -6.411 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.421 ; -6.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.156 ; -7.156 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.635 ; -5.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.626 ; -6.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.482 ; -6.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.039 ; -4.039 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.775 ; -3.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.968 ; -3.968 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -3.980 ; -3.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.057 ; -4.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.185 ; -4.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.275 ; -4.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.044 ; -4.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.973 ; -3.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.083 ; -4.083 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -3.866 ; -3.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.960 ; -3.960 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -3.917 ; -3.917 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.037 ; -4.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.799 ; -3.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.786 ; -3.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.483 ; -3.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.530 ; -5.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.283 ; -5.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -5.037 ; -5.037 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.782 ; -7.782 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.940 ; -5.940 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.921 ; -5.921 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -6.026 ; -6.026 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.901 ; -4.901 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.489 ; -5.489 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CLK_PLL1      ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_CTS        ; CLK_PLL1      ; -6.604 ; -6.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_DCD        ; CLK_PLL1      ; -6.406 ; -6.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; COM_RI         ; CLK_PLL1      ; -6.887 ; -6.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.490 ; -7.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.482 ; -7.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[5]     ; CLK_PLL1      ; -7.657 ; -7.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  CONFIG[6]     ; CLK_PLL1      ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN3       ; CLK_PLL1      ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; CRT_PIN4_CLK1  ; CLK_PLL1      ; -4.502 ; -4.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CLK_PLL1      ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; -5.007 ; -5.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; -4.973 ; -4.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; -4.856 ; -4.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; -4.358 ; -4.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; -4.409 ; -4.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; -4.930 ; -4.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; -4.343 ; -4.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; -4.422 ; -4.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; -4.197 ; -4.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; -3.738 ; -3.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; -3.593 ; -3.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; -3.585 ; -3.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; -3.745 ; -3.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; FC[*]          ; CLK_PLL1      ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[0]         ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[1]         ; CLK_PLL1      ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  FC[2]         ; CLK_PLL1      ; -5.555 ; -5.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; HDINTn         ; CLK_PLL1      ; -7.451 ; -7.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.588 ; -7.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LDSn           ; CLK_PLL1      ; -5.242 ; -5.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_BSY        ; CLK_PLL1      ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.828 ; -5.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.936 ; -5.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.444 ; -6.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; -4.035 ; -4.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.302 ; -6.302 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.344 ; -7.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -8.331 ; -8.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -8.585 ; -8.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.464 ; -7.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.614 ; -6.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.573 ; -7.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.629 ; -7.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -8.049 ; -8.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.368 ; -7.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -6.945 ; -6.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.254 ; -7.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.048 ; -7.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.069 ; -7.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RWn            ; CLK_PLL1      ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; SD_RESETn      ; CLK_PLL1      ; -5.648 ; -5.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; UDSn           ; CLK_PLL1      ; -5.333 ; -5.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; ASn            ; CRT_PIN4_CLK1 ; -3.859 ; -3.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_CTS        ; CRT_PIN4_CLK1 ; -6.604 ; -6.604 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -6.406 ; -6.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -6.887 ; -6.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.490 ; -7.490 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.482 ; -7.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -7.657 ; -7.657 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  CONFIG[6]     ; CRT_PIN4_CLK1 ; -6.942 ; -6.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN3       ; CRT_PIN4_CLK1 ; -4.775 ; -4.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; CRT_PIN4_CLK1  ; CRT_PIN4_CLK1 ; -4.502 ; -4.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -5.007 ; -5.007 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.973 ; -4.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.856 ; -4.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.358 ; -4.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.409 ; -4.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.930 ; -4.930 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.343 ; -4.343 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.422 ; -4.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -4.197 ; -4.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -3.738 ; -3.738 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -3.894 ; -3.894 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -3.593 ; -3.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -3.585 ; -3.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -3.745 ; -3.745 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -3.449 ; -3.449 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.191 ; -5.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.555 ; -5.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.451 ; -7.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.588 ; -7.588 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.242 ; -5.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.828 ; -5.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.936 ; -5.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.444 ; -6.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -4.035 ; -4.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -3.892 ; -3.892 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -3.951 ; -3.951 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -3.901 ; -3.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.302 ; -6.302 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.344 ; -7.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -8.331 ; -8.331 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -8.585 ; -8.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.464 ; -7.464 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.614 ; -6.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.573 ; -7.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.629 ; -7.629 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -8.049 ; -8.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.368 ; -7.368 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -6.945 ; -6.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.254 ; -7.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -6.599 ; -6.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.048 ; -7.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.069 ; -7.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.332 ; -7.332 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -3.825 ; -3.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.648 ; -5.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.333 ; -5.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 17.960 ; 17.960 ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 19.332 ; 19.332 ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 17.245 ; 17.245 ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 28.915 ; 28.915 ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 26.517 ; 26.517 ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 26.851 ; 26.851 ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 22.159 ; 22.159 ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 26.602 ; 26.602 ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 28.818 ; 28.818 ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 28.915 ; 28.915 ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 28.599 ; 28.599 ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 21.778 ; 21.778 ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 26.541 ; 26.541 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 24.161 ; 24.161 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 24.398 ; 24.398 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 22.966 ; 22.966 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 23.681 ; 23.681 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 23.422 ; 23.422 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 23.275 ; 23.275 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 23.027 ; 23.027 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 23.632 ; 23.632 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 25.957 ; 25.957 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 25.386 ; 25.386 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 25.569 ; 25.569 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 25.144 ; 25.144 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 24.382 ; 24.382 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 24.379 ; 24.379 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 26.541 ; 26.541 ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 25.907 ; 25.907 ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 7.237  ; 7.237  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 28.185 ; 28.185 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 26.248 ; 26.248 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 25.831 ; 25.831 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.549 ; 25.549 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 25.635 ; 25.635 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 26.315 ; 26.315 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.291 ; 25.291 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 26.613 ; 26.613 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 27.350 ; 27.350 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 28.185 ; 28.185 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 27.173 ; 27.173 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 25.916 ; 25.916 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 25.970 ; 25.970 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 25.794 ; 25.794 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 25.093 ; 25.093 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 26.548 ; 26.548 ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 26.160 ; 26.160 ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 13.209 ; 13.209 ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 7.234  ; 7.234  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 7.374  ; 7.374  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 22.837 ; 22.837 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 20.234 ; 20.234 ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 22.837 ; 22.837 ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 23.952 ; 23.952 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 23.952 ; 23.952 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 23.090 ; 23.090 ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 21.559 ; 21.559 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 18.837 ; 18.837 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 20.763 ; 20.763 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 19.000 ; 19.000 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 19.117 ; 19.117 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 18.080 ; 18.080 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 19.146 ; 19.146 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 17.941 ; 17.941 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 18.746 ; 18.746 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 20.179 ; 20.179 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 20.498 ; 20.498 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 20.351 ; 20.351 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 20.178 ; 20.178 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 21.473 ; 21.473 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 21.559 ; 21.559 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 21.522 ; 21.522 ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 21.363 ; 21.363 ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 22.885 ; 22.885 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 20.924 ; 20.924 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 22.196 ; 22.196 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 21.583 ; 21.583 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 21.071 ; 21.071 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 20.973 ; 20.973 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 21.162 ; 21.162 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 21.527 ; 21.527 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 22.464 ; 22.464 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 22.407 ; 22.407 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 22.285 ; 22.285 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 20.698 ; 20.698 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 21.004 ; 21.004 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 22.885 ; 22.885 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 22.273 ; 22.273 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 21.529 ; 21.529 ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 21.616 ; 21.616 ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.031 ; 13.031 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.460 ; 20.460 ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.604 ; 17.604 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 20.207 ; 20.207 ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 9.333  ; 9.333  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 21.322 ; 21.322 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.031 ; 13.031 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.941 ; 12.941 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.126 ; 12.126 ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.460 ; 20.460 ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 9.671  ; 9.671  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 35.030 ; 35.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 36.402 ; 36.402 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 19.599 ; 19.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.151 ; 19.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 19.321 ; 19.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 21.575 ; 21.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.986 ; 19.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 19.875 ; 19.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 19.625 ; 19.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 18.840 ; 18.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 18.957 ; 18.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 19.675 ; 19.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 18.709 ; 18.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 20.276 ; 20.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 20.690 ; 20.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 21.103 ; 21.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 21.165 ; 21.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 20.964 ; 20.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 20.749 ; 20.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 20.436 ; 20.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 21.613 ; 21.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 21.758 ; 21.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 21.219 ; 21.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 11.448 ; 11.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 7.109  ; 7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 7.600  ; 7.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 34.315 ; 34.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 43.587 ; 43.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 43.921 ; 43.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 39.229 ; 39.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 43.672 ; 43.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 45.888 ; 45.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 45.669 ; 45.669 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 38.848 ; 38.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 38.659 ; 38.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 39.090 ; 39.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 38.707 ; 38.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 38.618 ; 38.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 37.581 ; 37.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 38.498 ; 38.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 38.503 ; 38.503 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 37.977 ; 37.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 39.989 ; 39.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 39.809 ; 39.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 41.044 ; 41.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 40.130 ; 40.130 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 39.804 ; 39.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 40.376 ; 40.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 40.552 ; 40.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 9.165  ; 9.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 10.616 ; 10.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 21.732 ; 21.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 21.608 ; 21.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 20.873 ; 20.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 27.922 ; 27.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 28.477 ; 28.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 13.877 ; 13.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 28.488 ; 28.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 27.524 ; 27.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 28.153 ; 28.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 27.768 ; 27.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 27.522 ; 27.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 28.949 ; 28.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 30.672 ; 30.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 29.247 ; 29.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 29.399 ; 29.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 30.235 ; 30.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 10.624 ; 10.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.203  ; 9.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 8.717  ; 8.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 18.993 ; 18.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.715  ; 8.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 7.971  ; 7.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.725  ; 8.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 9.088  ; 9.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 8.053  ; 8.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 23.991 ; 23.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 25.046 ; 25.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 25.899 ; 25.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 27.749 ; 27.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 27.475 ; 27.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.186 ; 25.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 26.054 ; 26.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 23.945 ; 23.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 26.864 ; 26.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 25.107 ; 25.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 25.339 ; 25.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 28.144 ; 28.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 31.748 ; 31.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 30.492 ; 30.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 40.746 ; 40.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 40.523 ; 40.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 41.290 ; 41.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 40.572 ; 40.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 40.474 ; 40.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 40.514 ; 40.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 42.089 ; 42.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 41.695 ; 41.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 41.596 ; 41.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 41.391 ; 41.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 40.956 ; 40.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 41.216 ; 41.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 41.090 ; 41.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 41.315 ; 41.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 40.805 ; 40.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 30.803 ; 30.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 31.059 ; 31.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 31.045 ; 31.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 30.596 ; 30.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 31.780 ; 31.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 31.623 ; 31.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 13.001 ; 13.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 26.327 ; 26.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 26.421 ; 26.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 26.092 ; 26.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 27.267 ; 27.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 25.526 ; 25.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 9.489  ; 9.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.356  ; 8.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 7.059  ; 7.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 7.982  ; 7.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 7.586  ; 7.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 8.669  ; 8.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 8.594  ; 8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 10.611 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 9.812  ; 9.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 8.073  ; 8.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 8.125  ; 8.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 7.904  ; 7.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 19.298 ; 19.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 15.825 ; 15.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 15.928 ; 15.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 22.138 ; 22.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 23.510 ; 23.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 16.764 ; 16.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 21.423 ; 20.673 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 30.695 ; 30.695 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 31.029 ; 31.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 26.337 ; 26.337 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 30.780 ; 30.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 32.996 ; 32.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 32.777 ; 32.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 25.956 ; 25.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 25.657 ; 25.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 25.815 ; 25.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 25.726 ; 25.726 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 24.738 ; 24.775 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 25.692 ; 25.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 25.611 ; 25.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 24.914 ; 25.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 27.097 ; 27.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 27.003 ; 26.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 28.152 ; 28.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 27.238 ; 27.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 26.912 ; 26.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 27.484 ; 27.484 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 27.740 ; 27.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 14.457 ; 14.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 15.012 ; 15.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 15.596 ; 15.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 14.632 ; 14.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 15.261 ; 15.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 14.876 ; 14.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 14.630 ; 14.626 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 16.057 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 17.780 ; 17.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 16.355 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 15.757 ; 16.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 16.593 ; 17.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 11.518 ; 11.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 17.852 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 12.041 ; 12.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 12.891 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.282 ; 13.282 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.217 ; 13.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 15.025 ; 15.025 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 15.145 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 12.604 ; 12.604 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 12.568 ; 12.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 17.852 ; 14.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 14.319 ; 11.441 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.923 ; 15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 13.789 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 28.217 ; 28.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 27.631 ; 27.631 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 28.398 ; 28.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 27.680 ; 27.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 27.631 ; 27.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 27.708 ; 27.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 29.197 ; 29.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 28.632 ; 28.889 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 28.790 ; 28.649 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 28.064 ; 28.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 28.324 ; 28.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 28.198 ; 28.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 28.506 ; 28.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 27.993 ; 27.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 16.978 ; 14.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 17.234 ; 14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 14.342 ; 17.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 13.893 ; 16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 17.955 ; 15.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 14.920 ; 17.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 13.338 ; 9.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 12.293 ; 13.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 13.698 ; 14.133 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 12.951 ; 13.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 12.660 ; 12.558 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 13.557 ; 13.027 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 12.057 ; 12.634 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 11.821 ; 11.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 35.030 ; 35.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 36.402 ; 36.402 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 19.599 ; 19.599 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.151 ; 19.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 19.321 ; 19.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 21.575 ; 21.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.986 ; 19.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 19.875 ; 19.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 19.625 ; 19.625 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 18.840 ; 18.840 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 18.957 ; 18.957 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 19.675 ; 19.675 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 18.709 ; 18.709 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 20.276 ; 20.276 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 20.690 ; 20.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 21.103 ; 21.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 21.165 ; 21.165 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 20.964 ; 20.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 20.749 ; 20.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 20.436 ; 20.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 21.956 ; 21.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 21.613 ; 21.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 21.758 ; 21.758 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 21.219 ; 21.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 11.448 ; 11.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 5.649  ; 5.649  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 7.109  ; 7.109  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 7.600  ; 7.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 7.773  ; 7.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 29.656 ; 29.656 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 34.315 ; 34.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 43.587 ; 43.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 43.921 ; 43.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 39.229 ; 39.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 43.672 ; 43.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 45.888 ; 45.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 45.985 ; 45.985 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 45.669 ; 45.669 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 38.848 ; 38.848 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 5.112  ; 5.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 6.148  ; 6.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 8.892  ; 8.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 6.798  ; 6.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 7.471  ; 7.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 38.659 ; 38.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 39.090 ; 39.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 38.707 ; 38.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 38.618 ; 38.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 37.581 ; 37.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 38.498 ; 38.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 38.503 ; 38.503 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 37.977 ; 37.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 39.989 ; 39.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 39.809 ; 39.809 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 41.044 ; 41.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 40.130 ; 40.130 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 39.804 ; 39.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 40.376 ; 40.376 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 41.308 ; 41.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 40.552 ; 40.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 9.165  ; 9.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 10.616 ; 10.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.689  ; 6.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 5.548  ; 5.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 21.732 ; 21.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 21.608 ; 21.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 22.340 ; 22.340 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 6.942  ; 6.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 8.689  ; 8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 7.562  ; 7.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 6.841  ; 6.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 6.045  ; 6.045  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 7.466  ; 7.466  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 21.262 ; 21.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 20.873 ; 20.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 27.922 ; 27.922 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 28.477 ; 28.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 6.734  ; 6.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 5.914  ; 5.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 13.877 ; 13.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 28.488 ; 28.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 27.524 ; 27.524 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 28.153 ; 28.153 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 27.768 ; 27.768 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 27.522 ; 27.522 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 28.949 ; 28.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 30.672 ; 30.672 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 29.247 ; 29.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 29.399 ; 29.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 30.235 ; 30.235 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 10.624 ; 10.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.203  ; 9.203  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 8.717  ; 8.717  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 18.993 ; 18.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.258  ; 7.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.925  ; 6.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 6.019  ; 6.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 6.802  ; 6.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.598  ; 6.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.715  ; 8.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 7.971  ; 7.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.725  ; 8.725  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.775  ; 9.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.688  ; 7.688  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 9.088  ; 9.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 8.053  ; 8.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 23.991 ; 23.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 25.046 ; 25.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 25.899 ; 25.899 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 25.882 ; 25.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 27.749 ; 27.749 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 27.475 ; 27.475 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.186 ; 25.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 26.054 ; 26.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 31.677 ; 31.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 23.945 ; 23.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 26.864 ; 26.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 25.107 ; 25.107 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 25.339 ; 25.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 29.498 ; 29.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 28.144 ; 28.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 31.748 ; 31.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 30.492 ; 30.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 40.746 ; 40.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 40.523 ; 40.523 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 41.290 ; 41.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 40.572 ; 40.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 40.474 ; 40.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 40.514 ; 40.514 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 42.089 ; 42.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 41.695 ; 41.695 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 42.217 ; 42.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 41.596 ; 41.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 41.391 ; 41.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 40.956 ; 40.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 41.216 ; 41.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 41.090 ; 41.090 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 41.315 ; 41.315 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 40.805 ; 40.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 30.803 ; 30.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 31.059 ; 31.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 31.045 ; 31.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 30.596 ; 30.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 31.780 ; 31.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 31.623 ; 31.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 13.001 ; 13.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 26.327 ; 26.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 27.163 ; 27.163 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 26.421 ; 26.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 26.092 ; 26.092 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 27.267 ; 27.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 25.526 ; 25.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 9.489  ; 9.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.866  ; 8.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.502  ; 8.502  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.356  ; 8.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 10.820 ; 10.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 7.034  ; 7.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 7.059  ; 7.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 7.982  ; 7.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 8.148  ; 8.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 7.586  ; 7.586  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.495  ; 5.495  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 8.669  ; 8.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 4.739  ; 4.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.252  ; 5.252  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 10.823 ; 10.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 8.594  ; 8.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 10.611 ; 10.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.938  ; 9.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 7.826  ; 7.826  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 9.812  ; 9.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 7.572  ; 7.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 8.073  ; 8.073  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.303  ; 8.303  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 8.125  ; 8.125  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 7.904  ; 7.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 19.298 ; 19.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 7.093  ; 7.093  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 5.793  ; 5.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.607  ; 7.607  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 14.836 ; 14.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 15.825 ; 15.825 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 15.928 ; 15.928 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 22.138 ; 22.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 23.510 ; 23.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 9.402  ; 9.402  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 16.764 ; 16.014 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 21.423 ; 20.673 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 30.695 ; 30.695 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 31.029 ; 31.029 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 26.337 ; 26.337 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 30.780 ; 30.780 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 32.996 ; 32.996 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 33.093 ; 33.093 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 32.777 ; 32.777 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 25.956 ; 25.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 25.657 ; 25.767 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 26.198 ; 26.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 25.815 ; 25.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 25.726 ; 25.726 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 24.738 ; 24.775 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 25.692 ; 25.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 25.611 ; 25.611 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 24.914 ; 25.171 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 27.097 ; 27.097 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 27.003 ; 26.862 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 28.152 ; 28.152 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 27.238 ; 27.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 26.912 ; 26.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 27.484 ; 27.484 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 27.740 ; 27.740 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 8.538  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 8.299  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 14.457 ; 14.892 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 15.012 ; 15.447 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 15.596 ; 15.593 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 14.632 ; 14.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 15.261 ; 15.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 14.876 ; 14.872 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 14.630 ; 14.626 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 16.057 ; 16.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 17.780 ; 17.030 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 16.355 ; 15.605 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 15.757 ; 16.507 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 16.593 ; 17.343 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.518 ; 11.518 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 17.852 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 12.041 ; 12.041 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 12.891 ; 12.891 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.282 ; 13.282 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.217 ; 13.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 15.025 ; 15.025 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 15.145 ; 15.145 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 12.604 ; 12.604 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 12.568 ; 12.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 17.852 ; 14.974 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.325 ; 12.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.907 ; 14.907 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.493 ; 13.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 15.673 ; 12.795 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 14.319 ; 11.441 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.923 ; 15.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 13.789 ; 16.667 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 28.217 ; 28.217 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 27.631 ; 27.631 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 28.398 ; 28.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 27.680 ; 27.680 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 27.631 ; 27.668 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 27.708 ; 27.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 29.197 ; 29.197 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 28.632 ; 28.889 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 29.325 ; 29.325 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 28.790 ; 28.649 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 28.499 ; 28.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 28.064 ; 28.064 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 28.324 ; 28.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 28.198 ; 28.198 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 28.506 ; 28.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 27.993 ; 27.993 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 16.978 ; 14.100 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 17.234 ; 14.356 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 14.342 ; 17.220 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 13.893 ; 16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 17.955 ; 15.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 14.920 ; 17.798 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 13.338 ; 9.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 12.293 ; 13.603 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 13.698 ; 14.133 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 12.951 ; 13.529 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 12.660 ; 12.558 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 13.557 ; 13.027 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 12.057 ; 12.634 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.821 ; 11.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 14.859 ; 14.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 23.416 ; 23.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 23.750 ; 23.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 19.058 ; 19.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 23.501 ; 23.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 25.717 ; 25.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 25.498 ; 25.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.677 ; 18.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 8.017  ; 8.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 8.899  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 7.953  ; 7.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 16.178 ; 16.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 8.128  ; 8.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 8.633  ; 8.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 21.060 ; 21.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 21.297 ; 21.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 19.865 ; 19.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 20.580 ; 20.580 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 20.321 ; 20.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 20.174 ; 20.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 19.926 ; 19.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 20.531 ; 20.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 22.856 ; 22.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 22.285 ; 22.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 22.468 ; 22.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 22.043 ; 22.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 21.281 ; 21.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 21.278 ; 21.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 22.806 ; 22.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 9.023  ; 9.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 9.617  ; 9.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 8.579  ; 8.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 13.618 ; 13.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 13.886 ; 13.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 13.309 ; 13.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 13.797 ; 13.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 13.418 ; 13.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 13.002 ; 13.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 15.065 ; 15.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 12.834 ; 12.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 24.963 ; 24.963 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 25.020 ; 25.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 23.431 ; 23.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 24.598 ; 24.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 25.176 ; 25.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 24.927 ; 24.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 24.249 ; 24.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 24.552 ; 24.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 23.478 ; 23.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 23.996 ; 23.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 23.306 ; 23.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 24.401 ; 24.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 23.447 ; 23.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 23.438 ; 23.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 13.708 ; 13.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 13.964 ; 13.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 13.948 ; 13.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 13.499 ; 13.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 13.071 ; 13.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.916 ; 12.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 12.255 ; 12.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 11.384 ; 11.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 10.015 ; 10.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 11.172 ; 11.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 9.919  ; 9.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 14.859 ; 14.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.193  ; 8.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.653  ; 6.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 6.464  ; 6.464  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 14.144 ; 14.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 23.416 ; 23.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 23.750 ; 23.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 19.058 ; 19.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 23.501 ; 23.501 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 25.717 ; 25.717 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 25.814 ; 25.814 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 25.498 ; 25.498 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.677 ; 18.677 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.902  ; 8.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 8.017  ; 8.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 7.935  ; 7.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 8.899  ; 8.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 7.919  ; 7.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 7.953  ; 7.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 7.616  ; 7.616  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 8.253  ; 8.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 16.178 ; 16.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 9.358  ; 9.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 8.128  ; 8.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 8.633  ; 8.633  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 21.060 ; 21.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 21.297 ; 21.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 19.865 ; 19.865 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 20.580 ; 20.580 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 20.321 ; 20.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 20.174 ; 20.174 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 19.926 ; 19.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 20.531 ; 20.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 22.856 ; 22.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 22.285 ; 22.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 22.468 ; 22.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 22.043 ; 22.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 21.281 ; 21.281 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 21.278 ; 21.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 23.440 ; 23.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 22.806 ; 22.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 9.023  ; 9.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 9.617  ; 9.617  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 7.004  ; 7.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 8.579  ; 8.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 11.867 ; 11.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 13.618 ; 13.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 13.886 ; 13.886 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 13.309 ; 13.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 13.797 ; 13.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.025 ; 16.025 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 13.418 ; 13.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 12.262 ; 12.262 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 13.002 ; 13.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 15.065 ; 15.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 12.834 ; 12.834 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.908 ; 10.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 13.395 ; 13.395 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 25.796 ; 25.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 24.963 ; 24.963 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 25.020 ; 25.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 23.431 ; 23.431 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 24.598 ; 24.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 25.176 ; 25.176 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 24.927 ; 24.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 24.249 ; 24.249 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 25.104 ; 25.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 24.552 ; 24.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 23.478 ; 23.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 23.996 ; 23.996 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 23.306 ; 23.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 24.401 ; 24.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 23.447 ; 23.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 23.438 ; 23.438 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 13.708 ; 13.708 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 13.964 ; 13.964 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 13.948 ; 13.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 13.499 ; 13.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 13.071 ; 13.071 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.916 ; 12.916 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.255 ; 12.255 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 12.640 ; 12.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 7.338  ; 7.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 9.292  ; 9.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 11.384 ; 11.384 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 9.805  ; 9.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 10.015 ; 10.015 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 11.172 ; 11.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 9.919  ; 9.919  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 2.964  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 6.920  ; 6.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 6.490  ; 6.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 6.183  ; 6.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 7.855  ; 7.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 2.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 31.216 ; 31.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 31.517 ; 31.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 29.973 ; 29.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 31.037 ; 31.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 30.837 ; 30.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 31.452 ; 31.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 30.416 ; 30.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 30.391 ; 30.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 31.794 ; 31.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 31.977 ; 31.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 32.606 ; 32.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 32.079 ; 32.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 32.448 ; 32.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 30.068 ; 30.068 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 29.069 ; 29.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 12.280 ; 12.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 11.463 ; 11.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 33.303 ; 33.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 32.950 ; 32.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 32.556 ; 32.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 32.991 ; 32.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 33.730 ; 33.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.468 ; 33.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 34.002 ; 34.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 34.109 ; 34.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 34.022 ; 34.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 33.764 ; 33.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 33.432 ; 33.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 33.491 ; 33.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 33.162 ; 33.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 30.075 ; 30.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 29.322 ; 29.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 31.216 ; 31.216 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 31.517 ; 31.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 29.973 ; 29.973 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 31.037 ; 31.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 30.837 ; 30.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 31.452 ; 31.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 30.416 ; 30.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 30.391 ; 30.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 31.794 ; 31.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 31.977 ; 31.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 33.870 ; 33.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 32.606 ; 32.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 32.079 ; 32.079 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 32.448 ; 32.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 30.068 ; 30.068 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 29.069 ; 29.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 12.280 ; 12.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 11.463 ; 11.463 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 13.137 ; 13.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 33.303 ; 33.303 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 32.950 ; 32.950 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 32.556 ; 32.556 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 32.991 ; 32.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 33.730 ; 33.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.468 ; 33.468 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 34.002 ; 34.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 34.109 ; 34.109 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 34.022 ; 34.022 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 33.764 ; 33.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 34.217 ; 34.217 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 33.432 ; 33.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 33.491 ; 33.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 33.162 ; 33.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 30.075 ; 30.075 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 29.322 ; 29.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; ACSI_RDn       ; CLK_PLL1      ; 7.204  ; 7.204  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.833  ; 7.833  ; Rise       ; CLK_PLL1                                                   ;
; CA1_OUT        ; CLK_PLL1      ; 7.757  ; 7.757  ; Rise       ; CLK_PLL1                                                   ;
; CD[*]          ; CLK_PLL1      ; 7.413  ; 7.413  ; Rise       ; CLK_PLL1                                                   ;
;  CD[0]         ; CLK_PLL1      ; 8.162  ; 8.162  ; Rise       ; CLK_PLL1                                                   ;
;  CD[1]         ; CLK_PLL1      ; 8.269  ; 8.269  ; Rise       ; CLK_PLL1                                                   ;
;  CD[2]         ; CLK_PLL1      ; 7.565  ; 7.565  ; Rise       ; CLK_PLL1                                                   ;
;  CD[3]         ; CLK_PLL1      ; 8.167  ; 8.167  ; Rise       ; CLK_PLL1                                                   ;
;  CD[4]         ; CLK_PLL1      ; 7.725  ; 7.725  ; Rise       ; CLK_PLL1                                                   ;
;  CD[5]         ; CLK_PLL1      ; 7.934  ; 7.934  ; Rise       ; CLK_PLL1                                                   ;
;  CD[6]         ; CLK_PLL1      ; 7.893  ; 7.893  ; Rise       ; CLK_PLL1                                                   ;
;  CD[7]         ; CLK_PLL1      ; 7.413  ; 7.413  ; Rise       ; CLK_PLL1                                                   ;
; DATA[*]        ; CLK_PLL1      ; 7.447  ; 7.447  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[0]       ; CLK_PLL1      ; 7.727  ; 7.727  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[1]       ; CLK_PLL1      ; 8.047  ; 8.047  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[2]       ; CLK_PLL1      ; 7.478  ; 7.478  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[3]       ; CLK_PLL1      ; 7.980  ; 7.980  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[4]       ; CLK_PLL1      ; 7.632  ; 7.632  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[5]       ; CLK_PLL1      ; 7.736  ; 7.736  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[6]       ; CLK_PLL1      ; 7.447  ; 7.447  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[7]       ; CLK_PLL1      ; 7.658  ; 7.658  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[8]       ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[9]       ; CLK_PLL1      ; 8.260  ; 8.260  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[10]      ; CLK_PLL1      ; 8.550  ; 8.550  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[11]      ; CLK_PLL1      ; 8.515  ; 8.515  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[12]      ; CLK_PLL1      ; 8.013  ; 8.013  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[13]      ; CLK_PLL1      ; 8.133  ; 8.133  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[14]      ; CLK_PLL1      ; 8.669  ; 8.669  ; Rise       ; CLK_PLL1                                                   ;
;  DATA[15]      ; CLK_PLL1      ; 8.335  ; 8.335  ; Rise       ; CLK_PLL1                                                   ;
; PLL_FAULT      ; CLK_PLL1      ; 3.721  ; 3.721  ; Rise       ; CLK_PLL1                                                   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 8.586  ; 8.586  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.675  ; 8.675  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.760  ; 8.760  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.607  ; 8.607  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.912  ; 8.912  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.867  ; 8.867  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.676  ; 8.676  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.023  ; 9.023  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 9.394  ; 9.394  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.345  ; 9.345  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 9.144  ; 9.144  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.829  ; 8.829  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 9.015  ; 9.015  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.674  ; 8.674  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.587  ; 8.587  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.757  ; 8.757  ; Rise       ; CLK_PLL1                                                   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.586  ; 8.586  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 6.177  ; 6.177  ; Rise       ; CLK_PLL1                                                   ;
; CODEC_SDOUT    ; CODEC_SCLK    ; 3.434  ; 3.434  ; Rise       ; CODEC_SCLK                                                 ;
; CODEC_SSYNC    ; CODEC_SCLK    ; 3.514  ; 3.514  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 8.374  ; 8.374  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 8.374  ; 8.374  ; Rise       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 9.398  ; 9.398  ; Rise       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 9.649  ; 9.649  ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 10.110 ; 10.110 ; Rise       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 9.649  ; 9.649  ; Rise       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CODEC_SCLK    ; 6.384  ; 6.384  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[0]       ; CODEC_SCLK    ; 6.486  ; 6.486  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[1]       ; CODEC_SCLK    ; 6.970  ; 6.970  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[2]       ; CODEC_SCLK    ; 6.593  ; 6.593  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[3]       ; CODEC_SCLK    ; 6.742  ; 6.742  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[4]       ; CODEC_SCLK    ; 6.641  ; 6.641  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[5]       ; CODEC_SCLK    ; 7.001  ; 7.001  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[6]       ; CODEC_SCLK    ; 6.384  ; 6.384  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[7]       ; CODEC_SCLK    ; 6.733  ; 6.733  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[8]       ; CODEC_SCLK    ; 7.375  ; 7.375  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[9]       ; CODEC_SCLK    ; 6.858  ; 6.858  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[10]      ; CODEC_SCLK    ; 7.591  ; 7.591  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[11]      ; CODEC_SCLK    ; 7.466  ; 7.466  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[12]      ; CODEC_SCLK    ; 6.947  ; 6.947  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[13]      ; CODEC_SCLK    ; 7.298  ; 7.298  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[14]      ; CODEC_SCLK    ; 7.927  ; 7.927  ; Fall       ; CODEC_SCLK                                                 ;
;  DATA[15]      ; CODEC_SCLK    ; 7.166  ; 7.166  ; Fall       ; CODEC_SCLK                                                 ;
; RAM_DATA[*]    ; CODEC_SCLK    ; 7.417  ; 7.417  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[0]   ; CODEC_SCLK    ; 7.434  ; 7.434  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[1]   ; CODEC_SCLK    ; 7.683  ; 7.683  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[2]   ; CODEC_SCLK    ; 7.722  ; 7.722  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[3]   ; CODEC_SCLK    ; 7.674  ; 7.674  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[4]   ; CODEC_SCLK    ; 7.876  ; 7.876  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[5]   ; CODEC_SCLK    ; 7.941  ; 7.941  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[6]   ; CODEC_SCLK    ; 7.960  ; 7.960  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[7]   ; CODEC_SCLK    ; 8.469  ; 8.469  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[8]   ; CODEC_SCLK    ; 8.420  ; 8.420  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[9]   ; CODEC_SCLK    ; 7.742  ; 7.742  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[10]  ; CODEC_SCLK    ; 7.870  ; 7.870  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[11]  ; CODEC_SCLK    ; 7.966  ; 7.966  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[12]  ; CODEC_SCLK    ; 7.608  ; 7.608  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[13]  ; CODEC_SCLK    ; 7.752  ; 7.752  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[14]  ; CODEC_SCLK    ; 8.015  ; 8.015  ; Fall       ; CODEC_SCLK                                                 ;
;  RAM_DATA[15]  ; CODEC_SCLK    ; 7.417  ; 7.417  ; Fall       ; CODEC_SCLK                                                 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Rise       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Rise       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.549  ; 5.549  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Rise       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.358  ; 5.358  ; Rise       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Rise       ; CRT_PIN4_CLK1                                              ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.214  ; 8.214  ; Fall       ; CRT_PIN4_CLK1                                              ;
; HSYNC          ; CRT_PIN4_CLK1 ; 4.264  ; 4.264  ; Fall       ; CRT_PIN4_CLK1                                              ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.926  ; 8.926  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.549  ; 5.549  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.643  ; 5.643  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 5.248  ; 5.248  ; Fall       ; CRT_PIN4_CLK1                                              ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.358  ; 5.358  ; Fall       ; CRT_PIN4_CLK1                                              ;
; VSYNC          ; CRT_PIN4_CLK1 ; 4.342  ; 4.342  ; Fall       ; CRT_PIN4_CLK1                                              ;
; ACSI_RDn       ; CLK_PLL1      ; 4.016  ; 4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 4.645  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 3.768  ; 3.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 3.700  ; 3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 3.624  ; 3.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 2.817  ; 2.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 3.003  ; 3.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 3.112  ; 3.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 3.352  ; 3.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.226  ; 4.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 2.950  ; 2.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.572  ; 4.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 4.348  ; 4.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.057  ; 3.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.398  ; 3.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 3.595  ; 3.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL1      ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 2.836  ; 2.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SDATA      ; CLK_PLL1      ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SYNCn      ; CLK_PLL1      ; 3.873  ; 3.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 3.239  ; 3.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 3.172  ; 3.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 3.124  ; 3.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 2.848  ; 2.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 2.845  ; 2.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 2.690  ; 2.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.604  ; 2.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.570  ; 2.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.679  ; 2.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 2.834  ; 2.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.792  ; 2.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 3.988  ; 3.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.306  ; 3.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.532  ; 3.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 2.984  ; 2.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 2.661  ; 2.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 2.868  ; 2.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 2.561  ; 2.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.186  ; 3.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.668  ; 4.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.136  ; 4.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 5.171  ; 5.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 5.002  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.927  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.415  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 4.945  ; 5.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.452  ; 4.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.802  ; 4.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.939  ; 3.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 4.244  ; 4.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.381  ; 3.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.474  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.231  ; 3.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.023  ; 3.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.240  ; 3.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 3.501  ; 3.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.667  ; 2.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; PADRSTn        ; CLK_PLL1      ; 3.129  ; 3.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.013  ; 5.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.095  ; 5.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.835  ; 4.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.874  ; 5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.976  ; 4.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.837  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.915  ; 5.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.413  ; 5.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.319  ; 5.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.156  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.156  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.221  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.091  ; 5.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.076  ; 5.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.188  ; 5.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.115  ; 5.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.029  ; 5.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.201  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.202  ; 5.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.103  ; 5.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.163  ; 5.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.593  ; 4.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.498  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.948  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.777  ; 4.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.343  ; 4.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.234  ; 5.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.326  ; 5.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.631  ; 5.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.598  ; 5.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 4.730  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.536  ; 3.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.503  ; 4.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 3.792  ; 4.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.322  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.597  ; 3.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 3.982  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.039  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 2.708  ; 2.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.577  ; 2.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.429  ; 2.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.397  ; 2.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.324  ; 2.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.543  ; 2.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.643  ; 2.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.449  ; 2.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.715  ; 2.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.043  ; 3.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.844  ; 2.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.489  ; 3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.315  ; 3.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.301  ; 3.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.340  ; 3.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.378  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.330  ; 3.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 3.329  ; 3.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 3.161  ; 3.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.445  ; 5.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 6.074  ; 6.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.085  ; 3.244  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 5.632  ; 4.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 5.998  ; 6.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.403  ; 6.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 6.510  ; 6.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.848  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.408  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 5.966  ; 5.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.175  ; 6.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 4.812  ; 4.635  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 5.347  ; 4.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 4.809  ; 4.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 5.079  ; 5.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 5.349  ; 4.679  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 5.194  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 4.604  ; 4.740  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 5.784  ; 5.477  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 5.819  ; 5.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 5.295  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 5.229  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 5.476  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 5.143  ; 5.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.252  ; 5.252  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.051  ; 5.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 4.677  ; 4.073  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 4.886  ; 4.282  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 4.440  ; 4.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 4.169  ; 4.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 5.003  ; 5.171  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.834  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.759  ; 4.927  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 5.247  ; 5.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 5.049  ; 4.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.720  ; 4.452  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.534  ; 4.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.931  ; 3.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.148  ; 3.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 5.013  ; 5.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 5.095  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.868  ; 4.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 5.874  ; 5.874  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.976  ; 4.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 5.071  ; 5.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.054  ; 4.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.726  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 5.250  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.726  ; 4.416  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 6.192  ; 5.691  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 5.134  ; 5.606  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.076  ; 5.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 5.188  ; 5.188  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 5.115  ; 5.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.118  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.226  ; 5.226  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.035  ; 5.035  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 5.202  ; 5.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 5.250  ; 5.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.310  ; 5.163  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 4.740  ; 4.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.222  ; 4.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.995  ; 4.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.977  ; 4.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 5.114  ; 4.876  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.778  ; 5.277  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 5.871  ; 5.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.369  ; 5.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 5.198  ; 5.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 6.147  ; 5.674  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.641  ; 6.114  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.422  ; 3.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.236  ; 4.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.396  ; 3.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 3.742  ; 4.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.640  ; 3.597  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.378  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 3.454  ; 4.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.296  ; 3.725  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.016  ; 4.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 4.645  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 3.761  ; 3.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 3.768  ; 3.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 3.700  ; 3.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 3.614  ; 3.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 3.624  ; 3.624  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 3.419  ; 3.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 3.318  ; 3.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 3.354  ; 3.354  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 2.847  ; 2.847  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 2.817  ; 2.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 2.939  ; 2.939  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 3.003  ; 3.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 3.218  ; 3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 3.112  ; 3.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 3.352  ; 3.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.226  ; 4.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 3.946  ; 3.946  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 2.950  ; 2.950  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.468  ; 2.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.793  ; 2.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 3.496  ; 3.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.572  ; 4.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.348  ; 4.348  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.057  ; 3.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.398  ; 3.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 2.886  ; 2.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 3.595  ; 3.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 3.853  ; 3.853  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.294  ; 3.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CLK_AUX        ; CRT_PIN4_CLK1 ; 2.220  ; 2.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 2.629  ; 2.629  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 2.610  ; 2.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 2.836  ; 2.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.269  ; 3.269  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SDATA      ; CRT_PIN4_CLK1 ; 3.338  ; 3.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 3.873  ; 3.873  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 3.307  ; 3.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 3.239  ; 3.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 3.172  ; 3.172  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 3.007  ; 3.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 3.124  ; 3.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 2.848  ; 2.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 2.845  ; 2.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 2.690  ; 2.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.604  ; 2.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.570  ; 2.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.679  ; 2.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 2.834  ; 2.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.789  ; 2.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.792  ; 2.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 3.988  ; 3.988  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.957  ; 3.957  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 4.363  ; 4.363  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.858  ; 2.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.480  ; 2.480  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.306  ; 3.306  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.532  ; 3.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.219  ; 3.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 3.114  ; 3.114  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 3.144  ; 3.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 3.864  ; 3.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 3.404  ; 3.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 3.068  ; 3.068  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.676  ; 2.676  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 3.333  ; 3.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 2.984  ; 2.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 2.661  ; 2.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 2.868  ; 2.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 2.561  ; 2.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 2.615  ; 2.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.098  ; 3.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.186  ; 3.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.440  ; 3.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.668  ; 4.440  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.136  ; 4.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 5.171  ; 5.003  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 5.002  ; 4.834  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.927  ; 4.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.415  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 4.945  ; 5.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.452  ; 4.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.802  ; 4.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.939  ; 3.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 4.244  ; 4.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.381  ; 3.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 2.824  ; 2.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.474  ; 3.474  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.365  ; 3.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.231  ; 3.148  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.173  ; 3.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.065  ; 3.065  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.052  ; 3.052  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.940  ; 2.940  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.175  ; 3.175  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.023  ; 3.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.240  ; 3.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 3.501  ; 3.501  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.429  ; 3.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.667  ; 2.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 3.129  ; 3.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.013  ; 5.013  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.095  ; 5.095  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.835  ; 4.835  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.874  ; 5.874  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.976  ; 4.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.837  ; 5.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.915  ; 5.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.413  ; 5.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.319  ; 5.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.156  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.156  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.221  ; 4.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.091  ; 5.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.076  ; 5.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.188  ; 5.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.115  ; 5.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.029  ; 5.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.201  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.202  ; 5.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.103  ; 5.250  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.163  ; 5.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.593  ; 4.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.498  ; 4.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.948  ; 5.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.777  ; 4.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.204  ; 4.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.343  ; 4.343  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.234  ; 5.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.327  ; 5.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.326  ; 5.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.155  ; 5.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.631  ; 5.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.598  ; 5.598  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.730  ; 4.730  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.536  ; 3.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.503  ; 4.236  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 3.792  ; 4.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.322  ; 3.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.597  ; 3.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 3.982  ; 4.378  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.039  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.078  ; 3.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 2.708  ; 2.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.577  ; 2.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.429  ; 2.429  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.397  ; 2.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.324  ; 2.324  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.279  ; 2.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.543  ; 2.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.643  ; 2.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.449  ; 2.449  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.565  ; 2.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.489  ; 2.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.715  ; 2.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.167  ; 2.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.404  ; 2.404  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.543  ; 3.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.043  ; 3.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 3.396  ; 3.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.844  ; 2.844  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.489  ; 3.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.383  ; 3.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 3.990  ; 3.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 3.253  ; 3.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.315  ; 3.315  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.301  ; 3.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.340  ; 3.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.264  ; 3.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.378  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 3.126  ; 3.126  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 2.558  ; 2.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.268  ; 3.268  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.330  ; 3.330  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 3.329  ; 3.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 3.161  ; 3.161  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.445  ; 5.445  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 6.074  ; 6.074  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.085  ; 3.244  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 5.632  ; 4.572  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.998  ; 6.164  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.403  ; 6.403  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 6.510  ; 6.510  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.848  ; 5.806  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.408  ; 6.408  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.966  ; 5.966  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.175  ; 6.175  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.134  ; 6.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.654  ; 5.654  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.812  ; 4.635  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.347  ; 4.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.809  ; 4.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.079  ; 5.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.349  ; 4.679  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.194  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.604  ; 4.740  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.301  ; 4.622  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 5.784  ; 5.477  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.819  ; 5.217  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.295  ; 5.909  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.229  ; 5.566  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.476  ; 5.646  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 5.143  ; 5.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.252  ; 5.252  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.051  ; 5.051  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 3.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 3.301  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 4.677  ; 4.073  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 4.886  ; 4.282  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 4.440  ; 4.668  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 4.169  ; 4.921  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 5.003  ; 5.171  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.834  ; 5.002  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.759  ; 4.927  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 5.247  ; 5.415  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 5.049  ; 4.945  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.720  ; 4.452  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.534  ; 4.802  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.931  ; 3.939  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.148  ; 3.578  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.805  ; 4.805  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 5.107  ; 5.107  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 5.013  ; 5.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 5.095  ; 5.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.868  ; 4.868  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 5.874  ; 5.874  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.976  ; 4.976  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 5.071  ; 5.071  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.054  ; 4.837  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 5.915  ; 5.915  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 5.413  ; 5.413  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 5.319  ; 5.319  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.726  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 5.250  ; 4.156  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.726  ; 4.416  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 6.192  ; 5.691  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 5.134  ; 5.606  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.076  ; 5.076  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 5.188  ; 5.188  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 5.115  ; 5.115  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.118  ; 5.118  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.226  ; 5.226  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 5.202  ; 5.202  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.053  ; 5.053  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 5.250  ; 5.103  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.310  ; 5.163  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 4.740  ; 4.593  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.645  ; 4.498  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.222  ; 4.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.995  ; 4.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.977  ; 4.739  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 5.114  ; 4.876  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.778  ; 5.277  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 5.871  ; 5.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.369  ; 5.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 5.198  ; 5.670  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 6.147  ; 5.674  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.641  ; 6.114  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.422  ; 3.536  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.236  ; 4.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.396  ; 3.792  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 3.742  ; 4.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.640  ; 3.597  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.378  ; 3.982  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 3.454  ; 4.039  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.296  ; 3.725  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 4.761  ; 4.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.390  ; 5.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGACKn         ; CLK_PLL1      ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BGOn           ; CLK_PLL1      ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 4.289  ; 4.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.122  ; 5.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 5.282  ; 5.282  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.450  ; 5.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 4.970  ; 4.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 2.697  ; 2.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.298  ; 3.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 2.830  ; 2.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 3.632  ; 3.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.292  ; 3.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 2.777  ; 2.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 2.945  ; 2.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 4.484  ; 4.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 4.704  ; 4.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 4.931  ; 4.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 4.765  ; 4.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.032  ; 5.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 4.978  ; 4.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 5.542  ; 5.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 5.240  ; 5.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.316  ; 5.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 4.952  ; 4.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 6.226  ; 6.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 3.369  ; 3.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 3.384  ; 3.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 3.415  ; 3.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.635  ; 3.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 3.894  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.775  ; 3.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 3.675  ; 3.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 3.564  ; 3.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 3.557  ; 3.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.434  ; 3.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.483  ; 4.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.051  ; 4.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 3.576  ; 3.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 3.842  ; 3.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 3.644  ; 3.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.011  ; 4.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 4.057  ; 4.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 3.639  ; 3.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 3.542  ; 3.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 3.483  ; 3.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 3.634  ; 3.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.989  ; 3.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 3.967  ; 3.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.797  ; 3.797  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 4.309  ; 4.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.283  ; 4.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.740  ; 3.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 4.650  ; 4.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.892  ; 3.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RDn       ; CLK_PLL1      ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_RSTn      ; CLK_PLL1      ; 4.043  ; 4.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SCSI_WRn       ; CLK_PLL1      ; 4.611  ; 4.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 1.262  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[3]  ; CLK_PLL1      ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[4]  ; CLK_PLL1      ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[5]  ; CLK_PLL1      ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[6]  ; CLK_PLL1      ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[7]  ; CLK_PLL1      ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 4.761  ; 4.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.390  ; 5.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.234  ; 3.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 2.861  ; 2.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 2.843  ; 2.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 5.314  ; 5.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 4.182  ; 4.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 4.289  ; 4.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.122  ; 5.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 4.187  ; 4.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.282  ; 5.282  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.491  ; 5.491  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.450  ; 5.450  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 4.970  ; 4.970  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 2.665  ; 2.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 2.697  ; 2.697  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.298  ; 3.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 2.668  ; 2.668  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 2.681  ; 2.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 2.677  ; 2.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 2.830  ; 2.830  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 3.632  ; 3.632  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.292  ; 3.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 2.732  ; 2.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 2.777  ; 2.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 2.945  ; 2.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.243  ; 4.243  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 4.484  ; 4.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 4.704  ; 4.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.931  ; 4.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.580  ; 4.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 4.765  ; 4.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.032  ; 5.032  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 4.978  ; 4.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.542  ; 5.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.550  ; 5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 5.240  ; 5.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.316  ; 5.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 4.952  ; 4.952  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.226  ; 6.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 3.369  ; 3.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.968  ; 2.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 3.104  ; 3.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 3.384  ; 3.384  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 3.415  ; 3.415  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.635  ; 3.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 3.894  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.775  ; 3.775  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 3.841  ; 3.841  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 3.675  ; 3.675  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 3.564  ; 3.564  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.004  ; 4.004  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 3.557  ; 3.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 3.382  ; 3.382  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.713  ; 3.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.434  ; 3.434  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.810  ; 3.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.582  ; 3.582  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.048  ; 3.048  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.483  ; 4.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.051  ; 4.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 3.576  ; 3.576  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 3.608  ; 3.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 3.842  ; 3.842  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 3.644  ; 3.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 3.604  ; 3.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.011  ; 4.011  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 4.057  ; 4.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 3.639  ; 3.639  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 3.542  ; 3.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 3.793  ; 3.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 3.483  ; 3.483  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 3.467  ; 3.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 3.634  ; 3.634  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 3.895  ; 3.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.989  ; 3.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 3.967  ; 3.967  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.797  ; 3.797  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 4.309  ; 4.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.283  ; 4.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.740  ; 3.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 4.650  ; 4.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.892  ; 3.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 3.699  ; 3.699  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 4.043  ; 4.043  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.174  ; 4.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 4.611  ; 4.611  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.638  ; 3.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 1.262  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 1.262  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[3]  ; CRT_PIN4_CLK1 ; 3.072  ; 3.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[4]  ; CRT_PIN4_CLK1 ; 3.584  ; 3.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[5]  ; CRT_PIN4_CLK1 ; 2.953  ; 2.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[6]  ; CRT_PIN4_CLK1 ; 2.784  ; 2.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[7]  ; CRT_PIN4_CLK1 ; 3.395  ; 3.395  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 1.262  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CLK_PLL1      ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[0]       ; CLK_PLL1      ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[1]       ; CLK_PLL1      ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[2]       ; CLK_PLL1      ; 6.550  ; 6.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[3]       ; CLK_PLL1      ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[4]       ; CLK_PLL1      ; 6.516  ; 6.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[5]       ; CLK_PLL1      ; 6.529  ; 6.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[6]       ; CLK_PLL1      ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[7]       ; CLK_PLL1      ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[8]       ; CLK_PLL1      ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[9]       ; CLK_PLL1      ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[10]      ; CLK_PLL1      ; 8.007  ; 8.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[11]      ; CLK_PLL1      ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[12]      ; CLK_PLL1      ; 7.057  ; 7.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[13]      ; CLK_PLL1      ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[14]      ; CLK_PLL1      ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  DATA[15]      ; CLK_PLL1      ; 8.231  ; 8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[4]      ; CLK_PLL1      ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[5]      ; CLK_PLL1      ; 3.560  ; 3.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  LPT_D[6]      ; CLK_PLL1      ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 7.543  ; 7.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.679  ; 7.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 7.601  ; 7.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.431  ; 8.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.650  ; 8.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.595  ; 6.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 6.914  ; 6.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.550  ; 6.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.895  ; 6.895  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.516  ; 6.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.529  ; 6.529  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.025  ; 6.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.398  ; 6.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.386  ; 7.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 8.007  ; 8.007  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.458  ; 7.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.057  ; 7.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.992  ; 6.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 8.562  ; 8.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 8.231  ; 8.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 3.506  ; 3.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 3.560  ; 3.560  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 4.008  ; 4.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 7.543  ; 7.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 7.627  ; 7.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.679  ; 7.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 7.827  ; 7.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.751  ; 7.751  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.469  ; 7.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 7.601  ; 7.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.431  ; 8.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.307  ; 8.307  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 7.718  ; 7.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.446  ; 7.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.650  ; 8.650  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.482  ; 8.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Progagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 22.148 ; 22.148 ; 22.148 ; 22.148 ;
; ASn          ; ACSI_WRn      ; 23.520 ; 23.520 ; 23.520 ; 23.520 ;
; ASn          ; BUTTONn       ; 16.279 ;        ;        ; 16.279 ;
; ASn          ; CA1_OUT       ; 21.433 ;        ;        ; 21.433 ;
; ASn          ; CD[0]         ; 30.705 ; 30.705 ; 30.705 ; 30.705 ;
; ASn          ; CD[1]         ; 31.039 ; 31.039 ; 31.039 ; 31.039 ;
; ASn          ; CD[2]         ; 26.347 ; 26.347 ; 26.347 ; 26.347 ;
; ASn          ; CD[3]         ; 30.790 ; 30.790 ; 30.790 ; 30.790 ;
; ASn          ; CD[4]         ; 33.006 ; 33.006 ; 33.006 ; 33.006 ;
; ASn          ; CD[5]         ; 33.103 ; 33.103 ; 33.103 ; 33.103 ;
; ASn          ; CD[6]         ; 32.787 ; 32.787 ; 32.787 ; 32.787 ;
; ASn          ; CD[7]         ; 25.966 ; 25.966 ; 25.966 ; 25.966 ;
; ASn          ; DATA[0]       ; 30.501 ; 30.791 ; 30.791 ; 30.501 ;
; ASn          ; DATA[1]       ; 31.578 ; 31.578 ; 31.578 ; 31.578 ;
; ASn          ; DATA[2]       ; 30.662 ; 30.662 ; 30.662 ; 30.662 ;
; ASn          ; DATA[3]       ; 30.815 ; 31.102 ; 31.102 ; 30.815 ;
; ASn          ; DATA[4]       ; 30.121 ; 30.158 ; 30.158 ; 30.121 ;
; ASn          ; DATA[5]       ; 31.075 ; 31.075 ; 31.075 ; 31.075 ;
; ASn          ; DATA[6]       ; 30.144 ; 30.144 ; 30.144 ; 30.144 ;
; ASn          ; DATA[7]       ; 30.276 ; 30.554 ; 30.554 ; 30.276 ;
; ASn          ; DATA[8]       ; 31.993 ; 31.993 ; 31.993 ; 31.993 ;
; ASn          ; DATA[9]       ; 32.386 ; 32.245 ; 32.245 ; 32.386 ;
; ASn          ; DATA[10]      ; 32.541 ; 32.436 ; 32.436 ; 32.541 ;
; ASn          ; DATA[11]      ; 32.402 ; 32.480 ; 32.480 ; 32.402 ;
; ASn          ; DATA[12]      ; 31.301 ; 31.575 ; 31.575 ; 31.301 ;
; ASn          ; DATA[13]      ; 31.930 ; 32.314 ; 32.314 ; 31.930 ;
; ASn          ; DATA[14]      ; 33.882 ; 33.882 ; 33.882 ; 33.882 ;
; ASn          ; DATA[15]      ; 33.123 ; 33.123 ; 33.123 ; 33.123 ;
; ASn          ; DTACKn        ; 26.778 ; 26.778 ; 26.778 ; 26.778 ;
; ASn          ; FLASH_CEn     ; 15.131 ;        ;        ; 15.131 ;
; ASn          ; FLASH_OEn     ; 15.686 ;        ;        ; 15.686 ;
; ASn          ; IDE_CS0n      ; 13.497 ;        ;        ; 13.497 ;
; ASn          ; IDE_CS1n      ; 12.361 ;        ;        ; 12.361 ;
; ASn          ; IDE_D_EN_INn  ; 15.816 ;        ;        ; 15.816 ;
; ASn          ; IDE_D_EN_OUTn ; 15.431 ;        ;        ; 15.431 ;
; ASn          ; IDE_IORDn     ; 15.185 ;        ;        ; 15.185 ;
; ASn          ; IDE_IOWRn     ; 16.612 ;        ;        ; 16.612 ;
; ASn          ; JOY_RHn       ; 16.709 ;        ;        ; 16.709 ;
; ASn          ; JOY_RLn       ; 15.550 ;        ;        ; 15.550 ;
; ASn          ; JOY_WEn       ;        ; 15.702 ; 15.702 ;        ;
; ASn          ; JOY_WL        ;        ; 13.568 ; 13.568 ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 17.975 ; 17.975 ;        ;
; ASn          ; RAM_BA[0]     ;        ; 15.796 ; 15.796 ;        ;
; ASn          ; RAM_BA[1]     ;        ; 14.442 ; 14.442 ;        ;
; ASn          ; RAM_CAS0n     ;        ; 18.046 ; 18.046 ;        ;
; ASn          ; RAM_CAS1n     ; 16.790 ;        ;        ; 16.790 ;
; ASn          ; RAM_DATA[0]   ; 32.588 ; 32.878 ; 32.878 ; 32.588 ;
; ASn          ; RAM_DATA[1]   ; 33.011 ; 33.011 ; 33.011 ; 33.011 ;
; ASn          ; RAM_DATA[2]   ; 33.245 ; 33.245 ; 33.245 ; 33.245 ;
; ASn          ; RAM_DATA[3]   ; 32.769 ; 33.056 ; 33.056 ; 32.769 ;
; ASn          ; RAM_DATA[4]   ; 33.014 ; 33.051 ; 33.051 ; 33.014 ;
; ASn          ; RAM_DATA[5]   ; 33.091 ; 33.091 ; 33.091 ; 33.091 ;
; ASn          ; RAM_DATA[6]   ; 33.730 ; 33.730 ; 33.730 ; 33.730 ;
; ASn          ; RAM_DATA[7]   ; 33.994 ; 34.272 ; 34.272 ; 33.994 ;
; ASn          ; RAM_DATA[8]   ; 34.221 ; 34.221 ; 34.221 ; 34.221 ;
; ASn          ; RAM_DATA[9]   ; 34.173 ; 34.032 ; 34.032 ; 34.173 ;
; ASn          ; RAM_DATA[10]  ; 32.888 ; 32.783 ; 32.783 ; 32.888 ;
; ASn          ; RAM_DATA[11]  ; 33.228 ; 33.306 ; 33.306 ; 33.228 ;
; ASn          ; RAM_DATA[12]  ; 32.713 ; 32.987 ; 32.987 ; 32.713 ;
; ASn          ; RAM_DATA[13]  ; 32.644 ; 33.028 ; 33.028 ; 32.644 ;
; ASn          ; RAM_DATA[14]  ; 33.889 ; 33.889 ; 33.889 ; 33.889 ;
; ASn          ; RAM_DATA[15]  ; 33.376 ; 33.376 ; 33.376 ; 33.376 ;
; ASn          ; RAM_DQM0H     ;        ; 17.101 ; 17.101 ;        ;
; ASn          ; RAM_DQM0L     ;        ; 17.357 ; 17.357 ;        ;
; ASn          ; RAM_DQM1H     ; 17.343 ;        ;        ; 17.343 ;
; ASn          ; RAM_DQM1L     ; 16.894 ;        ;        ; 16.894 ;
; ASn          ; RAM_RAS0n     ;        ; 18.078 ; 18.078 ;        ;
; ASn          ; RAM_RAS1n     ; 17.921 ;        ;        ; 17.921 ;
; ASn          ; ROM0n         ; 15.912 ;        ;        ; 15.912 ;
; ASn          ; ROM1n         ; 14.842 ;        ;        ; 14.842 ;
; ASn          ; ROM2n         ; 14.372 ;        ;        ; 14.372 ;
; ASn          ; ROM3n         ; 14.938 ;        ;        ; 14.938 ;
; ASn          ; ROM4n         ; 14.635 ;        ;        ; 14.635 ;
; ASn          ; ROM5n         ; 16.899 ;        ;        ; 16.899 ;
; ASn          ; ROM6n         ; 14.037 ;        ;        ; 14.037 ;
; COM_CTS      ; DATA[2]       ;        ; 21.255 ; 21.255 ;        ;
; COM_CTS      ; DATA[10]      ;        ; 23.591 ; 23.591 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 23.838 ; 23.838 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 23.938 ; 23.938 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 23.020 ; 23.020 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 22.748 ; 22.748 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 24.453 ; 24.453 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 24.535 ; 24.535 ;        ;
; COM_RI       ; DATA[6]       ;        ; 20.562 ; 20.562 ;        ;
; COM_RI       ; DATA[14]      ; 25.036 ; 25.036 ; 25.036 ; 25.036 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 24.148 ; 24.148 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 25.043 ; 25.043 ; 25.043 ; 25.043 ;
; CONFIG[1]    ; DATA[7]       ; 23.007 ; 23.007 ; 23.007 ; 23.007 ;
; CONFIG[1]    ; DATA[15]      ; 25.610 ; 25.610 ; 25.610 ; 25.610 ;
; CONFIG[1]    ; HSYNC         ; 14.353 ; 14.353 ; 14.353 ; 14.353 ;
; CONFIG[1]    ; RAM_DATA[7]   ; 26.725 ; 26.725 ; 26.725 ; 26.725 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 17.617 ; 17.961 ; 17.961 ; 17.617 ;
; CONFIG[1]    ; RAM_DATA[13]  ; 17.871 ; 17.871 ; 17.871 ; 17.871 ;
; CONFIG[1]    ; RAM_DATA[14]  ; 16.805 ; 17.056 ; 17.056 ; 16.805 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 25.863 ; 25.863 ; 25.863 ; 25.863 ;
; CONFIG[1]    ; VSYNC         ; 14.686 ; 14.686 ; 14.686 ; 14.686 ;
; CONFIG[2]    ; DATA[7]       ; 23.109 ; 23.109 ; 23.109 ; 23.109 ;
; CONFIG[2]    ; DATA[15]      ; 25.712 ; 25.712 ; 25.712 ; 25.712 ;
; CONFIG[2]    ; HSYNC         ; 14.455 ; 14.455 ; 14.455 ; 14.455 ;
; CONFIG[2]    ; RAM_DATA[7]   ; 26.827 ; 26.827 ; 26.827 ; 26.827 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 18.027 ; 17.683 ; 17.683 ; 18.027 ;
; CONFIG[2]    ; RAM_DATA[13]  ; 17.937 ; 17.937 ; 17.937 ; 17.937 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 17.122 ; 16.871 ; 16.871 ; 17.122 ;
; CONFIG[2]    ; RAM_DATA[15]  ; 25.965 ; 25.965 ; 25.965 ; 25.965 ;
; CONFIG[2]    ; VSYNC         ; 14.783 ; 14.783 ; 14.783 ; 14.783 ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 17.201 ; 17.201 ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 14.783 ; 14.783 ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 32.280 ; 32.280 ; 32.280 ; 32.280 ;
; CONFIG[5]    ; ACSI_WRn      ; 33.652 ; 33.652 ; 33.652 ; 33.652 ;
; CONFIG[5]    ; BUTTONn       ; 26.906 ; 24.941 ; 24.941 ; 26.906 ;
; CONFIG[5]    ; CA1_OUT       ; 31.565 ; 29.600 ; 29.600 ; 31.565 ;
; CONFIG[5]    ; CD[0]         ; 40.837 ; 40.837 ; 40.837 ; 40.837 ;
; CONFIG[5]    ; CD[1]         ; 41.171 ; 41.171 ; 41.171 ; 41.171 ;
; CONFIG[5]    ; CD[2]         ; 36.479 ; 36.479 ; 36.479 ; 36.479 ;
; CONFIG[5]    ; CD[3]         ; 40.922 ; 40.922 ; 40.922 ; 40.922 ;
; CONFIG[5]    ; CD[4]         ; 43.138 ; 43.138 ; 43.138 ; 43.138 ;
; CONFIG[5]    ; CD[5]         ; 43.235 ; 43.235 ; 43.235 ; 43.235 ;
; CONFIG[5]    ; CD[6]         ; 42.919 ; 42.919 ; 42.919 ; 42.919 ;
; CONFIG[5]    ; CD[7]         ; 36.098 ; 36.098 ; 36.098 ; 36.098 ;
; CONFIG[5]    ; DATA[0]       ; 35.799 ; 35.909 ; 35.909 ; 35.799 ;
; CONFIG[5]    ; DATA[1]       ; 36.340 ; 36.340 ; 36.340 ; 36.340 ;
; CONFIG[5]    ; DATA[2]       ; 35.957 ; 35.957 ; 35.957 ; 35.957 ;
; CONFIG[5]    ; DATA[3]       ; 35.868 ; 35.868 ; 35.868 ; 35.868 ;
; CONFIG[5]    ; DATA[4]       ; 34.794 ; 34.831 ; 34.831 ; 34.794 ;
; CONFIG[5]    ; DATA[5]       ; 35.748 ; 35.748 ; 35.748 ; 35.748 ;
; CONFIG[5]    ; DATA[6]       ; 35.753 ; 35.753 ; 35.753 ; 35.753 ;
; CONFIG[5]    ; DATA[7]       ; 35.056 ; 35.227 ; 35.227 ; 35.056 ;
; CONFIG[5]    ; DATA[8]       ; 37.239 ; 37.239 ; 37.239 ; 37.239 ;
; CONFIG[5]    ; DATA[9]       ; 37.059 ; 36.918 ; 36.918 ; 37.059 ;
; CONFIG[5]    ; DATA[10]      ; 38.294 ; 38.294 ; 38.294 ; 38.294 ;
; CONFIG[5]    ; DATA[11]      ; 37.380 ; 37.380 ; 37.380 ; 37.380 ;
; CONFIG[5]    ; DATA[12]      ; 37.054 ; 36.810 ; 36.810 ; 37.054 ;
; CONFIG[5]    ; DATA[13]      ; 37.626 ; 37.626 ; 37.626 ; 37.626 ;
; CONFIG[5]    ; DATA[14]      ; 38.558 ; 38.558 ; 38.558 ; 38.558 ;
; CONFIG[5]    ; DATA[15]      ; 37.802 ; 37.802 ; 37.802 ; 37.802 ;
; CONFIG[5]    ; DTACKn        ; 33.673 ; 33.673 ; 33.673 ; 33.673 ;
; CONFIG[5]    ; FLASH_CEn     ; 24.755 ; 24.459 ; 24.459 ; 24.755 ;
; CONFIG[5]    ; FLASH_OEn     ; 25.310 ; 25.014 ; 25.014 ; 25.310 ;
; CONFIG[5]    ; IDE_CS0n      ; 25.738 ; 23.773 ; 23.773 ; 25.738 ;
; CONFIG[5]    ; IDE_CS1n      ; 24.774 ; 22.809 ; 22.809 ; 24.774 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 25.403 ; 23.438 ; 23.438 ; 25.403 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 25.018 ; 23.053 ; 23.053 ; 25.018 ;
; CONFIG[5]    ; IDE_IORDn     ; 24.772 ; 22.807 ; 22.807 ; 24.772 ;
; CONFIG[5]    ; IDE_IOWRn     ; 26.199 ; 24.234 ; 24.234 ; 26.199 ;
; CONFIG[5]    ; JOY_RHn       ; 27.922 ; 25.957 ; 25.957 ; 27.922 ;
; CONFIG[5]    ; JOY_RLn       ; 26.497 ; 24.532 ; 24.532 ; 26.497 ;
; CONFIG[5]    ; JOY_WEn       ; 24.684 ; 26.649 ; 26.649 ; 24.684 ;
; CONFIG[5]    ; JOY_WL        ; 25.520 ; 27.485 ; 27.485 ; 25.520 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 28.545 ; 27.005 ; 27.005 ; 28.545 ;
; CONFIG[5]    ; RAM_BA[0]     ; 26.366 ; 24.826 ; 24.826 ; 26.366 ;
; CONFIG[5]    ; RAM_BA[1]     ; 25.012 ; 23.472 ; 23.472 ; 25.012 ;
; CONFIG[5]    ; RAM_CAS0n     ; 28.616 ; 27.076 ; 27.076 ; 28.616 ;
; CONFIG[5]    ; RAM_CAS1n     ; 25.820 ; 27.360 ; 27.360 ; 25.820 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 37.886 ; 37.996 ; 37.996 ; 37.886 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 37.773 ; 37.773 ; 37.773 ; 37.773 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 38.540 ; 38.540 ; 38.540 ; 38.540 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 37.822 ; 37.822 ; 37.822 ; 37.822 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 37.687 ; 37.724 ; 37.724 ; 37.687 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 37.764 ; 37.764 ; 37.764 ; 37.764 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 39.339 ; 39.339 ; 39.339 ; 39.339 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 38.774 ; 38.945 ; 38.945 ; 38.774 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 39.467 ; 39.467 ; 39.467 ; 39.467 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 38.846 ; 38.705 ; 38.705 ; 38.846 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 38.641 ; 38.641 ; 38.641 ; 38.641 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 38.206 ; 38.206 ; 38.206 ; 38.206 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 38.466 ; 38.222 ; 38.222 ; 38.466 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 38.340 ; 38.340 ; 38.340 ; 38.340 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 38.565 ; 38.565 ; 38.565 ; 38.565 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 38.055 ; 38.055 ; 38.055 ; 38.055 ;
; CONFIG[5]    ; RAM_DQM0H     ; 27.671 ; 26.131 ; 26.131 ; 27.671 ;
; CONFIG[5]    ; RAM_DQM0L     ; 27.927 ; 26.387 ; 26.387 ; 27.927 ;
; CONFIG[5]    ; RAM_DQM1H     ; 26.373 ; 27.913 ; 27.913 ; 26.373 ;
; CONFIG[5]    ; RAM_DQM1L     ; 25.924 ; 27.464 ; 27.464 ; 25.924 ;
; CONFIG[5]    ; RAM_RAS0n     ; 28.648 ; 27.108 ; 27.108 ; 28.648 ;
; CONFIG[5]    ; RAM_RAS1n     ; 26.951 ; 28.491 ; 28.491 ; 26.951 ;
; CONFIG[5]    ; ROM0n         ; 24.031 ; 22.491 ; 22.491 ; 24.031 ;
; CONFIG[5]    ; ROM1n         ; 22.965 ; 21.425 ; 21.425 ; 22.965 ;
; CONFIG[5]    ; ROM2n         ; 23.996 ; 23.700 ; 23.700 ; 23.996 ;
; CONFIG[5]    ; ROM3n         ; 23.257 ; 23.671 ; 23.671 ; 23.257 ;
; CONFIG[5]    ; ROM4n         ; 22.960 ; 22.700 ; 22.700 ; 22.960 ;
; CONFIG[5]    ; ROM5n         ; 23.699 ; 24.291 ; 24.291 ; 23.699 ;
; CONFIG[5]    ; ROM6n         ; 22.358 ; 22.776 ; 22.776 ; 22.358 ;
; CONFIG[6]    ; DATA[0]       ; 25.262 ; 25.262 ; 25.262 ; 25.262 ;
; CONFIG[6]    ; DATA[1]       ; 26.913 ; 26.913 ; 26.913 ; 26.913 ;
; CONFIG[6]    ; DATA[2]       ; 25.713 ; 25.713 ; 25.713 ; 25.713 ;
; CONFIG[6]    ; DATA[3]       ; 26.557 ; 26.557 ; 26.557 ; 26.557 ;
; CONFIG[6]    ; DATA[4]       ; 25.893 ; 25.893 ; 25.893 ; 25.893 ;
; CONFIG[6]    ; DATA[5]       ; 25.813 ; 25.813 ; 25.813 ; 25.813 ;
; CONFIG[6]    ; DATA[6]       ; 25.124 ; 25.124 ; 25.124 ; 25.124 ;
; CONFIG[6]    ; DATA[7]       ; 25.526 ; 25.526 ; 25.526 ; 25.526 ;
; CONFIG[6]    ; DATA[8]       ; 26.728 ; 26.497 ; 26.497 ; 26.728 ;
; CONFIG[6]    ; DATA[9]       ; 26.626 ; 26.626 ; 26.626 ; 26.626 ;
; CONFIG[6]    ; DATA[10]      ; 28.444 ; 28.057 ; 28.057 ; 28.444 ;
; CONFIG[6]    ; DATA[11]      ; 27.398 ; 27.342 ; 27.342 ; 27.398 ;
; CONFIG[6]    ; DATA[12]      ; 25.797 ; 26.451 ; 26.451 ; 25.797 ;
; CONFIG[6]    ; DATA[13]      ; 26.578 ; 26.313 ; 26.313 ; 26.578 ;
; CONFIG[6]    ; DATA[14]      ; 25.275 ; 25.275 ; 25.275 ; 25.275 ;
; CONFIG[6]    ; DATA[15]      ; 24.698 ; 24.698 ; 24.698 ; 24.698 ;
; CONFIG[6]    ; DTACKn        ; 21.582 ; 21.582 ; 21.582 ; 21.582 ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 15.016 ; 15.016 ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 14.105 ; 14.105 ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 16.994 ; 16.252 ; 16.252 ; 16.994 ;
; CONFIG[6]    ; FLASH_OEn     ; 17.549 ; 16.807 ; 16.807 ; 17.549 ;
; CONFIG[6]    ; RAM_DATA[0]   ; 27.349 ; 27.349 ; 27.349 ; 27.349 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 28.346 ; 28.346 ; 28.346 ; 28.346 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 28.296 ; 28.296 ; 28.296 ; 28.296 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 28.511 ; 28.511 ; 28.511 ; 28.511 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 28.786 ; 28.786 ; 28.786 ; 28.786 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 27.829 ; 27.829 ; 27.829 ; 27.829 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 28.710 ; 28.710 ; 28.710 ; 28.710 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 29.244 ; 29.244 ; 29.244 ; 29.244 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 28.956 ; 28.725 ; 28.725 ; 28.956 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 28.413 ; 28.413 ; 28.413 ; 28.413 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 28.791 ; 28.404 ; 28.404 ; 28.791 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 28.224 ; 28.168 ; 28.168 ; 28.224 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 27.209 ; 27.863 ; 27.863 ; 27.209 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 27.292 ; 27.027 ; 27.027 ; 27.292 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 25.282 ; 25.282 ; 25.282 ; 25.282 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 24.951 ; 24.951 ; 24.951 ; 24.951 ;
; CONFIG[6]    ; ROM2n         ; 16.235 ; 15.493 ; 15.493 ; 16.235 ;
; CRT_PIN3     ; DATA[7]       ; 18.241 ; 18.241 ; 18.241 ; 18.241 ;
; CRT_PIN3     ; DATA[15]      ; 20.844 ; 20.844 ; 20.844 ; 20.844 ;
; CRT_PIN3     ; RAM_DATA[7]   ; 21.959 ; 21.959 ; 21.959 ; 21.959 ;
; CRT_PIN3     ; RAM_DATA[12]  ; 13.325 ; 13.669 ; 13.669 ; 13.325 ;
; CRT_PIN3     ; RAM_DATA[13]  ; 13.579 ; 13.579 ; 13.579 ; 13.579 ;
; CRT_PIN3     ; RAM_DATA[14]  ; 12.513 ; 12.764 ; 12.764 ; 12.513 ;
; CRT_PIN3     ; RAM_DATA[15]  ; 21.097 ; 21.097 ; 21.097 ; 21.097 ;
; DATA[0]      ; DATA[0]       ; 19.775 ;        ;        ; 19.775 ;
; DATA[0]      ; RAM_DATA[0]   ; 21.862 ;        ;        ; 21.862 ;
; DATA[1]      ; DATA[1]       ; 22.128 ;        ;        ; 22.128 ;
; DATA[1]      ; RAM_DATA[1]   ; 23.561 ;        ;        ; 23.561 ;
; DATA[2]      ; DATA[2]       ; 19.438 ;        ;        ; 19.438 ;
; DATA[2]      ; RAM_DATA[2]   ; 22.021 ;        ;        ; 22.021 ;
; DATA[3]      ; DATA[3]       ; 21.023 ;        ;        ; 21.023 ;
; DATA[3]      ; RAM_DATA[3]   ; 22.977 ;        ;        ; 22.977 ;
; DATA[4]      ; DATA[4]       ; 19.975 ;        ;        ; 19.975 ;
; DATA[4]      ; RAM_DATA[4]   ; 22.868 ;        ;        ; 22.868 ;
; DATA[5]      ; DATA[5]       ; 19.542 ;        ;        ; 19.542 ;
; DATA[5]      ; RAM_DATA[5]   ; 21.558 ;        ;        ; 21.558 ;
; DATA[6]      ; DATA[6]       ; 18.822 ;        ;        ; 18.822 ;
; DATA[6]      ; RAM_DATA[6]   ; 22.408 ;        ;        ; 22.408 ;
; DATA[7]      ; DATA[7]       ; 19.216 ;        ;        ; 19.216 ;
; DATA[7]      ; RAM_DATA[7]   ; 22.934 ;        ;        ; 22.934 ;
; DATA[8]      ; DATA[8]       ; 21.738 ;        ;        ; 21.738 ;
; DATA[8]      ; RAM_DATA[8]   ; 23.966 ;        ;        ; 23.966 ;
; DATA[9]      ; DATA[9]       ; 21.879 ;        ;        ; 21.879 ;
; DATA[9]      ; RAM_DATA[9]   ; 23.666 ;        ;        ; 23.666 ;
; DATA[10]     ; DATA[10]      ; 22.578 ;        ;        ; 22.578 ;
; DATA[10]     ; RAM_DATA[10]  ; 22.925 ;        ;        ; 22.925 ;
; DATA[11]     ; DATA[11]      ; 22.206 ;        ;        ; 22.206 ;
; DATA[11]     ; RAM_DATA[11]  ; 23.032 ;        ;        ; 23.032 ;
; DATA[12]     ; DATA[12]      ; 21.271 ;        ;        ; 21.271 ;
; DATA[12]     ; RAM_DATA[12]  ; 22.683 ;        ;        ; 22.683 ;
; DATA[13]     ; DATA[13]      ; 20.835 ;        ;        ; 20.835 ;
; DATA[13]     ; RAM_DATA[13]  ; 21.549 ;        ;        ; 21.549 ;
; DATA[14]     ; DATA[14]      ; 15.689 ;        ;        ; 15.689 ;
; DATA[14]     ; RAM_DATA[14]  ; 15.696 ;        ;        ; 15.696 ;
; DATA[15]     ; DATA[15]      ; 15.063 ;        ;        ; 15.063 ;
; DATA[15]     ; RAM_DATA[15]  ; 15.316 ;        ;        ; 15.316 ;
; FC[0]        ; ACSI_RDn      ; 19.899 ; 19.899 ; 19.899 ; 19.899 ;
; FC[0]        ; ACSI_WRn      ; 21.271 ; 21.271 ; 21.271 ; 21.271 ;
; FC[0]        ; BUTTONn       ; 17.123 ; 17.123 ; 17.123 ; 17.123 ;
; FC[0]        ; CA1_OUT       ; 19.184 ; 19.184 ; 19.184 ; 19.184 ;
; FC[0]        ; CD[0]         ; 28.456 ; 28.456 ; 28.456 ; 28.456 ;
; FC[0]        ; CD[1]         ; 28.790 ; 28.790 ; 28.790 ; 28.790 ;
; FC[0]        ; CD[2]         ; 24.098 ; 24.098 ; 24.098 ; 24.098 ;
; FC[0]        ; CD[3]         ; 28.541 ; 28.541 ; 28.541 ; 28.541 ;
; FC[0]        ; CD[4]         ; 30.757 ; 30.757 ; 30.757 ; 30.757 ;
; FC[0]        ; CD[5]         ; 30.854 ; 30.854 ; 30.854 ; 30.854 ;
; FC[0]        ; CD[6]         ; 30.538 ; 30.538 ; 30.538 ; 30.538 ;
; FC[0]        ; CD[7]         ; 23.717 ; 23.717 ; 23.717 ; 23.717 ;
; FC[0]        ; DATA[0]       ; 30.607 ; 30.607 ; 30.607 ; 30.607 ;
; FC[0]        ; DATA[1]       ; 31.689 ; 31.689 ; 31.689 ; 31.689 ;
; FC[0]        ; DATA[2]       ; 30.382 ; 30.382 ; 30.382 ; 30.382 ;
; FC[0]        ; DATA[3]       ; 30.962 ; 30.962 ; 30.962 ; 30.962 ;
; FC[0]        ; DATA[4]       ; 30.183 ; 30.183 ; 30.183 ; 30.183 ;
; FC[0]        ; DATA[5]       ; 30.799 ; 30.799 ; 30.799 ; 30.799 ;
; FC[0]        ; DATA[6]       ; 30.177 ; 30.177 ; 30.177 ; 30.177 ;
; FC[0]        ; DATA[7]       ; 29.560 ; 29.560 ; 29.560 ; 29.560 ;
; FC[0]        ; DATA[8]       ; 32.626 ; 32.626 ; 32.626 ; 32.626 ;
; FC[0]        ; DATA[9]       ; 31.417 ; 31.417 ; 31.417 ; 31.417 ;
; FC[0]        ; DATA[10]      ; 32.719 ; 32.719 ; 32.719 ; 32.719 ;
; FC[0]        ; DATA[11]      ; 32.447 ; 32.447 ; 32.447 ; 32.447 ;
; FC[0]        ; DATA[12]      ; 31.585 ; 31.585 ; 31.585 ; 31.585 ;
; FC[0]        ; DATA[13]      ; 32.273 ; 32.273 ; 32.273 ; 32.273 ;
; FC[0]        ; DATA[14]      ; 33.464 ; 33.464 ; 33.464 ; 33.464 ;
; FC[0]        ; DATA[15]      ; 32.163 ; 32.163 ; 32.163 ; 32.163 ;
; FC[0]        ; DTACKn        ; 25.504 ; 25.504 ; 25.504 ; 25.504 ;
; FC[0]        ; FLASH_CEn     ; 16.824 ; 16.824 ; 16.824 ; 16.824 ;
; FC[0]        ; FLASH_OEn     ; 17.379 ; 17.379 ; 17.379 ; 17.379 ;
; FC[0]        ; JOY_RHn       ; 19.551 ; 19.551 ; 19.551 ; 19.551 ;
; FC[0]        ; JOY_RLn       ; 18.392 ; 18.392 ; 18.392 ; 18.392 ;
; FC[0]        ; JOY_WEn       ; 18.544 ; 18.544 ; 18.544 ; 18.544 ;
; FC[0]        ; JOY_WL        ; 16.410 ; 16.410 ; 16.410 ; 16.410 ;
; FC[0]        ; RAM_ADR[8]    ; 19.506 ; 19.506 ; 19.506 ; 19.506 ;
; FC[0]        ; RAM_BA[0]     ; 17.327 ; 17.327 ; 17.327 ; 17.327 ;
; FC[0]        ; RAM_BA[1]     ; 15.973 ; 15.973 ; 15.973 ; 15.973 ;
; FC[0]        ; RAM_CAS0n     ; 19.577 ; 19.577 ; 19.577 ; 19.577 ;
; FC[0]        ; RAM_CAS1n     ; 18.321 ; 18.321 ; 18.321 ; 18.321 ;
; FC[0]        ; RAM_DATA[0]   ; 32.694 ; 32.694 ; 32.694 ; 32.694 ;
; FC[0]        ; RAM_DATA[1]   ; 33.122 ; 33.122 ; 33.122 ; 33.122 ;
; FC[0]        ; RAM_DATA[2]   ; 32.965 ; 32.965 ; 32.965 ; 32.965 ;
; FC[0]        ; RAM_DATA[3]   ; 32.916 ; 32.916 ; 32.916 ; 32.916 ;
; FC[0]        ; RAM_DATA[4]   ; 33.076 ; 33.076 ; 33.076 ; 33.076 ;
; FC[0]        ; RAM_DATA[5]   ; 32.815 ; 32.815 ; 32.815 ; 32.815 ;
; FC[0]        ; RAM_DATA[6]   ; 33.763 ; 33.763 ; 33.763 ; 33.763 ;
; FC[0]        ; RAM_DATA[7]   ; 33.278 ; 33.278 ; 33.278 ; 33.278 ;
; FC[0]        ; RAM_DATA[8]   ; 34.854 ; 34.854 ; 34.854 ; 34.854 ;
; FC[0]        ; RAM_DATA[9]   ; 33.204 ; 33.204 ; 33.204 ; 33.204 ;
; FC[0]        ; RAM_DATA[10]  ; 33.066 ; 33.066 ; 33.066 ; 33.066 ;
; FC[0]        ; RAM_DATA[11]  ; 33.273 ; 33.273 ; 33.273 ; 33.273 ;
; FC[0]        ; RAM_DATA[12]  ; 32.997 ; 32.997 ; 32.997 ; 32.997 ;
; FC[0]        ; RAM_DATA[13]  ; 32.987 ; 32.987 ; 32.987 ; 32.987 ;
; FC[0]        ; RAM_DATA[14]  ; 33.471 ; 33.471 ; 33.471 ; 33.471 ;
; FC[0]        ; RAM_DATA[15]  ; 32.416 ; 32.416 ; 32.416 ; 32.416 ;
; FC[0]        ; RAM_DQM0H     ; 18.632 ; 18.632 ; 18.632 ; 18.632 ;
; FC[0]        ; RAM_DQM0L     ; 18.888 ; 18.888 ; 18.888 ; 18.888 ;
; FC[0]        ; RAM_DQM1H     ; 18.874 ; 18.874 ; 18.874 ; 18.874 ;
; FC[0]        ; RAM_DQM1L     ; 18.425 ; 18.425 ; 18.425 ; 18.425 ;
; FC[0]        ; RAM_RAS0n     ; 19.609 ; 19.609 ; 19.609 ; 19.609 ;
; FC[0]        ; RAM_RAS1n     ; 19.452 ; 19.452 ; 19.452 ; 19.452 ;
; FC[0]        ; ROM0n         ; 15.320 ; 15.320 ; 15.320 ; 15.320 ;
; FC[0]        ; ROM1n         ; 14.250 ; 14.250 ; 14.250 ; 14.250 ;
; FC[0]        ; ROM2n         ; 16.065 ; 16.065 ; 16.065 ; 16.065 ;
; FC[0]        ; ROM3n         ; 14.346 ; 14.346 ; 14.346 ; 14.346 ;
; FC[0]        ; ROM4n         ; 14.043 ; 14.043 ; 14.043 ; 14.043 ;
; FC[0]        ; ROM5n         ; 16.307 ; 16.307 ; 16.307 ; 16.307 ;
; FC[0]        ; ROM6n         ; 13.445 ; 13.445 ; 13.445 ; 13.445 ;
; FC[1]        ; ACSI_RDn      ; 19.443 ; 19.443 ; 19.443 ; 19.443 ;
; FC[1]        ; ACSI_WRn      ; 20.815 ; 20.815 ; 20.815 ; 20.815 ;
; FC[1]        ; BUTTONn       ; 17.157 ; 17.157 ; 17.157 ; 17.157 ;
; FC[1]        ; CA1_OUT       ; 18.728 ; 18.728 ; 18.728 ; 18.728 ;
; FC[1]        ; CD[0]         ; 28.000 ; 28.000 ; 28.000 ; 28.000 ;
; FC[1]        ; CD[1]         ; 28.334 ; 28.334 ; 28.334 ; 28.334 ;
; FC[1]        ; CD[2]         ; 23.642 ; 23.642 ; 23.642 ; 23.642 ;
; FC[1]        ; CD[3]         ; 28.085 ; 28.085 ; 28.085 ; 28.085 ;
; FC[1]        ; CD[4]         ; 30.301 ; 30.301 ; 30.301 ; 30.301 ;
; FC[1]        ; CD[5]         ; 30.398 ; 30.398 ; 30.398 ; 30.398 ;
; FC[1]        ; CD[6]         ; 30.082 ; 30.082 ; 30.082 ; 30.082 ;
; FC[1]        ; CD[7]         ; 23.261 ; 23.261 ; 23.261 ; 23.261 ;
; FC[1]        ; DATA[0]       ; 30.151 ; 30.151 ; 30.151 ; 30.151 ;
; FC[1]        ; DATA[1]       ; 31.233 ; 31.233 ; 31.233 ; 31.233 ;
; FC[1]        ; DATA[2]       ; 29.929 ; 29.929 ; 29.929 ; 29.929 ;
; FC[1]        ; DATA[3]       ; 30.506 ; 30.506 ; 30.506 ; 30.506 ;
; FC[1]        ; DATA[4]       ; 29.727 ; 29.727 ; 29.727 ; 29.727 ;
; FC[1]        ; DATA[5]       ; 30.343 ; 30.343 ; 30.343 ; 30.343 ;
; FC[1]        ; DATA[6]       ; 29.724 ; 29.724 ; 29.724 ; 29.724 ;
; FC[1]        ; DATA[7]       ; 29.124 ; 29.124 ; 29.124 ; 29.124 ;
; FC[1]        ; DATA[8]       ; 32.170 ; 32.170 ; 32.170 ; 32.170 ;
; FC[1]        ; DATA[9]       ; 30.961 ; 30.961 ; 30.961 ; 30.961 ;
; FC[1]        ; DATA[10]      ; 32.266 ; 32.266 ; 32.266 ; 32.266 ;
; FC[1]        ; DATA[11]      ; 31.991 ; 31.991 ; 31.991 ; 31.991 ;
; FC[1]        ; DATA[12]      ; 31.129 ; 31.129 ; 31.129 ; 31.129 ;
; FC[1]        ; DATA[13]      ; 31.817 ; 31.817 ; 31.817 ; 31.817 ;
; FC[1]        ; DATA[14]      ; 33.008 ; 33.008 ; 33.008 ; 33.008 ;
; FC[1]        ; DATA[15]      ; 31.707 ; 31.707 ; 31.707 ; 31.707 ;
; FC[1]        ; DTACKn        ; 25.348 ; 25.348 ; 25.348 ; 25.348 ;
; FC[1]        ; FLASH_CEn     ; 16.858 ; 16.858 ; 16.858 ; 16.858 ;
; FC[1]        ; FLASH_OEn     ; 17.413 ; 17.413 ; 17.413 ; 17.413 ;
; FC[1]        ; JOY_RHn       ; 19.095 ; 19.095 ; 19.095 ; 19.095 ;
; FC[1]        ; JOY_RLn       ; 17.936 ; 17.936 ; 17.936 ; 17.936 ;
; FC[1]        ; JOY_WEn       ; 18.088 ; 18.088 ; 18.088 ; 18.088 ;
; FC[1]        ; JOY_WL        ; 15.954 ; 15.954 ; 15.954 ; 15.954 ;
; FC[1]        ; RAM_ADR[8]    ; 19.540 ; 19.540 ; 19.540 ; 19.540 ;
; FC[1]        ; RAM_BA[0]     ; 17.361 ; 17.361 ; 17.361 ; 17.361 ;
; FC[1]        ; RAM_BA[1]     ; 16.007 ; 16.007 ; 16.007 ; 16.007 ;
; FC[1]        ; RAM_CAS0n     ; 19.611 ; 19.611 ; 19.611 ; 19.611 ;
; FC[1]        ; RAM_CAS1n     ; 18.355 ; 18.355 ; 18.355 ; 18.355 ;
; FC[1]        ; RAM_DATA[0]   ; 32.238 ; 32.238 ; 32.238 ; 32.238 ;
; FC[1]        ; RAM_DATA[1]   ; 32.666 ; 32.666 ; 32.666 ; 32.666 ;
; FC[1]        ; RAM_DATA[2]   ; 32.512 ; 32.512 ; 32.512 ; 32.512 ;
; FC[1]        ; RAM_DATA[3]   ; 32.460 ; 32.460 ; 32.460 ; 32.460 ;
; FC[1]        ; RAM_DATA[4]   ; 32.620 ; 32.620 ; 32.620 ; 32.620 ;
; FC[1]        ; RAM_DATA[5]   ; 32.359 ; 32.359 ; 32.359 ; 32.359 ;
; FC[1]        ; RAM_DATA[6]   ; 33.310 ; 33.310 ; 33.310 ; 33.310 ;
; FC[1]        ; RAM_DATA[7]   ; 32.842 ; 32.842 ; 32.842 ; 32.842 ;
; FC[1]        ; RAM_DATA[8]   ; 34.398 ; 34.398 ; 34.398 ; 34.398 ;
; FC[1]        ; RAM_DATA[9]   ; 32.748 ; 32.748 ; 32.748 ; 32.748 ;
; FC[1]        ; RAM_DATA[10]  ; 32.613 ; 32.613 ; 32.613 ; 32.613 ;
; FC[1]        ; RAM_DATA[11]  ; 32.817 ; 32.817 ; 32.817 ; 32.817 ;
; FC[1]        ; RAM_DATA[12]  ; 32.541 ; 32.541 ; 32.541 ; 32.541 ;
; FC[1]        ; RAM_DATA[13]  ; 32.531 ; 32.531 ; 32.531 ; 32.531 ;
; FC[1]        ; RAM_DATA[14]  ; 33.015 ; 33.015 ; 33.015 ; 33.015 ;
; FC[1]        ; RAM_DATA[15]  ; 31.960 ; 31.960 ; 31.960 ; 31.960 ;
; FC[1]        ; RAM_DQM0H     ; 18.666 ; 18.666 ; 18.666 ; 18.666 ;
; FC[1]        ; RAM_DQM0L     ; 18.922 ; 18.922 ; 18.922 ; 18.922 ;
; FC[1]        ; RAM_DQM1H     ; 18.908 ; 18.908 ; 18.908 ; 18.908 ;
; FC[1]        ; RAM_DQM1L     ; 18.459 ; 18.459 ; 18.459 ; 18.459 ;
; FC[1]        ; RAM_RAS0n     ; 19.643 ; 19.643 ; 19.643 ; 19.643 ;
; FC[1]        ; RAM_RAS1n     ; 19.486 ; 19.486 ; 19.486 ; 19.486 ;
; FC[1]        ; ROM0n         ; 15.355 ; 15.355 ; 15.355 ; 15.355 ;
; FC[1]        ; ROM1n         ; 14.285 ; 14.285 ; 14.285 ; 14.285 ;
; FC[1]        ; ROM2n         ; 16.099 ; 16.099 ; 16.099 ; 16.099 ;
; FC[1]        ; ROM3n         ; 14.381 ; 14.381 ; 14.381 ; 14.381 ;
; FC[1]        ; ROM4n         ; 14.078 ; 14.078 ; 14.078 ; 14.078 ;
; FC[1]        ; ROM5n         ; 16.342 ; 16.342 ; 16.342 ; 16.342 ;
; FC[1]        ; ROM6n         ; 13.480 ; 13.480 ; 13.480 ; 13.480 ;
; FC[2]        ; ACSI_RDn      ; 19.742 ; 19.742 ; 19.742 ; 19.742 ;
; FC[2]        ; ACSI_WRn      ; 21.114 ; 21.114 ; 21.114 ; 21.114 ;
; FC[2]        ; CA1_OUT       ;        ; 19.027 ; 19.027 ;        ;
; FC[2]        ; CD[0]         ; 28.299 ; 28.299 ; 28.299 ; 28.299 ;
; FC[2]        ; CD[1]         ; 28.633 ; 28.633 ; 28.633 ; 28.633 ;
; FC[2]        ; CD[2]         ; 23.941 ; 23.941 ; 23.941 ; 23.941 ;
; FC[2]        ; CD[3]         ; 28.384 ; 28.384 ; 28.384 ; 28.384 ;
; FC[2]        ; CD[4]         ; 30.600 ; 30.600 ; 30.600 ; 30.600 ;
; FC[2]        ; CD[5]         ; 30.697 ; 30.697 ; 30.697 ; 30.697 ;
; FC[2]        ; CD[6]         ; 30.381 ; 30.381 ; 30.381 ; 30.381 ;
; FC[2]        ; CD[7]         ; 23.560 ; 23.560 ; 23.560 ; 23.560 ;
; FC[2]        ; DATA[0]       ; 30.450 ; 30.450 ; 30.450 ; 30.450 ;
; FC[2]        ; DATA[1]       ; 31.532 ; 31.532 ; 31.532 ; 31.532 ;
; FC[2]        ; DATA[2]       ; 30.227 ; 30.227 ; 30.227 ; 30.227 ;
; FC[2]        ; DATA[3]       ; 30.805 ; 30.754 ; 30.754 ; 30.805 ;
; FC[2]        ; DATA[4]       ; 30.026 ; 30.026 ; 30.026 ; 30.026 ;
; FC[2]        ; DATA[5]       ; 30.642 ; 30.642 ; 30.642 ; 30.642 ;
; FC[2]        ; DATA[6]       ; 30.022 ; 30.022 ; 30.022 ; 30.022 ;
; FC[2]        ; DATA[7]       ; 29.403 ; 29.403 ; 29.403 ; 29.403 ;
; FC[2]        ; DATA[8]       ; 32.469 ; 32.469 ; 32.469 ; 32.469 ;
; FC[2]        ; DATA[9]       ; 31.260 ; 31.260 ; 31.260 ; 31.260 ;
; FC[2]        ; DATA[10]      ; 32.564 ; 32.564 ; 32.564 ; 32.564 ;
; FC[2]        ; DATA[11]      ; 32.290 ; 32.239 ; 32.239 ; 32.290 ;
; FC[2]        ; DATA[12]      ; 31.428 ; 31.428 ; 31.428 ; 31.428 ;
; FC[2]        ; DATA[13]      ; 32.116 ; 32.116 ; 32.116 ; 32.116 ;
; FC[2]        ; DATA[14]      ; 33.307 ; 33.307 ; 33.307 ; 33.307 ;
; FC[2]        ; DATA[15]      ; 32.006 ; 32.006 ; 32.006 ; 32.006 ;
; FC[2]        ; DTACKn        ; 22.639 ; 22.639 ; 22.639 ; 22.639 ;
; FC[2]        ; JOY_RHn       ;        ; 19.394 ; 19.394 ;        ;
; FC[2]        ; JOY_RLn       ;        ; 18.235 ; 18.235 ;        ;
; FC[2]        ; JOY_WEn       ; 18.387 ;        ;        ; 18.387 ;
; FC[2]        ; JOY_WL        ; 16.253 ;        ;        ; 16.253 ;
; FC[2]        ; RAM_DATA[0]   ; 32.537 ; 32.537 ; 32.537 ; 32.537 ;
; FC[2]        ; RAM_DATA[1]   ; 32.965 ; 32.965 ; 32.965 ; 32.965 ;
; FC[2]        ; RAM_DATA[2]   ; 32.810 ; 32.810 ; 32.810 ; 32.810 ;
; FC[2]        ; RAM_DATA[3]   ; 32.759 ; 32.708 ; 32.708 ; 32.759 ;
; FC[2]        ; RAM_DATA[4]   ; 32.919 ; 32.919 ; 32.919 ; 32.919 ;
; FC[2]        ; RAM_DATA[5]   ; 32.658 ; 32.658 ; 32.658 ; 32.658 ;
; FC[2]        ; RAM_DATA[6]   ; 33.608 ; 33.608 ; 33.608 ; 33.608 ;
; FC[2]        ; RAM_DATA[7]   ; 33.121 ; 33.121 ; 33.121 ; 33.121 ;
; FC[2]        ; RAM_DATA[8]   ; 34.697 ; 34.697 ; 34.697 ; 34.697 ;
; FC[2]        ; RAM_DATA[9]   ; 33.047 ; 33.047 ; 33.047 ; 33.047 ;
; FC[2]        ; RAM_DATA[10]  ; 32.911 ; 32.911 ; 32.911 ; 32.911 ;
; FC[2]        ; RAM_DATA[11]  ; 33.116 ; 33.065 ; 33.065 ; 33.116 ;
; FC[2]        ; RAM_DATA[12]  ; 32.840 ; 32.840 ; 32.840 ; 32.840 ;
; FC[2]        ; RAM_DATA[13]  ; 32.830 ; 32.830 ; 32.830 ; 32.830 ;
; FC[2]        ; RAM_DATA[14]  ; 33.314 ; 33.314 ; 33.314 ; 33.314 ;
; FC[2]        ; RAM_DATA[15]  ; 32.259 ; 32.259 ; 32.259 ; 32.259 ;
; HDINTn       ; DATA[5]       ; 24.068 ;        ;        ; 24.068 ;
; HDINTn       ; DATA[13]      ; 25.542 ;        ;        ; 25.542 ;
; HDINTn       ; RAM_DATA[5]   ; 26.084 ;        ;        ; 26.084 ;
; HDINTn       ; RAM_DATA[13]  ; 26.256 ;        ;        ; 26.256 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 24.507 ; 24.507 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 25.981 ; 25.981 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 26.523 ; 26.523 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 26.695 ; 26.695 ;        ;
; IDE_IORDY    ; DTACKn        ; 21.049 ; 21.049 ; 21.049 ; 21.049 ;
; LDSn         ; ACSI_RDn      ; 18.937 ; 18.937 ; 18.937 ; 18.937 ;
; LDSn         ; ACSI_WRn      ; 20.309 ; 20.309 ; 20.309 ; 20.309 ;
; LDSn         ; BUTTONn       ; 15.512 ;        ;        ; 15.512 ;
; LDSn         ; CA1_OUT       ; 18.222 ;        ;        ; 18.222 ;
; LDSn         ; CD[0]         ; 27.494 ; 27.494 ; 27.494 ; 27.494 ;
; LDSn         ; CD[1]         ; 27.828 ; 27.828 ; 27.828 ; 27.828 ;
; LDSn         ; CD[2]         ; 23.136 ; 23.136 ; 23.136 ; 23.136 ;
; LDSn         ; CD[3]         ; 27.579 ; 27.579 ; 27.579 ; 27.579 ;
; LDSn         ; CD[4]         ; 29.795 ; 29.795 ; 29.795 ; 29.795 ;
; LDSn         ; CD[5]         ; 29.892 ; 29.892 ; 29.892 ; 29.892 ;
; LDSn         ; CD[6]         ; 29.576 ; 29.576 ; 29.576 ; 29.576 ;
; LDSn         ; CD[7]         ; 22.755 ; 22.755 ; 22.755 ; 22.755 ;
; LDSn         ; DATA[0]       ; 28.560 ; 28.850 ; 28.850 ; 28.560 ;
; LDSn         ; DATA[1]       ; 29.637 ; 29.637 ; 29.637 ; 29.637 ;
; LDSn         ; DATA[2]       ; 28.721 ; 28.721 ; 28.721 ; 28.721 ;
; LDSn         ; DATA[3]       ; 28.874 ; 29.161 ; 29.161 ; 28.874 ;
; LDSn         ; DATA[4]       ; 28.180 ; 28.217 ; 28.217 ; 28.180 ;
; LDSn         ; DATA[5]       ; 29.134 ; 29.134 ; 29.134 ; 29.134 ;
; LDSn         ; DATA[6]       ; 28.203 ; 28.203 ; 28.203 ; 28.203 ;
; LDSn         ; DATA[7]       ; 28.335 ; 28.613 ; 28.613 ; 28.335 ;
; LDSn         ; DATA[8]       ; 30.052 ; 30.052 ; 30.052 ; 30.052 ;
; LDSn         ; DATA[9]       ; 30.445 ; 30.304 ; 30.304 ; 30.445 ;
; LDSn         ; DATA[10]      ; 30.600 ; 30.495 ; 30.495 ; 30.600 ;
; LDSn         ; DATA[11]      ; 30.461 ; 30.539 ; 30.539 ; 30.461 ;
; LDSn         ; DATA[12]      ; 29.360 ; 29.634 ; 29.634 ; 29.360 ;
; LDSn         ; DATA[13]      ; 29.989 ; 30.373 ; 30.373 ; 29.989 ;
; LDSn         ; DATA[14]      ; 31.941 ; 31.941 ; 31.941 ; 31.941 ;
; LDSn         ; DATA[15]      ; 31.182 ; 31.182 ; 31.182 ; 31.182 ;
; LDSn         ; DTACKn        ; 24.837 ; 24.837 ; 24.837 ; 24.837 ;
; LDSn         ; IDE_IORDn     ; 13.117 ;        ;        ; 13.117 ;
; LDSn         ; IDE_IOWRn     ; 14.546 ;        ;        ; 14.546 ;
; LDSn         ; JOY_RLn       ; 16.673 ;        ;        ; 16.673 ;
; LDSn         ; JOY_WEn       ;        ; 16.825 ; 16.825 ;        ;
; LDSn         ; JOY_WL        ;        ; 13.922 ; 13.922 ;        ;
; LDSn         ; RAM_CAS0n     ; 16.261 ;        ;        ; 16.261 ;
; LDSn         ; RAM_CAS1n     ; 15.005 ;        ;        ; 15.005 ;
; LDSn         ; RAM_DATA[0]   ; 30.647 ; 30.937 ; 30.937 ; 30.647 ;
; LDSn         ; RAM_DATA[1]   ; 31.070 ; 31.070 ; 31.070 ; 31.070 ;
; LDSn         ; RAM_DATA[2]   ; 31.304 ; 31.304 ; 31.304 ; 31.304 ;
; LDSn         ; RAM_DATA[3]   ; 30.828 ; 31.115 ; 31.115 ; 30.828 ;
; LDSn         ; RAM_DATA[4]   ; 31.073 ; 31.110 ; 31.110 ; 31.073 ;
; LDSn         ; RAM_DATA[5]   ; 31.150 ; 31.150 ; 31.150 ; 31.150 ;
; LDSn         ; RAM_DATA[6]   ; 31.789 ; 31.789 ; 31.789 ; 31.789 ;
; LDSn         ; RAM_DATA[7]   ; 32.053 ; 32.331 ; 32.331 ; 32.053 ;
; LDSn         ; RAM_DATA[8]   ; 32.280 ; 32.280 ; 32.280 ; 32.280 ;
; LDSn         ; RAM_DATA[9]   ; 32.232 ; 32.091 ; 32.091 ; 32.232 ;
; LDSn         ; RAM_DATA[10]  ; 30.947 ; 30.842 ; 30.842 ; 30.947 ;
; LDSn         ; RAM_DATA[11]  ; 31.287 ; 31.365 ; 31.365 ; 31.287 ;
; LDSn         ; RAM_DATA[12]  ; 30.772 ; 31.046 ; 31.046 ; 30.772 ;
; LDSn         ; RAM_DATA[13]  ; 30.703 ; 31.087 ; 31.087 ; 30.703 ;
; LDSn         ; RAM_DATA[14]  ; 31.948 ; 31.948 ; 31.948 ; 31.948 ;
; LDSn         ; RAM_DATA[15]  ; 31.435 ; 31.435 ; 31.435 ; 31.435 ;
; LDSn         ; RAM_DQM0L     ; 14.741 ;        ;        ; 14.741 ;
; LDSn         ; RAM_DQM1L     ; 14.286 ;        ;        ; 14.286 ;
; LPT_BSY      ; DATA[0]       ; 23.440 ;        ;        ; 23.440 ;
; LPT_BSY      ; DATA[8]       ; 25.459 ;        ;        ; 25.459 ;
; LPT_BSY      ; RAM_DATA[0]   ; 25.527 ;        ;        ; 25.527 ;
; LPT_BSY      ; RAM_DATA[8]   ; 27.687 ;        ;        ; 27.687 ;
; LPT_D[0]     ; DATA[0]       ; 19.574 ;        ;        ; 19.574 ;
; LPT_D[0]     ; DATA[8]       ; 21.252 ;        ;        ; 21.252 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 21.661 ;        ;        ; 21.661 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 23.480 ;        ;        ; 23.480 ;
; LPT_D[1]     ; DATA[1]       ; 21.080 ;        ;        ; 21.080 ;
; LPT_D[1]     ; DATA[9]       ; 21.204 ;        ;        ; 21.204 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 22.513 ;        ;        ; 22.513 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 22.991 ;        ;        ; 22.991 ;
; LPT_D[2]     ; DATA[2]       ; 20.240 ;        ;        ; 20.240 ;
; LPT_D[2]     ; DATA[10]      ; 22.577 ;        ;        ; 22.577 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 22.823 ;        ;        ; 22.823 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 22.924 ;        ;        ; 22.924 ;
; LPT_D[3]     ; DATA[3]       ; 20.711 ;        ;        ; 20.711 ;
; LPT_D[3]     ; DATA[11]      ; 22.223 ;        ;        ; 22.223 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 22.665 ;        ;        ; 22.665 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 23.049 ;        ;        ; 23.049 ;
; LPT_D[4]     ; DATA[4]       ; 22.828 ;        ;        ; 22.828 ;
; LPT_D[4]     ; DATA[12]      ; 24.045 ;        ;        ; 24.045 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.721 ;        ;        ; 25.721 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 25.457 ;        ;        ; 25.457 ;
; LPT_D[5]     ; DATA[5]       ; 20.161 ;        ;        ; 20.161 ;
; LPT_D[5]     ; DATA[13]      ; 22.249 ;        ;        ; 22.249 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 22.177 ;        ;        ; 22.177 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 22.963 ;        ;        ; 22.963 ;
; LPT_D[6]     ; DATA[6]       ; 20.170 ;        ;        ; 20.170 ;
; LPT_D[6]     ; DATA[14]      ; 22.975 ; 22.975 ; 22.975 ; 22.975 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 23.756 ;        ;        ; 23.756 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 22.982 ; 22.982 ; 22.982 ; 22.982 ;
; LPT_D[7]     ; DATA[7]       ; 20.541 ;        ;        ; 20.541 ;
; LPT_D[7]     ; DATA[15]      ; 22.601 ; 22.601 ; 22.601 ; 22.601 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 24.259 ;        ;        ; 24.259 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 22.854 ; 22.854 ; 22.854 ; 22.854 ;
; MIDI_IN      ; MIDI_TLR      ; 8.871  ;        ;        ; 8.871  ;
; RAM_DATA[0]  ; DATA[0]       ; 22.386 ;        ;        ; 22.386 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 24.473 ;        ;        ; 24.473 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.685 ;        ;        ; 24.685 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 26.118 ;        ;        ; 26.118 ;
; RAM_DATA[2]  ; DATA[2]       ; 24.490 ;        ;        ; 24.490 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 27.073 ;        ;        ; 27.073 ;
; RAM_DATA[3]  ; DATA[3]       ; 22.581 ;        ;        ; 22.581 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 24.535 ;        ;        ; 24.535 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.917 ;        ;        ; 21.917 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 24.810 ;        ;        ; 24.810 ;
; RAM_DATA[5]  ; DATA[5]       ; 23.287 ;        ;        ; 23.287 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 25.303 ;        ;        ; 25.303 ;
; RAM_DATA[6]  ; DATA[6]       ; 22.355 ;        ;        ; 22.355 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.941 ;        ;        ; 25.941 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.981 ;        ;        ; 22.981 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 26.699 ;        ;        ; 26.699 ;
; RAM_DATA[8]  ; DATA[8]       ; 25.310 ;        ;        ; 25.310 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 27.538 ;        ;        ; 27.538 ;
; RAM_DATA[9]  ; DATA[9]       ; 24.007 ;        ;        ; 24.007 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 25.794 ;        ;        ; 25.794 ;
; RAM_DATA[10] ; DATA[10]      ; 25.005 ;        ;        ; 25.005 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 25.352 ;        ;        ; 25.352 ;
; RAM_DATA[11] ; DATA[11]      ; 24.771 ;        ;        ; 24.771 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 25.597 ;        ;        ; 25.597 ;
; RAM_DATA[12] ; DATA[12]      ; 23.020 ;        ;        ; 23.020 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 24.432 ;        ;        ; 24.432 ;
; RAM_DATA[13] ; DATA[13]      ; 24.628 ;        ;        ; 24.628 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 25.342 ;        ;        ; 25.342 ;
; RAM_DATA[14] ; DATA[14]      ; 24.239 ; 24.239 ; 24.239 ; 24.239 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 24.246 ; 24.246 ; 24.246 ; 24.246 ;
; RAM_DATA[15] ; DATA[15]      ; 24.937 ; 24.937 ; 24.937 ; 24.937 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 25.190 ; 25.190 ; 25.190 ; 25.190 ;
; RWn          ; ACSI_RDn      ; 18.870 ; 18.870 ; 18.870 ; 18.870 ;
; RWn          ; ACSI_WRn      ; 20.242 ; 20.242 ; 20.242 ; 20.242 ;
; RWn          ; BUTTONn       ;        ; 15.643 ; 15.643 ;        ;
; RWn          ; CA1_OUT       ;        ; 18.155 ; 18.155 ;        ;
; RWn          ; CD[0]         ; 27.427 ; 27.427 ; 27.427 ; 27.427 ;
; RWn          ; CD[1]         ; 27.761 ; 27.761 ; 27.761 ; 27.761 ;
; RWn          ; CD[2]         ; 23.069 ; 23.069 ; 23.069 ; 23.069 ;
; RWn          ; CD[3]         ; 27.512 ; 27.512 ; 27.512 ; 27.512 ;
; RWn          ; CD[4]         ; 29.728 ; 29.728 ; 29.728 ; 29.728 ;
; RWn          ; CD[5]         ; 29.825 ; 29.825 ; 29.825 ; 29.825 ;
; RWn          ; CD[6]         ; 29.509 ; 29.509 ; 29.509 ; 29.509 ;
; RWn          ; CD[7]         ; 22.688 ; 22.688 ; 22.688 ; 22.688 ;
; RWn          ; DATA[0]       ; 29.578 ; 29.578 ; 29.578 ; 29.578 ;
; RWn          ; DATA[1]       ; 30.660 ; 30.660 ; 30.660 ; 30.660 ;
; RWn          ; DATA[2]       ; 29.356 ; 29.356 ; 29.356 ; 29.356 ;
; RWn          ; DATA[3]       ; 29.933 ; 29.882 ; 29.882 ; 29.933 ;
; RWn          ; DATA[4]       ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
; RWn          ; DATA[5]       ; 29.770 ; 29.770 ; 29.770 ; 29.770 ;
; RWn          ; DATA[6]       ; 29.151 ; 29.151 ; 29.151 ; 29.151 ;
; RWn          ; DATA[7]       ; 28.531 ; 28.531 ; 28.531 ; 28.531 ;
; RWn          ; DATA[8]       ; 31.597 ; 31.597 ; 31.597 ; 31.597 ;
; RWn          ; DATA[9]       ; 30.388 ; 30.388 ; 30.388 ; 30.388 ;
; RWn          ; DATA[10]      ; 31.693 ; 31.693 ; 31.693 ; 31.693 ;
; RWn          ; DATA[11]      ; 31.418 ; 31.367 ; 31.367 ; 31.418 ;
; RWn          ; DATA[12]      ; 30.556 ; 30.556 ; 30.556 ; 30.556 ;
; RWn          ; DATA[13]      ; 31.244 ; 31.244 ; 31.244 ; 31.244 ;
; RWn          ; DATA[14]      ; 32.435 ; 32.435 ; 32.435 ; 32.435 ;
; RWn          ; DATA[15]      ; 31.134 ; 31.134 ; 31.134 ; 31.134 ;
; RWn          ; DTACKn        ; 24.283 ; 24.283 ; 24.283 ; 24.283 ;
; RWn          ; FLASH_CEn     ;        ; 14.864 ; 14.864 ;        ;
; RWn          ; FLASH_OEn     ;        ; 15.419 ; 15.419 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 14.749 ; 14.749 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 12.847 ;        ;        ; 12.847 ;
; RWn          ; IDE_IORDn     ;        ; 12.986 ; 12.986 ;        ;
; RWn          ; IDE_IOWRn     ; 14.416 ;        ;        ; 14.416 ;
; RWn          ; JOY_RHn       ;        ; 18.522 ; 18.522 ;        ;
; RWn          ; JOY_RLn       ;        ; 17.363 ; 17.363 ;        ;
; RWn          ; JOY_WEn       ; 17.515 ;        ;        ; 17.515 ;
; RWn          ; JOY_WL        ; 15.381 ; 13.745 ; 13.745 ; 15.381 ;
; RWn          ; RAM_DATA[0]   ; 31.665 ; 31.665 ; 31.665 ; 31.665 ;
; RWn          ; RAM_DATA[1]   ; 32.093 ; 32.093 ; 32.093 ; 32.093 ;
; RWn          ; RAM_DATA[2]   ; 31.939 ; 31.939 ; 31.939 ; 31.939 ;
; RWn          ; RAM_DATA[3]   ; 31.887 ; 31.836 ; 31.836 ; 31.887 ;
; RWn          ; RAM_DATA[4]   ; 32.047 ; 32.047 ; 32.047 ; 32.047 ;
; RWn          ; RAM_DATA[5]   ; 31.786 ; 31.786 ; 31.786 ; 31.786 ;
; RWn          ; RAM_DATA[6]   ; 32.737 ; 32.737 ; 32.737 ; 32.737 ;
; RWn          ; RAM_DATA[7]   ; 32.249 ; 32.249 ; 32.249 ; 32.249 ;
; RWn          ; RAM_DATA[8]   ; 33.825 ; 33.825 ; 33.825 ; 33.825 ;
; RWn          ; RAM_DATA[9]   ; 32.175 ; 32.175 ; 32.175 ; 32.175 ;
; RWn          ; RAM_DATA[10]  ; 32.040 ; 32.040 ; 32.040 ; 32.040 ;
; RWn          ; RAM_DATA[11]  ; 32.244 ; 32.193 ; 32.193 ; 32.244 ;
; RWn          ; RAM_DATA[12]  ; 31.968 ; 31.968 ; 31.968 ; 31.968 ;
; RWn          ; RAM_DATA[13]  ; 31.958 ; 31.958 ; 31.958 ; 31.958 ;
; RWn          ; RAM_DATA[14]  ; 32.442 ; 32.442 ; 32.442 ; 32.442 ;
; RWn          ; RAM_DATA[15]  ; 31.387 ; 31.387 ; 31.387 ; 31.387 ;
; RWn          ; RAM_WEn       ; 14.842 ;        ;        ; 14.842 ;
; RWn          ; ROM0n         ;        ; 14.976 ; 14.976 ;        ;
; RWn          ; ROM1n         ;        ; 13.906 ; 13.906 ;        ;
; RWn          ; ROM2n         ;        ; 14.105 ; 14.105 ;        ;
; RWn          ; ROM3n         ;        ; 14.002 ; 14.002 ;        ;
; RWn          ; ROM4n         ;        ; 13.699 ; 13.699 ;        ;
; RWn          ; ROM5n         ;        ; 15.963 ; 15.963 ;        ;
; RWn          ; ROM6n         ;        ; 13.101 ; 13.101 ;        ;
; SCSI_ACKn    ; CD[0]         ; 16.457 ; 16.457 ; 16.457 ; 16.457 ;
; SCSI_ATNn    ; CD[1]         ; 18.058 ; 18.058 ; 18.058 ; 18.058 ;
; SCSI_BSYn    ; CD[6]         ; 22.644 ; 22.644 ; 22.644 ; 22.644 ;
; SCSI_D[0]    ; CD[0]         ; 17.333 ; 17.333 ; 17.333 ; 17.333 ;
; SCSI_D[1]    ; CD[1]         ; 16.480 ; 16.480 ; 16.480 ; 16.480 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.613 ; 16.613 ;        ;
; SCSI_D[3]    ; CD[3]         ; 16.418 ; 16.418 ; 16.418 ; 16.418 ;
; SCSI_D[4]    ; CD[4]         ; 23.558 ; 23.558 ; 23.558 ; 23.558 ;
; SCSI_D[5]    ; CD[5]         ; 23.090 ; 23.090 ; 23.090 ; 23.090 ;
; SCSI_D[6]    ; CD[6]         ; 22.848 ; 22.848 ; 22.848 ; 22.848 ;
; SCSI_D[7]    ; CD[7]         ; 17.816 ; 17.816 ; 17.816 ; 17.816 ;
; SCSI_DCn     ; CD[3]         ; 18.105 ; 18.105 ; 18.105 ; 18.105 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 16.690 ; 16.690 ; 16.690 ; 16.690 ;
; SCSI_DCn     ; SCSI_D[0]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[1]     ; 15.349 ; 15.349 ; 15.349 ; 15.349 ;
; SCSI_DCn     ; SCSI_D[2]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[3]     ; 14.803 ; 14.803 ; 14.803 ; 14.803 ;
; SCSI_DCn     ; SCSI_D[4]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[5]     ; 15.111 ; 15.111 ; 15.111 ; 15.111 ;
; SCSI_DCn     ; SCSI_D[6]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_D[7]     ; 15.387 ; 15.387 ; 15.387 ; 15.387 ;
; SCSI_DCn     ; SCSI_DP       ; 15.359 ; 15.359 ; 15.359 ; 15.359 ;
; SCSI_DP      ; CD[0]         ; 16.084 ; 16.084 ; 16.084 ; 16.084 ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 12.209 ; 12.209 ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 12.911 ;        ;        ; 12.911 ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 12.310 ; 12.310 ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 12.664 ;        ;        ; 12.664 ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 12.961 ; 12.961 ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 12.526 ;        ;        ; 12.526 ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 13.749 ; 13.749 ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 12.994 ;        ;        ; 12.994 ;
; SCSI_IDn[1]  ; SCSI_DP       ; 14.270 ; 14.270 ; 14.270 ; 14.270 ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 11.564 ; 11.564 ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 12.276 ; 12.276 ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 11.663 ;        ;        ; 11.663 ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 12.018 ;        ;        ; 12.018 ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 12.320 ; 12.320 ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 11.894 ; 11.894 ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 13.108 ;        ;        ; 13.108 ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 12.349 ;        ;        ; 12.349 ;
; SCSI_IDn[2]  ; SCSI_DP       ; 13.629 ; 13.629 ; 13.629 ; 13.629 ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 12.373 ; 12.373 ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 13.079 ; 13.079 ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 12.503 ; 12.503 ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 12.857 ; 12.857 ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 13.065 ;        ;        ; 13.065 ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 12.636 ;        ;        ; 12.636 ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 13.893 ;        ;        ; 13.893 ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 13.127 ;        ;        ; 13.127 ;
; SCSI_IDn[3]  ; SCSI_DP       ; 14.414 ; 14.414 ; 14.414 ; 14.414 ;
; SCSI_IOn     ; CD[2]         ;        ; 17.074 ; 17.074 ;        ;
; SCSI_IOn     ; CD[3]         ; 17.643 ; 17.643 ; 17.643 ; 17.643 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 16.228 ; 16.228 ; 16.228 ; 16.228 ;
; SCSI_IOn     ; SCSI_D[0]     ; 14.887 ; 14.887 ; 14.887 ; 14.887 ;
; SCSI_IOn     ; SCSI_D[1]     ; 14.887 ; 14.887 ; 14.887 ; 14.887 ;
; SCSI_IOn     ; SCSI_D[2]     ; 14.341 ; 14.341 ; 14.341 ; 14.341 ;
; SCSI_IOn     ; SCSI_D[3]     ; 14.341 ; 14.341 ; 14.341 ; 14.341 ;
; SCSI_IOn     ; SCSI_D[4]     ; 14.649 ; 14.649 ; 14.649 ; 14.649 ;
; SCSI_IOn     ; SCSI_D[5]     ; 14.649 ; 14.649 ; 14.649 ; 14.649 ;
; SCSI_IOn     ; SCSI_D[6]     ; 14.925 ; 14.925 ; 14.925 ; 14.925 ;
; SCSI_IOn     ; SCSI_D[7]     ; 14.925 ; 14.925 ; 14.925 ; 14.925 ;
; SCSI_IOn     ; SCSI_DP       ; 14.897 ; 14.897 ; 14.897 ; 14.897 ;
; SCSI_IOn     ; SCSI_RDn      ; 13.498 ;        ;        ; 13.498 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 13.290 ; 13.290 ;        ;
; SCSI_MSGn    ; CD[3]         ; 17.772 ; 17.772 ; 17.772 ; 17.772 ;
; SCSI_MSGn    ; CD[4]         ; 22.329 ; 22.329 ; 22.329 ; 22.329 ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 16.357 ; 16.357 ; 16.357 ; 16.357 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 15.016 ; 15.016 ; 15.016 ; 15.016 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 14.470 ; 14.470 ; 14.470 ; 14.470 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 14.778 ; 14.778 ; 14.778 ; 14.778 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 15.054 ; 15.054 ; 15.054 ; 15.054 ;
; SCSI_MSGn    ; SCSI_DP       ; 15.026 ; 15.026 ; 15.026 ; 15.026 ;
; SCSI_REQn    ; CD[3]         ; 17.887 ; 17.887 ; 17.887 ; 17.887 ;
; SCSI_REQn    ; CD[5]         ; 22.156 ; 22.156 ; 22.156 ; 22.156 ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 16.472 ;        ;        ; 16.472 ;
; SCSI_REQn    ; SCSI_D[0]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[1]     ; 15.131 ; 15.131 ; 15.131 ; 15.131 ;
; SCSI_REQn    ; SCSI_D[2]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[3]     ; 14.585 ; 14.585 ; 14.585 ; 14.585 ;
; SCSI_REQn    ; SCSI_D[4]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[5]     ; 14.893 ; 14.893 ; 14.893 ; 14.893 ;
; SCSI_REQn    ; SCSI_D[6]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_D[7]     ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; SCSI_REQn    ; SCSI_DP       ; 15.141 ; 15.141 ; 15.141 ; 15.141 ;
; SCSI_RSTn    ; CD[7]         ;        ; 18.133 ; 18.133 ;        ;
; SCSI_SELn    ; CD[1]         ; 16.156 ; 16.156 ; 16.156 ; 16.156 ;
; SD_AVR_ENn   ; RESETn        ;        ; 17.730 ; 17.730 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 13.086 ; 13.086 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 10.631 ; 10.631 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 13.038 ;        ;        ; 13.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.504 ;        ;        ; 12.504 ;
; SD_RESETn    ; ACSI_RDn      ; 21.724 ; 21.724 ; 21.724 ; 21.724 ;
; SD_RESETn    ; ACSI_WRn      ; 23.096 ; 23.096 ; 23.096 ; 23.096 ;
; SD_RESETn    ; CA1_OUT       ; 21.009 ;        ;        ; 21.009 ;
; SD_RESETn    ; CD[0]         ; 30.281 ; 30.281 ; 30.281 ; 30.281 ;
; SD_RESETn    ; CD[1]         ; 30.615 ; 30.615 ; 30.615 ; 30.615 ;
; SD_RESETn    ; CD[2]         ; 25.923 ; 25.923 ; 25.923 ; 25.923 ;
; SD_RESETn    ; CD[3]         ; 30.366 ; 30.366 ; 30.366 ; 30.366 ;
; SD_RESETn    ; CD[4]         ; 32.582 ; 32.582 ; 32.582 ; 32.582 ;
; SD_RESETn    ; CD[5]         ; 32.679 ; 32.679 ; 32.679 ; 32.679 ;
; SD_RESETn    ; CD[6]         ; 32.363 ; 32.363 ; 32.363 ; 32.363 ;
; SD_RESETn    ; CD[7]         ; 25.542 ; 25.542 ; 25.542 ; 25.542 ;
; SD_RESETn    ; COM_TxD       ; 18.782 ; 18.782 ; 18.782 ; 18.782 ;
; SD_RESETn    ; DATA[0]       ; 27.599 ; 27.925 ; 27.925 ; 27.599 ;
; SD_RESETn    ; DATA[1]       ; 28.162 ; 28.162 ; 28.162 ; 28.162 ;
; SD_RESETn    ; DATA[2]       ; 26.730 ; 26.730 ; 26.730 ; 26.730 ;
; SD_RESETn    ; DATA[3]       ; 27.445 ; 27.445 ; 27.445 ; 27.445 ;
; SD_RESETn    ; DATA[4]       ; 27.186 ; 27.186 ; 27.186 ; 27.186 ;
; SD_RESETn    ; DATA[5]       ; 27.039 ; 27.039 ; 27.039 ; 27.039 ;
; SD_RESETn    ; DATA[6]       ; 26.791 ; 26.791 ; 26.791 ; 26.791 ;
; SD_RESETn    ; DATA[7]       ; 27.396 ; 27.396 ; 27.396 ; 27.396 ;
; SD_RESETn    ; DATA[8]       ; 29.395 ; 29.721 ; 29.721 ; 29.395 ;
; SD_RESETn    ; DATA[9]       ; 29.150 ; 29.150 ; 29.150 ; 29.150 ;
; SD_RESETn    ; DATA[10]      ; 29.333 ; 29.333 ; 29.333 ; 29.333 ;
; SD_RESETn    ; DATA[11]      ; 28.908 ; 28.908 ; 28.908 ; 28.908 ;
; SD_RESETn    ; DATA[12]      ; 28.146 ; 28.146 ; 28.146 ; 28.146 ;
; SD_RESETn    ; DATA[13]      ; 28.143 ; 28.143 ; 28.143 ; 28.143 ;
; SD_RESETn    ; DATA[14]      ; 30.305 ; 30.305 ; 30.305 ; 30.305 ;
; SD_RESETn    ; DATA[15]      ; 29.671 ; 29.671 ; 29.671 ; 29.671 ;
; SD_RESETn    ; DTACKn        ; 19.293 ; 19.293 ; 19.293 ; 19.293 ;
; SD_RESETn    ; RAM_DATA[0]   ; 29.686 ; 30.012 ; 30.012 ; 29.686 ;
; SD_RESETn    ; RAM_DATA[1]   ; 29.595 ; 29.595 ; 29.595 ; 29.595 ;
; SD_RESETn    ; RAM_DATA[2]   ; 29.313 ; 29.313 ; 29.313 ; 29.313 ;
; SD_RESETn    ; RAM_DATA[3]   ; 29.399 ; 29.399 ; 29.399 ; 29.399 ;
; SD_RESETn    ; RAM_DATA[4]   ; 30.079 ; 30.079 ; 30.079 ; 30.079 ;
; SD_RESETn    ; RAM_DATA[5]   ; 29.055 ; 29.055 ; 29.055 ; 29.055 ;
; SD_RESETn    ; RAM_DATA[6]   ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; SD_RESETn    ; RAM_DATA[7]   ; 31.114 ; 31.114 ; 31.114 ; 31.114 ;
; SD_RESETn    ; RAM_DATA[8]   ; 31.623 ; 31.949 ; 31.949 ; 31.623 ;
; SD_RESETn    ; RAM_DATA[9]   ; 30.937 ; 30.937 ; 30.937 ; 30.937 ;
; SD_RESETn    ; RAM_DATA[10]  ; 29.680 ; 29.680 ; 29.680 ; 29.680 ;
; SD_RESETn    ; RAM_DATA[11]  ; 29.734 ; 29.734 ; 29.734 ; 29.734 ;
; SD_RESETn    ; RAM_DATA[12]  ; 29.558 ; 29.558 ; 29.558 ; 29.558 ;
; SD_RESETn    ; RAM_DATA[13]  ; 28.857 ; 28.857 ; 28.857 ; 28.857 ;
; SD_RESETn    ; RAM_DATA[14]  ; 30.312 ; 30.312 ; 30.312 ; 30.312 ;
; SD_RESETn    ; RAM_DATA[15]  ; 29.924 ; 29.924 ; 29.924 ; 29.924 ;
; UDSn         ; ACSI_RDn      ; 20.933 ; 20.933 ; 20.933 ; 20.933 ;
; UDSn         ; ACSI_WRn      ; 22.305 ; 22.305 ; 22.305 ; 22.305 ;
; UDSn         ; CA1_OUT       ; 20.218 ;        ;        ; 20.218 ;
; UDSn         ; CD[0]         ; 29.490 ; 29.490 ; 29.490 ; 29.490 ;
; UDSn         ; CD[1]         ; 29.824 ; 29.824 ; 29.824 ; 29.824 ;
; UDSn         ; CD[2]         ; 25.132 ; 25.132 ; 25.132 ; 25.132 ;
; UDSn         ; CD[3]         ; 29.575 ; 29.575 ; 29.575 ; 29.575 ;
; UDSn         ; CD[4]         ; 31.791 ; 31.791 ; 31.791 ; 31.791 ;
; UDSn         ; CD[5]         ; 31.888 ; 31.888 ; 31.888 ; 31.888 ;
; UDSn         ; CD[6]         ; 31.572 ; 31.572 ; 31.572 ; 31.572 ;
; UDSn         ; CD[7]         ; 24.751 ; 24.751 ; 24.751 ; 24.751 ;
; UDSn         ; DATA[0]       ; 29.286 ; 29.576 ; 29.576 ; 29.286 ;
; UDSn         ; DATA[1]       ; 30.363 ; 30.363 ; 30.363 ; 30.363 ;
; UDSn         ; DATA[2]       ; 29.447 ; 29.447 ; 29.447 ; 29.447 ;
; UDSn         ; DATA[3]       ; 29.600 ; 29.887 ; 29.887 ; 29.600 ;
; UDSn         ; DATA[4]       ; 28.906 ; 28.943 ; 28.943 ; 28.906 ;
; UDSn         ; DATA[5]       ; 29.860 ; 29.860 ; 29.860 ; 29.860 ;
; UDSn         ; DATA[6]       ; 28.929 ; 28.929 ; 28.929 ; 28.929 ;
; UDSn         ; DATA[7]       ; 29.061 ; 29.339 ; 29.339 ; 29.061 ;
; UDSn         ; DATA[8]       ; 30.778 ; 30.778 ; 30.778 ; 30.778 ;
; UDSn         ; DATA[9]       ; 31.171 ; 31.030 ; 31.030 ; 31.171 ;
; UDSn         ; DATA[10]      ; 31.326 ; 31.221 ; 31.221 ; 31.326 ;
; UDSn         ; DATA[11]      ; 31.187 ; 31.265 ; 31.265 ; 31.187 ;
; UDSn         ; DATA[12]      ; 30.086 ; 30.360 ; 30.360 ; 30.086 ;
; UDSn         ; DATA[13]      ; 30.715 ; 31.099 ; 31.099 ; 30.715 ;
; UDSn         ; DATA[14]      ; 32.667 ; 32.667 ; 32.667 ; 32.667 ;
; UDSn         ; DATA[15]      ; 31.908 ; 31.908 ; 31.908 ; 31.908 ;
; UDSn         ; DTACKn        ; 25.563 ; 25.563 ; 25.563 ; 25.563 ;
; UDSn         ; JOY_RHn       ; 14.641 ;        ;        ; 14.641 ;
; UDSn         ; RAM_CAS0n     ; 15.583 ;        ;        ; 15.583 ;
; UDSn         ; RAM_CAS1n     ; 14.327 ;        ;        ; 14.327 ;
; UDSn         ; RAM_DATA[0]   ; 31.373 ; 31.663 ; 31.663 ; 31.373 ;
; UDSn         ; RAM_DATA[1]   ; 31.796 ; 31.796 ; 31.796 ; 31.796 ;
; UDSn         ; RAM_DATA[2]   ; 32.030 ; 32.030 ; 32.030 ; 32.030 ;
; UDSn         ; RAM_DATA[3]   ; 31.554 ; 31.841 ; 31.841 ; 31.554 ;
; UDSn         ; RAM_DATA[4]   ; 31.799 ; 31.836 ; 31.836 ; 31.799 ;
; UDSn         ; RAM_DATA[5]   ; 31.876 ; 31.876 ; 31.876 ; 31.876 ;
; UDSn         ; RAM_DATA[6]   ; 32.515 ; 32.515 ; 32.515 ; 32.515 ;
; UDSn         ; RAM_DATA[7]   ; 32.779 ; 33.057 ; 33.057 ; 32.779 ;
; UDSn         ; RAM_DATA[8]   ; 33.006 ; 33.006 ; 33.006 ; 33.006 ;
; UDSn         ; RAM_DATA[9]   ; 32.958 ; 32.817 ; 32.817 ; 32.958 ;
; UDSn         ; RAM_DATA[10]  ; 31.673 ; 31.568 ; 31.568 ; 31.673 ;
; UDSn         ; RAM_DATA[11]  ; 32.013 ; 32.091 ; 32.091 ; 32.013 ;
; UDSn         ; RAM_DATA[12]  ; 31.498 ; 31.772 ; 31.772 ; 31.498 ;
; UDSn         ; RAM_DATA[13]  ; 31.429 ; 31.813 ; 31.813 ; 31.429 ;
; UDSn         ; RAM_DATA[14]  ; 32.674 ; 32.674 ; 32.674 ; 32.674 ;
; UDSn         ; RAM_DATA[15]  ; 32.161 ; 32.161 ; 32.161 ; 32.161 ;
; UDSn         ; RAM_DQM0H     ; 13.771 ;        ;        ; 13.771 ;
; UDSn         ; RAM_DQM1H     ; 14.022 ;        ;        ; 14.022 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Progagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ASn          ; ACSI_RDn      ; 9.340  ; 9.340  ; 9.340  ; 9.340  ;
; ASn          ; ACSI_WRn      ; 9.969  ; 9.969  ; 9.969  ; 9.969  ;
; ASn          ; BUTTONn       ; 7.765  ;        ;        ; 7.765  ;
; ASn          ; CA1_OUT       ; 9.893  ;        ;        ; 9.893  ;
; ASn          ; CD[0]         ; 10.218 ; 10.218 ; 10.218 ; 10.218 ;
; ASn          ; CD[1]         ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; ASn          ; CD[2]         ; 9.743  ; 9.701  ; 9.701  ; 9.743  ;
; ASn          ; CD[3]         ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; ASn          ; CD[4]         ; 9.861  ; 9.861  ; 9.861  ; 9.861  ;
; ASn          ; CD[5]         ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; ASn          ; CD[6]         ; 10.029 ; 10.029 ; 10.029 ; 10.029 ;
; ASn          ; CD[7]         ; 9.549  ; 9.549  ; 9.549  ; 9.549  ;
; ASn          ; DATA[0]       ; 8.511  ; 8.700  ; 8.700  ; 8.511  ;
; ASn          ; DATA[1]       ; 8.831  ; 8.831  ; 8.831  ; 8.831  ;
; ASn          ; DATA[2]       ; 8.488  ; 8.262  ; 8.262  ; 8.488  ;
; ASn          ; DATA[3]       ; 8.876  ; 8.764  ; 8.764  ; 8.876  ;
; ASn          ; DATA[4]       ; 8.416  ; 8.416  ; 8.416  ; 8.416  ;
; ASn          ; DATA[5]       ; 8.520  ; 8.520  ; 8.520  ; 8.520  ;
; ASn          ; DATA[6]       ; 8.231  ; 8.231  ; 8.231  ; 8.231  ;
; ASn          ; DATA[7]       ; 8.651  ; 8.483  ; 8.483  ; 8.651  ;
; ASn          ; DATA[8]       ; 8.876  ; 8.876  ; 8.876  ; 8.876  ;
; ASn          ; DATA[9]       ; 8.876  ; 8.876  ; 8.876  ; 8.876  ;
; ASn          ; DATA[10]      ; 9.012  ; 9.012  ; 9.012  ; 9.012  ;
; ASn          ; DATA[11]      ; 9.012  ; 9.012  ; 9.012  ; 9.012  ;
; ASn          ; DATA[12]      ; 8.797  ; 8.797  ; 8.797  ; 8.797  ;
; ASn          ; DATA[13]      ; 8.917  ; 8.917  ; 8.917  ; 8.917  ;
; ASn          ; DATA[14]      ; 9.060  ; 9.060  ; 9.060  ; 9.060  ;
; ASn          ; DATA[15]      ; 9.050  ; 9.050  ; 9.050  ; 9.050  ;
; ASn          ; DTACKn        ; 8.121  ; 8.121  ; 8.121  ; 8.121  ;
; ASn          ; FLASH_CEn     ; 7.260  ;        ;        ; 7.260  ;
; ASn          ; FLASH_OEn     ; 7.469  ;        ;        ; 7.469  ;
; ASn          ; IDE_CS0n      ; 6.658  ;        ;        ; 6.658  ;
; ASn          ; IDE_CS1n      ; 6.283  ;        ;        ; 6.283  ;
; ASn          ; IDE_D_EN_INn  ; 7.626  ;        ;        ; 7.626  ;
; ASn          ; IDE_D_EN_OUTn ; 7.457  ;        ;        ; 7.457  ;
; ASn          ; IDE_IORDn     ; 7.382  ;        ;        ; 7.382  ;
; ASn          ; IDE_IOWRn     ; 7.870  ;        ;        ; 7.870  ;
; ASn          ; JOY_RHn       ; 7.921  ;        ;        ; 7.921  ;
; ASn          ; JOY_RLn       ; 7.592  ;        ;        ; 7.592  ;
; ASn          ; JOY_WEn       ;        ; 7.674  ; 7.674  ;        ;
; ASn          ; JOY_WL        ;        ; 6.811  ; 6.811  ;        ;
; ASn          ; RAM_ADR[8]    ;        ; 8.413  ; 8.413  ;        ;
; ASn          ; RAM_BA[0]     ;        ; 7.609  ; 7.609  ;        ;
; ASn          ; RAM_BA[1]     ;        ; 7.085  ; 7.085  ;        ;
; ASn          ; RAM_CAS0n     ;        ; 8.551  ; 8.551  ;        ;
; ASn          ; RAM_CAS1n     ; 7.965  ;        ;        ; 7.965  ;
; ASn          ; RAM_DATA[0]   ; 9.459  ; 9.648  ; 9.648  ; 9.459  ;
; ASn          ; RAM_DATA[1]   ; 9.544  ; 9.544  ; 9.544  ; 9.544  ;
; ASn          ; RAM_DATA[2]   ; 9.617  ; 9.391  ; 9.391  ; 9.617  ;
; ASn          ; RAM_DATA[3]   ; 9.861  ; 9.696  ; 9.696  ; 9.861  ;
; ASn          ; RAM_DATA[4]   ; 9.651  ; 9.651  ; 9.651  ; 9.651  ;
; ASn          ; RAM_DATA[5]   ; 9.460  ; 9.460  ; 9.460  ; 9.460  ;
; ASn          ; RAM_DATA[6]   ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; ASn          ; RAM_DATA[7]   ; 10.387 ; 10.219 ; 10.219 ; 10.387 ;
; ASn          ; RAM_DATA[8]   ; 10.129 ; 10.480 ; 10.480 ; 10.129 ;
; ASn          ; RAM_DATA[9]   ; 9.957  ; 9.957  ; 9.957  ; 9.957  ;
; ASn          ; RAM_DATA[10]  ; 9.613  ; 9.613  ; 9.613  ; 9.613  ;
; ASn          ; RAM_DATA[11]  ; 9.789  ; 9.789  ; 9.789  ; 9.789  ;
; ASn          ; RAM_DATA[12]  ; 9.458  ; 9.458  ; 9.458  ; 9.458  ;
; ASn          ; RAM_DATA[13]  ; 9.371  ; 9.371  ; 9.371  ; 9.371  ;
; ASn          ; RAM_DATA[14]  ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; ASn          ; RAM_DATA[15]  ; 9.743  ; 9.743  ; 9.743  ; 9.743  ;
; ASn          ; RAM_DQM0H     ;        ; 8.137  ; 8.137  ;        ;
; ASn          ; RAM_DQM0L     ;        ; 8.230  ; 8.230  ;        ;
; ASn          ; RAM_DQM1H     ; 8.200  ;        ;        ; 8.200  ;
; ASn          ; RAM_DQM1L     ; 8.029  ;        ;        ; 8.029  ;
; ASn          ; RAM_RAS0n     ;        ; 8.506  ; 8.506  ;        ;
; ASn          ; RAM_RAS1n     ; 8.473  ;        ;        ; 8.473  ;
; ASn          ; ROM0n         ; 7.539  ;        ;        ; 7.539  ;
; ASn          ; ROM1n         ; 7.164  ;        ;        ; 7.164  ;
; ASn          ; ROM2n         ; 6.979  ;        ;        ; 6.979  ;
; ASn          ; ROM3n         ; 7.139  ;        ;        ; 7.139  ;
; ASn          ; ROM4n         ; 7.033  ;        ;        ; 7.033  ;
; ASn          ; ROM5n         ; 7.847  ;        ;        ; 7.847  ;
; ASn          ; ROM6n         ; 6.847  ;        ;        ; 6.847  ;
; COM_CTS      ; DATA[2]       ;        ; 9.271  ; 9.271  ;        ;
; COM_CTS      ; DATA[10]      ;        ; 10.282 ; 10.282 ;        ;
; COM_CTS      ; RAM_DATA[2]   ;        ; 10.400 ; 10.400 ;        ;
; COM_CTS      ; RAM_DATA[10]  ;        ; 10.561 ; 10.561 ;        ;
; COM_DCD      ; DATA[1]       ;        ; 9.959  ; 9.959  ;        ;
; COM_DCD      ; DATA[9]       ;        ; 9.885  ; 9.885  ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.672 ; 10.672 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.769 ; 10.769 ;        ;
; COM_RI       ; DATA[6]       ;        ; 9.078  ; 9.078  ;        ;
; COM_RI       ; DATA[14]      ; 10.954 ; 10.954 ; 10.954 ; 10.954 ;
; COM_RI       ; RAM_DATA[6]   ;        ; 10.654 ; 10.654 ;        ;
; COM_RI       ; RAM_DATA[14]  ; 11.042 ; 11.042 ; 11.042 ; 11.042 ;
; CONFIG[1]    ; DATA[7]       ; 10.178 ; 10.178 ; 10.178 ; 10.178 ;
; CONFIG[1]    ; DATA[15]      ; 11.202 ; 11.202 ; 11.202 ; 11.202 ;
; CONFIG[1]    ; HSYNC         ; 7.120  ; 7.120  ; 7.120  ; 7.120  ;
; CONFIG[1]    ; RAM_DATA[7]   ; 11.914 ; 11.914 ; 11.914 ; 11.914 ;
; CONFIG[1]    ; RAM_DATA[12]  ; 8.370  ; 8.502  ; 8.502  ; 8.370  ;
; CONFIG[1]    ; RAM_DATA[13]  ; 8.464  ; 8.464  ; 8.464  ; 8.464  ;
; CONFIG[1]    ; RAM_DATA[14]  ; 8.069  ; 8.184  ; 8.184  ; 8.069  ;
; CONFIG[1]    ; RAM_DATA[15]  ; 8.179  ; 8.190  ; 8.190  ; 8.179  ;
; CONFIG[1]    ; VSYNC         ; 7.191  ; 7.191  ; 7.191  ; 7.191  ;
; CONFIG[2]    ; DATA[7]       ; 10.170 ; 10.170 ; 10.170 ; 10.170 ;
; CONFIG[2]    ; DATA[15]      ; 11.194 ; 11.194 ; 11.194 ; 11.194 ;
; CONFIG[2]    ; HSYNC         ; 7.114  ; 7.114  ; 7.114  ; 7.114  ;
; CONFIG[2]    ; RAM_DATA[7]   ; 11.906 ; 11.906 ; 11.906 ; 11.906 ;
; CONFIG[2]    ; RAM_DATA[12]  ; 8.490  ; 8.358  ; 8.358  ; 8.490  ;
; CONFIG[2]    ; RAM_DATA[13]  ; 8.452  ; 8.452  ; 8.452  ; 8.452  ;
; CONFIG[2]    ; RAM_DATA[14]  ; 8.172  ; 8.057  ; 8.057  ; 8.172  ;
; CONFIG[2]    ; RAM_DATA[15]  ; 8.178  ; 8.167  ; 8.167  ; 8.178  ;
; CONFIG[2]    ; VSYNC         ; 7.182  ; 7.182  ; 7.182  ; 7.182  ;
; CONFIG[4]    ; RAM_ADR[8]    ;        ; 8.113  ; 8.113  ;        ;
; CONFIG[4]    ; RAM_BA[0]     ;        ; 7.229  ; 7.229  ;        ;
; CONFIG[5]    ; ACSI_RDn      ; 12.513 ; 12.513 ; 12.513 ; 12.513 ;
; CONFIG[5]    ; ACSI_WRn      ; 13.142 ; 13.142 ; 13.142 ; 13.142 ;
; CONFIG[5]    ; BUTTONn       ; 11.244 ; 11.129 ; 11.129 ; 11.244 ;
; CONFIG[5]    ; CA1_OUT       ; 13.181 ; 13.066 ; 13.066 ; 13.181 ;
; CONFIG[5]    ; CD[0]         ; 13.391 ; 13.391 ; 13.391 ; 13.391 ;
; CONFIG[5]    ; CD[1]         ; 13.274 ; 13.274 ; 13.274 ; 13.274 ;
; CONFIG[5]    ; CD[2]         ; 12.874 ; 12.916 ; 12.916 ; 12.874 ;
; CONFIG[5]    ; CD[3]         ; 13.274 ; 13.274 ; 13.274 ; 13.274 ;
; CONFIG[5]    ; CD[4]         ; 13.034 ; 13.034 ; 13.034 ; 13.034 ;
; CONFIG[5]    ; CD[5]         ; 13.243 ; 13.243 ; 13.243 ; 13.243 ;
; CONFIG[5]    ; CD[6]         ; 13.202 ; 13.202 ; 13.202 ; 13.202 ;
; CONFIG[5]    ; CD[7]         ; 12.722 ; 12.722 ; 12.722 ; 12.722 ;
; CONFIG[5]    ; DATA[0]       ; 10.915 ; 10.915 ; 10.915 ; 10.915 ;
; CONFIG[5]    ; DATA[1]       ; 10.915 ; 10.915 ; 10.915 ; 10.915 ;
; CONFIG[5]    ; DATA[2]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[3]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[4]       ; 10.769 ; 10.769 ; 10.769 ; 10.769 ;
; CONFIG[5]    ; DATA[5]       ; 10.769 ; 10.769 ; 10.769 ; 10.769 ;
; CONFIG[5]    ; DATA[6]       ; 10.624 ; 10.624 ; 10.624 ; 10.624 ;
; CONFIG[5]    ; DATA[7]       ; 10.614 ; 10.614 ; 10.614 ; 10.614 ;
; CONFIG[5]    ; DATA[8]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[9]       ; 10.777 ; 10.777 ; 10.777 ; 10.777 ;
; CONFIG[5]    ; DATA[10]      ; 10.913 ; 10.913 ; 10.913 ; 10.913 ;
; CONFIG[5]    ; DATA[11]      ; 10.913 ; 10.913 ; 10.913 ; 10.913 ;
; CONFIG[5]    ; DATA[12]      ; 10.955 ; 10.955 ; 10.955 ; 10.955 ;
; CONFIG[5]    ; DATA[13]      ; 10.955 ; 10.955 ; 10.955 ; 10.955 ;
; CONFIG[5]    ; DATA[14]      ; 10.961 ; 10.961 ; 10.961 ; 10.961 ;
; CONFIG[5]    ; DATA[15]      ; 10.951 ; 10.951 ; 10.951 ; 10.951 ;
; CONFIG[5]    ; DTACKn        ; 11.294 ; 11.294 ; 11.294 ; 11.294 ;
; CONFIG[5]    ; FLASH_CEn     ; 9.604  ; 9.719  ; 9.719  ; 9.604  ;
; CONFIG[5]    ; FLASH_OEn     ; 9.813  ; 9.928  ; 9.928  ; 9.813  ;
; CONFIG[5]    ; IDE_CS0n      ; 10.620 ; 10.471 ; 10.471 ; 10.620 ;
; CONFIG[5]    ; IDE_CS1n      ; 10.316 ; 10.167 ; 10.167 ; 10.316 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 10.566 ; 10.417 ; 10.417 ; 10.566 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 10.397 ; 10.248 ; 10.248 ; 10.397 ;
; CONFIG[5]    ; IDE_IORDn     ; 10.322 ; 10.173 ; 10.173 ; 10.322 ;
; CONFIG[5]    ; IDE_IOWRn     ; 10.810 ; 10.661 ; 10.661 ; 10.810 ;
; CONFIG[5]    ; JOY_RHn       ; 11.549 ; 11.434 ; 11.434 ; 11.549 ;
; CONFIG[5]    ; JOY_RLn       ; 11.123 ; 11.008 ; 11.008 ; 11.123 ;
; CONFIG[5]    ; JOY_WEn       ; 11.090 ; 11.205 ; 11.205 ; 11.090 ;
; CONFIG[5]    ; JOY_WL        ; 11.475 ; 11.590 ; 11.590 ; 11.475 ;
; CONFIG[5]    ; RAM_ADR[8]    ; 10.896 ; 10.008 ; 10.008 ; 10.896 ;
; CONFIG[5]    ; RAM_BA[0]     ; 10.092 ; 9.204  ; 9.204  ; 10.092 ;
; CONFIG[5]    ; RAM_BA[1]     ; 9.434  ; 8.680  ; 8.680  ; 9.434  ;
; CONFIG[5]    ; RAM_CAS0n     ; 10.662 ; 10.146 ; 10.146 ; 10.662 ;
; CONFIG[5]    ; RAM_CAS1n     ; 9.560  ; 10.105 ; 10.105 ; 9.560  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 12.226 ; 12.186 ; 12.186 ; 12.226 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 12.295 ; 12.255 ; 12.255 ; 12.295 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 12.361 ; 12.510 ; 12.510 ; 12.361 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 12.591 ; 12.551 ; 12.551 ; 12.591 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 12.570 ; 12.530 ; 12.530 ; 12.570 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 12.430 ; 12.430 ; 12.430 ; 12.430 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 12.777 ; 12.777 ; 12.777 ; 12.777 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 12.647 ; 12.687 ; 12.687 ; 12.647 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 13.178 ; 13.099 ; 13.099 ; 13.178 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 12.757 ; 12.717 ; 12.717 ; 12.757 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 12.184 ; 12.224 ; 12.224 ; 12.184 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 12.339 ; 12.379 ; 12.379 ; 12.339 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 12.428 ; 12.428 ; 12.428 ; 12.428 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 12.213 ; 12.253 ; 12.253 ; 12.213 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 11.950 ; 11.950 ; 11.950 ; 11.950 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 11.912 ; 11.912 ; 11.912 ; 11.912 ;
; CONFIG[5]    ; RAM_DQM0H     ; 10.248 ; 9.732  ; 9.732  ; 10.248 ;
; CONFIG[5]    ; RAM_DQM0L     ; 10.341 ; 9.825  ; 9.825  ; 10.341 ;
; CONFIG[5]    ; RAM_DQM1H     ; 9.795  ; 10.340 ; 10.340 ; 9.795  ;
; CONFIG[5]    ; RAM_DQM1L     ; 9.624  ; 10.169 ; 10.169 ; 9.624  ;
; CONFIG[5]    ; RAM_RAS0n     ; 10.645 ; 10.101 ; 10.101 ; 10.645 ;
; CONFIG[5]    ; RAM_RAS1n     ; 10.068 ; 10.612 ; 10.612 ; 10.068 ;
; CONFIG[5]    ; ROM0n         ; 9.092  ; 8.977  ; 8.977  ; 9.092  ;
; CONFIG[5]    ; ROM1n         ; 9.369  ; 9.254  ; 9.254  ; 9.369  ;
; CONFIG[5]    ; ROM2n         ; 9.323  ; 9.438  ; 9.438  ; 9.323  ;
; CONFIG[5]    ; ROM3n         ; 9.563  ; 9.448  ; 9.448  ; 9.563  ;
; CONFIG[5]    ; ROM4n         ; 9.303  ; 9.347  ; 9.347  ; 9.303  ;
; CONFIG[5]    ; ROM5n         ; 9.372  ; 9.372  ; 9.372  ; 9.372  ;
; CONFIG[5]    ; ROM6n         ; 9.276  ; 9.161  ; 9.161  ; 9.276  ;
; CONFIG[6]    ; DATA[0]       ; 10.733 ; 10.733 ; 10.733 ; 10.733 ;
; CONFIG[6]    ; DATA[1]       ; 11.321 ; 11.321 ; 11.321 ; 11.321 ;
; CONFIG[6]    ; DATA[2]       ; 10.881 ; 10.881 ; 10.881 ; 10.881 ;
; CONFIG[6]    ; DATA[3]       ; 11.258 ; 11.258 ; 11.258 ; 11.258 ;
; CONFIG[6]    ; DATA[4]       ; 10.986 ; 10.986 ; 10.986 ; 10.986 ;
; CONFIG[6]    ; DATA[5]       ; 10.990 ; 10.990 ; 10.990 ; 10.990 ;
; CONFIG[6]    ; DATA[6]       ; 10.643 ; 10.643 ; 10.643 ; 10.643 ;
; CONFIG[6]    ; DATA[7]       ; 10.812 ; 10.812 ; 10.812 ; 10.812 ;
; CONFIG[6]    ; DATA[8]       ; 11.288 ; 11.376 ; 11.376 ; 11.288 ;
; CONFIG[6]    ; DATA[9]       ; 11.253 ; 11.253 ; 11.253 ; 11.253 ;
; CONFIG[6]    ; DATA[10]      ; 11.866 ; 12.046 ; 12.046 ; 11.866 ;
; CONFIG[6]    ; DATA[11]      ; 11.562 ; 11.610 ; 11.610 ; 11.562 ;
; CONFIG[6]    ; DATA[12]      ; 11.218 ; 10.994 ; 10.994 ; 11.218 ;
; CONFIG[6]    ; DATA[13]      ; 11.122 ; 11.239 ; 11.239 ; 11.122 ;
; CONFIG[6]    ; DATA[14]      ; 10.988 ; 10.988 ; 10.988 ; 10.988 ;
; CONFIG[6]    ; DATA[15]      ; 10.654 ; 10.654 ; 10.654 ; 10.654 ;
; CONFIG[6]    ; DTACKn        ; 9.405  ; 9.405  ; 9.405  ; 9.405  ;
; CONFIG[6]    ; FLASH_ADR_18  ;        ; 7.351  ; 7.351  ;        ;
; CONFIG[6]    ; FLASH_ADR_19  ;        ; 6.944  ; 6.944  ;        ;
; CONFIG[6]    ; FLASH_CEn     ; 7.995  ; 7.715  ; 7.715  ; 7.995  ;
; CONFIG[6]    ; FLASH_OEn     ; 8.204  ; 7.924  ; 7.924  ; 8.204  ;
; CONFIG[6]    ; RAM_DATA[0]   ; 11.681 ; 11.681 ; 11.681 ; 11.681 ;
; CONFIG[6]    ; RAM_DATA[1]   ; 12.034 ; 12.034 ; 12.034 ; 12.034 ;
; CONFIG[6]    ; RAM_DATA[2]   ; 12.010 ; 12.010 ; 12.010 ; 12.010 ;
; CONFIG[6]    ; RAM_DATA[3]   ; 12.190 ; 12.190 ; 12.190 ; 12.190 ;
; CONFIG[6]    ; RAM_DATA[4]   ; 12.221 ; 12.221 ; 12.221 ; 12.221 ;
; CONFIG[6]    ; RAM_DATA[5]   ; 11.930 ; 11.930 ; 11.930 ; 11.930 ;
; CONFIG[6]    ; RAM_DATA[6]   ; 12.219 ; 12.219 ; 12.219 ; 12.219 ;
; CONFIG[6]    ; RAM_DATA[7]   ; 12.548 ; 12.548 ; 12.548 ; 12.548 ;
; CONFIG[6]    ; RAM_DATA[8]   ; 12.333 ; 12.421 ; 12.421 ; 12.333 ;
; CONFIG[6]    ; RAM_DATA[9]   ; 12.137 ; 12.137 ; 12.137 ; 12.137 ;
; CONFIG[6]    ; RAM_DATA[10]  ; 12.145 ; 12.325 ; 12.325 ; 12.145 ;
; CONFIG[6]    ; RAM_DATA[11]  ; 12.062 ; 12.110 ; 12.110 ; 12.062 ;
; CONFIG[6]    ; RAM_DATA[12]  ; 11.879 ; 11.655 ; 11.655 ; 11.879 ;
; CONFIG[6]    ; RAM_DATA[13]  ; 11.576 ; 11.693 ; 11.693 ; 11.576 ;
; CONFIG[6]    ; RAM_DATA[14]  ; 11.076 ; 11.076 ; 11.076 ; 11.076 ;
; CONFIG[6]    ; RAM_DATA[15]  ; 10.905 ; 10.905 ; 10.905 ; 10.905 ;
; CONFIG[6]    ; ROM2n         ; 7.714  ; 7.434  ; 7.434  ; 7.714  ;
; CRT_PIN3     ; DATA[7]       ; 7.463  ; 7.463  ; 7.463  ; 7.463  ;
; CRT_PIN3     ; DATA[15]      ; 8.487  ; 8.487  ; 8.487  ; 8.487  ;
; CRT_PIN3     ; RAM_DATA[7]   ; 9.199  ; 9.199  ; 9.199  ; 9.199  ;
; CRT_PIN3     ; RAM_DATA[12]  ; 5.829  ; 5.961  ; 5.961  ; 5.829  ;
; CRT_PIN3     ; RAM_DATA[13]  ; 5.923  ; 5.923  ; 5.923  ; 5.923  ;
; CRT_PIN3     ; RAM_DATA[14]  ; 5.528  ; 5.643  ; 5.643  ; 5.528  ;
; CRT_PIN3     ; RAM_DATA[15]  ; 5.638  ; 5.649  ; 5.649  ; 5.638  ;
; DATA[0]      ; DATA[0]       ; 7.528  ;        ;        ; 7.528  ;
; DATA[0]      ; RAM_DATA[0]   ; 8.476  ;        ;        ; 8.476  ;
; DATA[1]      ; DATA[1]       ; 7.334  ;        ;        ; 7.334  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.047  ;        ;        ; 8.047  ;
; DATA[2]      ; DATA[2]       ; 6.949  ;        ;        ; 6.949  ;
; DATA[2]      ; RAM_DATA[2]   ; 8.078  ;        ;        ; 8.078  ;
; DATA[3]      ; DATA[3]       ; 6.857  ;        ;        ; 6.857  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.789  ;        ;        ; 7.789  ;
; DATA[4]      ; DATA[4]       ; 7.492  ;        ;        ; 7.492  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.727  ;        ;        ; 8.727  ;
; DATA[5]      ; DATA[5]       ; 7.742  ;        ;        ; 7.742  ;
; DATA[5]      ; RAM_DATA[5]   ; 8.682  ;        ;        ; 8.682  ;
; DATA[6]      ; DATA[6]       ; 6.534  ;        ;        ; 6.534  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.110  ;        ;        ; 8.110  ;
; DATA[7]      ; DATA[7]       ; 6.472  ;        ;        ; 6.472  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.208  ;        ;        ; 8.208  ;
; DATA[8]      ; DATA[8]       ; 7.874  ;        ;        ; 7.874  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.919  ;        ;        ; 8.919  ;
; DATA[9]      ; DATA[9]       ; 7.217  ;        ;        ; 7.217  ;
; DATA[9]      ; RAM_DATA[9]   ; 8.101  ;        ;        ; 8.101  ;
; DATA[10]     ; DATA[10]      ; 7.572  ;        ;        ; 7.572  ;
; DATA[10]     ; RAM_DATA[10]  ; 7.851  ;        ;        ; 7.851  ;
; DATA[11]     ; DATA[11]      ; 7.385  ;        ;        ; 7.385  ;
; DATA[11]     ; RAM_DATA[11]  ; 7.885  ;        ;        ; 7.885  ;
; DATA[12]     ; DATA[12]      ; 7.060  ;        ;        ; 7.060  ;
; DATA[12]     ; RAM_DATA[12]  ; 7.721  ;        ;        ; 7.721  ;
; DATA[13]     ; DATA[13]      ; 7.172  ;        ;        ; 7.172  ;
; DATA[13]     ; RAM_DATA[13]  ; 7.626  ;        ;        ; 7.626  ;
; DATA[14]     ; DATA[14]      ; 7.487  ;        ;        ; 7.487  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.575  ;        ;        ; 7.575  ;
; DATA[15]     ; DATA[15]      ; 7.161  ;        ;        ; 7.161  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.412  ;        ;        ; 7.412  ;
; FC[0]        ; ACSI_RDn      ; 8.497  ; 8.497  ; 8.497  ; 8.497  ;
; FC[0]        ; ACSI_WRn      ; 9.126  ; 9.126  ; 9.126  ; 9.126  ;
; FC[0]        ; BUTTONn       ; 8.110  ; 8.110  ; 8.110  ; 8.110  ;
; FC[0]        ; CA1_OUT       ; 9.050  ; 9.050  ; 9.050  ; 9.050  ;
; FC[0]        ; CD[0]         ; 9.375  ; 9.375  ; 9.375  ; 9.375  ;
; FC[0]        ; CD[1]         ; 9.258  ; 9.258  ; 9.258  ; 9.258  ;
; FC[0]        ; CD[2]         ; 8.858  ; 8.858  ; 8.858  ; 8.858  ;
; FC[0]        ; CD[3]         ; 9.258  ; 9.258  ; 9.258  ; 9.258  ;
; FC[0]        ; CD[4]         ; 9.018  ; 9.018  ; 9.018  ; 9.018  ;
; FC[0]        ; CD[5]         ; 9.227  ; 9.227  ; 9.227  ; 9.227  ;
; FC[0]        ; CD[6]         ; 9.186  ; 9.186  ; 9.186  ; 9.186  ;
; FC[0]        ; CD[7]         ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; FC[0]        ; DATA[0]       ; 8.883  ; 8.883  ; 8.883  ; 8.883  ;
; FC[0]        ; DATA[1]       ; 8.944  ; 8.944  ; 8.944  ; 8.944  ;
; FC[0]        ; DATA[2]       ; 8.413  ; 8.413  ; 8.413  ; 8.413  ;
; FC[0]        ; DATA[3]       ; 8.515  ; 8.515  ; 8.515  ; 8.515  ;
; FC[0]        ; DATA[4]       ; 8.468  ; 8.468  ; 8.468  ; 8.468  ;
; FC[0]        ; DATA[5]       ; 8.797  ; 8.797  ; 8.797  ; 8.797  ;
; FC[0]        ; DATA[6]       ; 8.258  ; 8.258  ; 8.258  ; 8.258  ;
; FC[0]        ; DATA[7]       ; 8.361  ; 8.361  ; 8.361  ; 8.361  ;
; FC[0]        ; DATA[8]       ; 9.370  ; 9.370  ; 9.370  ; 9.370  ;
; FC[0]        ; DATA[9]       ; 9.132  ; 9.132  ; 9.132  ; 9.132  ;
; FC[0]        ; DATA[10]      ; 9.476  ; 9.476  ; 9.476  ; 9.476  ;
; FC[0]        ; DATA[11]      ; 9.169  ; 9.169  ; 9.169  ; 9.169  ;
; FC[0]        ; DATA[12]      ; 8.890  ; 8.890  ; 8.890  ; 8.890  ;
; FC[0]        ; DATA[13]      ; 9.006  ; 9.006  ; 9.006  ; 9.006  ;
; FC[0]        ; DATA[14]      ; 9.588  ; 9.588  ; 9.588  ; 9.588  ;
; FC[0]        ; DATA[15]      ; 9.261  ; 9.261  ; 9.261  ; 9.261  ;
; FC[0]        ; DTACKn        ; 7.938  ; 7.938  ; 7.938  ; 7.938  ;
; FC[0]        ; FLASH_CEn     ; 7.851  ; 7.851  ; 7.851  ; 7.851  ;
; FC[0]        ; FLASH_OEn     ; 8.060  ; 8.060  ; 8.060  ; 8.060  ;
; FC[0]        ; JOY_RHn       ; 8.992  ; 8.992  ; 8.992  ; 8.992  ;
; FC[0]        ; JOY_RLn       ; 8.663  ; 8.663  ; 8.663  ; 8.663  ;
; FC[0]        ; JOY_WEn       ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; FC[0]        ; JOY_WL        ; 7.882  ; 7.882  ; 7.882  ; 7.882  ;
; FC[0]        ; RAM_ADR[8]    ; 9.001  ; 9.001  ; 9.001  ; 9.001  ;
; FC[0]        ; RAM_BA[0]     ; 8.197  ; 8.197  ; 8.197  ; 8.197  ;
; FC[0]        ; RAM_BA[1]     ; 7.673  ; 7.673  ; 7.673  ; 7.673  ;
; FC[0]        ; RAM_CAS0n     ; 9.139  ; 9.139  ; 9.139  ; 9.139  ;
; FC[0]        ; RAM_CAS1n     ; 8.553  ; 8.553  ; 8.553  ; 8.553  ;
; FC[0]        ; RAM_DATA[0]   ; 9.831  ; 9.831  ; 9.831  ; 9.831  ;
; FC[0]        ; RAM_DATA[1]   ; 9.657  ; 9.657  ; 9.657  ; 9.657  ;
; FC[0]        ; RAM_DATA[2]   ; 9.542  ; 9.542  ; 9.542  ; 9.542  ;
; FC[0]        ; RAM_DATA[3]   ; 9.447  ; 9.447  ; 9.447  ; 9.447  ;
; FC[0]        ; RAM_DATA[4]   ; 9.703  ; 9.703  ; 9.703  ; 9.703  ;
; FC[0]        ; RAM_DATA[5]   ; 9.737  ; 9.737  ; 9.737  ; 9.737  ;
; FC[0]        ; RAM_DATA[6]   ; 9.834  ; 9.834  ; 9.834  ; 9.834  ;
; FC[0]        ; RAM_DATA[7]   ; 10.097 ; 10.097 ; 10.097 ; 10.097 ;
; FC[0]        ; RAM_DATA[8]   ; 10.415 ; 10.415 ; 10.415 ; 10.415 ;
; FC[0]        ; RAM_DATA[9]   ; 10.016 ; 10.016 ; 10.016 ; 10.016 ;
; FC[0]        ; RAM_DATA[10]  ; 9.755  ; 9.755  ; 9.755  ; 9.755  ;
; FC[0]        ; RAM_DATA[11]  ; 9.669  ; 9.669  ; 9.669  ; 9.669  ;
; FC[0]        ; RAM_DATA[12]  ; 9.551  ; 9.551  ; 9.551  ; 9.551  ;
; FC[0]        ; RAM_DATA[13]  ; 9.460  ; 9.460  ; 9.460  ; 9.460  ;
; FC[0]        ; RAM_DATA[14]  ; 9.676  ; 9.676  ; 9.676  ; 9.676  ;
; FC[0]        ; RAM_DATA[15]  ; 9.512  ; 9.512  ; 9.512  ; 9.512  ;
; FC[0]        ; RAM_DQM0H     ; 8.725  ; 8.725  ; 8.725  ; 8.725  ;
; FC[0]        ; RAM_DQM0L     ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; FC[0]        ; RAM_DQM1H     ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; FC[0]        ; RAM_DQM1L     ; 8.617  ; 8.617  ; 8.617  ; 8.617  ;
; FC[0]        ; RAM_RAS0n     ; 9.094  ; 9.094  ; 9.094  ; 9.094  ;
; FC[0]        ; RAM_RAS1n     ; 9.061  ; 9.061  ; 9.061  ; 9.061  ;
; FC[0]        ; ROM0n         ; 7.329  ; 7.329  ; 7.329  ; 7.329  ;
; FC[0]        ; ROM1n         ; 6.954  ; 6.954  ; 6.954  ; 6.954  ;
; FC[0]        ; ROM2n         ; 7.570  ; 7.570  ; 7.570  ; 7.570  ;
; FC[0]        ; ROM3n         ; 6.929  ; 6.929  ; 6.929  ; 6.929  ;
; FC[0]        ; ROM4n         ; 6.823  ; 6.823  ; 6.823  ; 6.823  ;
; FC[0]        ; ROM5n         ; 7.637  ; 7.637  ; 7.637  ; 7.637  ;
; FC[0]        ; ROM6n         ; 6.637  ; 6.637  ; 6.637  ; 6.637  ;
; FC[1]        ; ACSI_RDn      ; 8.303  ; 8.303  ; 8.303  ; 8.303  ;
; FC[1]        ; ACSI_WRn      ; 8.932  ; 8.932  ; 8.932  ; 8.932  ;
; FC[1]        ; BUTTONn       ; 8.100  ; 8.100  ; 8.100  ; 8.100  ;
; FC[1]        ; CA1_OUT       ; 8.856  ; 8.856  ; 8.856  ; 8.856  ;
; FC[1]        ; CD[0]         ; 9.181  ; 9.181  ; 9.181  ; 9.181  ;
; FC[1]        ; CD[1]         ; 9.064  ; 9.064  ; 9.064  ; 9.064  ;
; FC[1]        ; CD[2]         ; 8.664  ; 8.664  ; 8.664  ; 8.664  ;
; FC[1]        ; CD[3]         ; 9.064  ; 9.064  ; 9.064  ; 9.064  ;
; FC[1]        ; CD[4]         ; 8.824  ; 8.824  ; 8.824  ; 8.824  ;
; FC[1]        ; CD[5]         ; 9.033  ; 9.033  ; 9.033  ; 9.033  ;
; FC[1]        ; CD[6]         ; 8.992  ; 8.992  ; 8.992  ; 8.992  ;
; FC[1]        ; CD[7]         ; 8.512  ; 8.512  ; 8.512  ; 8.512  ;
; FC[1]        ; DATA[0]       ; 8.689  ; 8.689  ; 8.689  ; 8.689  ;
; FC[1]        ; DATA[1]       ; 8.750  ; 8.750  ; 8.750  ; 8.750  ;
; FC[1]        ; DATA[2]       ; 8.219  ; 8.219  ; 8.219  ; 8.219  ;
; FC[1]        ; DATA[3]       ; 8.321  ; 8.321  ; 8.321  ; 8.321  ;
; FC[1]        ; DATA[4]       ; 8.274  ; 8.274  ; 8.274  ; 8.274  ;
; FC[1]        ; DATA[5]       ; 8.603  ; 8.603  ; 8.603  ; 8.603  ;
; FC[1]        ; DATA[6]       ; 8.064  ; 8.064  ; 8.064  ; 8.064  ;
; FC[1]        ; DATA[7]       ; 8.167  ; 8.167  ; 8.167  ; 8.167  ;
; FC[1]        ; DATA[8]       ; 9.176  ; 9.176  ; 9.176  ; 9.176  ;
; FC[1]        ; DATA[9]       ; 8.938  ; 8.938  ; 8.938  ; 8.938  ;
; FC[1]        ; DATA[10]      ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; FC[1]        ; DATA[11]      ; 8.975  ; 8.975  ; 8.975  ; 8.975  ;
; FC[1]        ; DATA[12]      ; 8.696  ; 8.696  ; 8.696  ; 8.696  ;
; FC[1]        ; DATA[13]      ; 8.812  ; 8.812  ; 8.812  ; 8.812  ;
; FC[1]        ; DATA[14]      ; 9.394  ; 9.394  ; 9.394  ; 9.394  ;
; FC[1]        ; DATA[15]      ; 9.067  ; 9.067  ; 9.067  ; 9.067  ;
; FC[1]        ; DTACKn        ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; FC[1]        ; FLASH_CEn     ; 7.841  ; 7.841  ; 7.841  ; 7.841  ;
; FC[1]        ; FLASH_OEn     ; 8.050  ; 8.050  ; 8.050  ; 8.050  ;
; FC[1]        ; JOY_RHn       ; 8.798  ; 8.798  ; 8.798  ; 8.798  ;
; FC[1]        ; JOY_RLn       ; 8.469  ; 8.469  ; 8.469  ; 8.469  ;
; FC[1]        ; JOY_WEn       ; 8.551  ; 8.551  ; 8.551  ; 8.551  ;
; FC[1]        ; JOY_WL        ; 7.688  ; 7.688  ; 7.688  ; 7.688  ;
; FC[1]        ; RAM_ADR[8]    ; 8.991  ; 8.991  ; 8.991  ; 8.991  ;
; FC[1]        ; RAM_BA[0]     ; 8.187  ; 8.187  ; 8.187  ; 8.187  ;
; FC[1]        ; RAM_BA[1]     ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; FC[1]        ; RAM_CAS0n     ; 9.129  ; 9.129  ; 9.129  ; 9.129  ;
; FC[1]        ; RAM_CAS1n     ; 8.543  ; 8.543  ; 8.543  ; 8.543  ;
; FC[1]        ; RAM_DATA[0]   ; 9.637  ; 9.637  ; 9.637  ; 9.637  ;
; FC[1]        ; RAM_DATA[1]   ; 9.463  ; 9.463  ; 9.463  ; 9.463  ;
; FC[1]        ; RAM_DATA[2]   ; 9.348  ; 9.348  ; 9.348  ; 9.348  ;
; FC[1]        ; RAM_DATA[3]   ; 9.253  ; 9.253  ; 9.253  ; 9.253  ;
; FC[1]        ; RAM_DATA[4]   ; 9.509  ; 9.509  ; 9.509  ; 9.509  ;
; FC[1]        ; RAM_DATA[5]   ; 9.543  ; 9.543  ; 9.543  ; 9.543  ;
; FC[1]        ; RAM_DATA[6]   ; 9.640  ; 9.640  ; 9.640  ; 9.640  ;
; FC[1]        ; RAM_DATA[7]   ; 9.903  ; 9.903  ; 9.903  ; 9.903  ;
; FC[1]        ; RAM_DATA[8]   ; 10.221 ; 10.221 ; 10.221 ; 10.221 ;
; FC[1]        ; RAM_DATA[9]   ; 9.822  ; 9.822  ; 9.822  ; 9.822  ;
; FC[1]        ; RAM_DATA[10]  ; 9.561  ; 9.561  ; 9.561  ; 9.561  ;
; FC[1]        ; RAM_DATA[11]  ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[1]        ; RAM_DATA[12]  ; 9.357  ; 9.357  ; 9.357  ; 9.357  ;
; FC[1]        ; RAM_DATA[13]  ; 9.266  ; 9.266  ; 9.266  ; 9.266  ;
; FC[1]        ; RAM_DATA[14]  ; 9.482  ; 9.482  ; 9.482  ; 9.482  ;
; FC[1]        ; RAM_DATA[15]  ; 9.318  ; 9.318  ; 9.318  ; 9.318  ;
; FC[1]        ; RAM_DQM0H     ; 8.715  ; 8.715  ; 8.715  ; 8.715  ;
; FC[1]        ; RAM_DQM0L     ; 8.808  ; 8.808  ; 8.808  ; 8.808  ;
; FC[1]        ; RAM_DQM1H     ; 8.778  ; 8.778  ; 8.778  ; 8.778  ;
; FC[1]        ; RAM_DQM1L     ; 8.607  ; 8.607  ; 8.607  ; 8.607  ;
; FC[1]        ; RAM_RAS0n     ; 9.084  ; 9.084  ; 9.084  ; 9.084  ;
; FC[1]        ; RAM_RAS1n     ; 9.051  ; 9.051  ; 9.051  ; 9.051  ;
; FC[1]        ; ROM0n         ; 7.319  ; 7.319  ; 7.319  ; 7.319  ;
; FC[1]        ; ROM1n         ; 6.944  ; 6.944  ; 6.944  ; 6.944  ;
; FC[1]        ; ROM2n         ; 7.560  ; 7.560  ; 7.560  ; 7.560  ;
; FC[1]        ; ROM3n         ; 6.919  ; 6.919  ; 6.919  ; 6.919  ;
; FC[1]        ; ROM4n         ; 6.813  ; 6.813  ; 6.813  ; 6.813  ;
; FC[1]        ; ROM5n         ; 7.627  ; 7.627  ; 7.627  ; 7.627  ;
; FC[1]        ; ROM6n         ; 6.627  ; 6.627  ; 6.627  ; 6.627  ;
; FC[2]        ; ACSI_RDn      ; 8.393  ; 8.393  ; 8.393  ; 8.393  ;
; FC[2]        ; ACSI_WRn      ; 9.022  ; 9.022  ; 9.022  ; 9.022  ;
; FC[2]        ; CA1_OUT       ;        ; 8.946  ; 8.946  ;        ;
; FC[2]        ; CD[0]         ; 9.271  ; 9.271  ; 9.271  ; 9.271  ;
; FC[2]        ; CD[1]         ; 9.154  ; 9.154  ; 9.154  ; 9.154  ;
; FC[2]        ; CD[2]         ; 8.754  ; 8.796  ; 8.796  ; 8.754  ;
; FC[2]        ; CD[3]         ; 9.154  ; 9.154  ; 9.154  ; 9.154  ;
; FC[2]        ; CD[4]         ; 8.914  ; 8.914  ; 8.914  ; 8.914  ;
; FC[2]        ; CD[5]         ; 9.123  ; 9.123  ; 9.123  ; 9.123  ;
; FC[2]        ; CD[6]         ; 9.082  ; 9.082  ; 9.082  ; 9.082  ;
; FC[2]        ; CD[7]         ; 8.602  ; 8.602  ; 8.602  ; 8.602  ;
; FC[2]        ; DATA[0]       ; 8.960  ; 8.846  ; 8.846  ; 8.960  ;
; FC[2]        ; DATA[1]       ; 8.958  ; 8.907  ; 8.907  ; 8.958  ;
; FC[2]        ; DATA[2]       ; 8.792  ; 8.792  ; 8.792  ; 8.792  ;
; FC[2]        ; DATA[3]       ; 9.406  ; 8.905  ; 8.905  ; 9.406  ;
; FC[2]        ; DATA[4]       ; 8.949  ; 8.638  ; 8.638  ; 8.949  ;
; FC[2]        ; DATA[5]       ; 9.288  ; 9.077  ; 9.077  ; 9.288  ;
; FC[2]        ; DATA[6]       ; 8.777  ; 8.648  ; 8.648  ; 8.777  ;
; FC[2]        ; DATA[7]       ; 8.922  ; 8.581  ; 8.581  ; 8.922  ;
; FC[2]        ; DATA[8]       ; 10.649 ; 9.436  ; 9.436  ; 10.649 ;
; FC[2]        ; DATA[9]       ; 10.287 ; 9.176  ; 9.176  ; 10.287 ;
; FC[2]        ; DATA[10]      ; 10.548 ; 9.798  ; 9.798  ; 10.548 ;
; FC[2]        ; DATA[11]      ; 10.513 ; 9.525  ; 9.525  ; 10.513 ;
; FC[2]        ; DATA[12]      ; 10.011 ; 9.345  ; 9.345  ; 10.011 ;
; FC[2]        ; DATA[13]      ; 10.131 ; 9.457  ; 9.457  ; 10.131 ;
; FC[2]        ; DATA[14]      ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[2]        ; DATA[15]      ; 9.526  ; 9.526  ; 9.526  ; 9.526  ;
; FC[2]        ; DTACKn        ; 7.834  ; 7.834  ; 7.834  ; 7.834  ;
; FC[2]        ; JOY_RHn       ;        ; 8.888  ; 8.888  ;        ;
; FC[2]        ; JOY_RLn       ;        ; 8.559  ; 8.559  ;        ;
; FC[2]        ; JOY_WEn       ; 8.641  ;        ;        ; 8.641  ;
; FC[2]        ; JOY_WL        ; 7.778  ;        ;        ; 7.778  ;
; FC[2]        ; RAM_DATA[0]   ; 9.908  ; 9.794  ; 9.794  ; 9.908  ;
; FC[2]        ; RAM_DATA[1]   ; 9.671  ; 9.620  ; 9.620  ; 9.671  ;
; FC[2]        ; RAM_DATA[2]   ; 9.921  ; 9.921  ; 9.921  ; 9.921  ;
; FC[2]        ; RAM_DATA[3]   ; 10.338 ; 9.837  ; 9.837  ; 10.338 ;
; FC[2]        ; RAM_DATA[4]   ; 10.184 ; 9.873  ; 9.873  ; 10.184 ;
; FC[2]        ; RAM_DATA[5]   ; 10.228 ; 10.017 ; 10.017 ; 10.228 ;
; FC[2]        ; RAM_DATA[6]   ; 10.353 ; 10.224 ; 10.224 ; 10.353 ;
; FC[2]        ; RAM_DATA[7]   ; 10.658 ; 10.317 ; 10.317 ; 10.658 ;
; FC[2]        ; RAM_DATA[8]   ; 11.694 ; 10.481 ; 10.481 ; 11.694 ;
; FC[2]        ; RAM_DATA[9]   ; 11.171 ; 10.060 ; 10.060 ; 11.171 ;
; FC[2]        ; RAM_DATA[10]  ; 10.827 ; 10.077 ; 10.077 ; 10.827 ;
; FC[2]        ; RAM_DATA[11]  ; 11.013 ; 10.025 ; 10.025 ; 11.013 ;
; FC[2]        ; RAM_DATA[12]  ; 10.672 ; 10.006 ; 10.006 ; 10.672 ;
; FC[2]        ; RAM_DATA[13]  ; 10.585 ; 9.911  ; 9.911  ; 10.585 ;
; FC[2]        ; RAM_DATA[14]  ; 9.798  ; 9.798  ; 9.798  ; 9.798  ;
; FC[2]        ; RAM_DATA[15]  ; 9.777  ; 9.777  ; 9.777  ; 9.777  ;
; HDINTn       ; DATA[5]       ; 10.555 ;        ;        ; 10.555 ;
; HDINTn       ; DATA[13]      ; 11.038 ;        ;        ; 11.038 ;
; HDINTn       ; RAM_DATA[5]   ; 11.495 ;        ;        ; 11.495 ;
; HDINTn       ; RAM_DATA[13]  ; 11.492 ;        ;        ; 11.492 ;
; IDE_INTRQ    ; DATA[5]       ;        ; 10.692 ; 10.692 ;        ;
; IDE_INTRQ    ; DATA[13]      ;        ; 11.175 ; 11.175 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ;        ; 11.632 ; 11.632 ;        ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 11.629 ; 11.629 ;        ;
; IDE_IORDY    ; DTACKn        ; 9.443  ; 9.443  ; 9.443  ; 9.443  ;
; LDSn         ; ACSI_RDn      ; 8.057  ; 8.057  ; 8.057  ; 8.057  ;
; LDSn         ; ACSI_WRn      ; 8.686  ; 8.686  ; 8.686  ; 8.686  ;
; LDSn         ; BUTTONn       ; 7.446  ;        ;        ; 7.446  ;
; LDSn         ; CA1_OUT       ; 8.610  ;        ;        ; 8.610  ;
; LDSn         ; CD[0]         ; 8.935  ; 8.935  ; 8.935  ; 8.935  ;
; LDSn         ; CD[1]         ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; LDSn         ; CD[2]         ; 8.460  ; 8.418  ; 8.418  ; 8.460  ;
; LDSn         ; CD[3]         ; 8.818  ; 8.818  ; 8.818  ; 8.818  ;
; LDSn         ; CD[4]         ; 8.578  ; 8.578  ; 8.578  ; 8.578  ;
; LDSn         ; CD[5]         ; 8.787  ; 8.787  ; 8.787  ; 8.787  ;
; LDSn         ; CD[6]         ; 8.746  ; 8.746  ; 8.746  ; 8.746  ;
; LDSn         ; CD[7]         ; 8.266  ; 8.266  ; 8.266  ; 8.266  ;
; LDSn         ; DATA[0]       ; 8.423  ; 8.612  ; 8.612  ; 8.423  ;
; LDSn         ; DATA[1]       ; 8.743  ; 8.743  ; 8.743  ; 8.743  ;
; LDSn         ; DATA[2]       ; 8.400  ; 8.174  ; 8.174  ; 8.400  ;
; LDSn         ; DATA[3]       ; 8.648  ; 8.611  ; 8.611  ; 8.648  ;
; LDSn         ; DATA[4]       ; 8.328  ; 8.328  ; 8.328  ; 8.328  ;
; LDSn         ; DATA[5]       ; 8.432  ; 8.432  ; 8.432  ; 8.432  ;
; LDSn         ; DATA[6]       ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; LDSn         ; DATA[7]       ; 8.489  ; 8.294  ; 8.294  ; 8.489  ;
; LDSn         ; DATA[8]       ; 8.652  ; 8.652  ; 8.652  ; 8.652  ;
; LDSn         ; DATA[9]       ; 8.652  ; 8.652  ; 8.652  ; 8.652  ;
; LDSn         ; DATA[10]      ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; LDSn         ; DATA[11]      ; 8.788  ; 8.788  ; 8.788  ; 8.788  ;
; LDSn         ; DATA[12]      ; 8.709  ; 8.709  ; 8.709  ; 8.709  ;
; LDSn         ; DATA[13]      ; 8.829  ; 8.829  ; 8.829  ; 8.829  ;
; LDSn         ; DATA[14]      ; 8.836  ; 8.836  ; 8.836  ; 8.836  ;
; LDSn         ; DATA[15]      ; 8.826  ; 8.826  ; 8.826  ; 8.826  ;
; LDSn         ; DTACKn        ; 7.621  ; 7.621  ; 7.621  ; 7.621  ;
; LDSn         ; IDE_IORDn     ; 6.538  ;        ;        ; 6.538  ;
; LDSn         ; IDE_IOWRn     ; 7.028  ;        ;        ; 7.028  ;
; LDSn         ; JOY_RLn       ; 7.927  ;        ;        ; 7.927  ;
; LDSn         ; JOY_WEn       ;        ; 8.009  ; 8.009  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.860  ; 6.860  ;        ;
; LDSn         ; RAM_CAS0n     ; 7.850  ;        ;        ; 7.850  ;
; LDSn         ; RAM_CAS1n     ; 7.262  ;        ;        ; 7.262  ;
; LDSn         ; RAM_DATA[0]   ; 9.371  ; 9.560  ; 9.560  ; 9.371  ;
; LDSn         ; RAM_DATA[1]   ; 9.456  ; 9.456  ; 9.456  ; 9.456  ;
; LDSn         ; RAM_DATA[2]   ; 9.529  ; 9.303  ; 9.303  ; 9.529  ;
; LDSn         ; RAM_DATA[3]   ; 9.580  ; 9.543  ; 9.543  ; 9.580  ;
; LDSn         ; RAM_DATA[4]   ; 9.563  ; 9.563  ; 9.563  ; 9.563  ;
; LDSn         ; RAM_DATA[5]   ; 9.372  ; 9.372  ; 9.372  ; 9.372  ;
; LDSn         ; RAM_DATA[6]   ; 9.719  ; 9.719  ; 9.719  ; 9.719  ;
; LDSn         ; RAM_DATA[7]   ; 10.276 ; 10.030 ; 10.030 ; 10.276 ;
; LDSn         ; RAM_DATA[8]   ; 10.041 ; 10.371 ; 10.371 ; 10.041 ;
; LDSn         ; RAM_DATA[9]   ; 9.869  ; 9.869  ; 9.869  ; 9.869  ;
; LDSn         ; RAM_DATA[10]  ; 9.525  ; 9.525  ; 9.525  ; 9.525  ;
; LDSn         ; RAM_DATA[11]  ; 9.565  ; 9.565  ; 9.565  ; 9.565  ;
; LDSn         ; RAM_DATA[12]  ; 9.370  ; 9.370  ; 9.370  ; 9.370  ;
; LDSn         ; RAM_DATA[13]  ; 9.283  ; 9.283  ; 9.283  ; 9.283  ;
; LDSn         ; RAM_DATA[14]  ; 9.282  ; 9.282  ; 9.282  ; 9.282  ;
; LDSn         ; RAM_DATA[15]  ; 9.438  ; 9.438  ; 9.438  ; 9.438  ;
; LDSn         ; RAM_DQM0L     ; 7.239  ;        ;        ; 7.239  ;
; LDSn         ; RAM_DQM1L     ; 7.044  ;        ;        ; 7.044  ;
; LPT_BSY      ; DATA[0]       ; 10.282 ;        ;        ; 10.282 ;
; LPT_BSY      ; DATA[8]       ; 11.099 ;        ;        ; 11.099 ;
; LPT_BSY      ; RAM_DATA[0]   ; 11.230 ;        ;        ; 11.230 ;
; LPT_BSY      ; RAM_DATA[8]   ; 12.144 ;        ;        ; 12.144 ;
; LPT_D[0]     ; DATA[0]       ; 8.799  ;        ;        ; 8.799  ;
; LPT_D[0]     ; DATA[8]       ; 9.505  ;        ;        ; 9.505  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 9.747  ;        ;        ; 9.747  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 10.550 ;        ;        ; 10.550 ;
; LPT_D[1]     ; DATA[1]       ; 9.348  ;        ;        ; 9.348  ;
; LPT_D[1]     ; DATA[9]       ; 9.415  ;        ;        ; 9.415  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 10.061 ;        ;        ; 10.061 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 10.299 ;        ;        ; 10.299 ;
; LPT_D[2]     ; DATA[2]       ; 9.111  ;        ;        ; 9.111  ;
; LPT_D[2]     ; DATA[10]      ; 10.122 ;        ;        ; 10.122 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 10.240 ;        ;        ; 10.240 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 10.401 ;        ;        ; 10.401 ;
; LPT_D[3]     ; DATA[3]       ; 9.269  ;        ;        ; 9.269  ;
; LPT_D[3]     ; DATA[11]      ; 9.890  ;        ;        ; 9.890  ;
; LPT_D[3]     ; RAM_DATA[3]   ; 10.201 ;        ;        ; 10.201 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 10.390 ;        ;        ; 10.390 ;
; LPT_D[4]     ; DATA[4]       ; 9.991  ;        ;        ; 9.991  ;
; LPT_D[4]     ; DATA[12]      ; 10.465 ;        ;        ; 10.465 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.226 ;        ;        ; 11.226 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 11.126 ;        ;        ; 11.126 ;
; LPT_D[5]     ; DATA[5]       ; 9.074  ;        ;        ; 9.074  ;
; LPT_D[5]     ; DATA[13]      ; 9.802  ;        ;        ; 9.802  ;
; LPT_D[5]     ; RAM_DATA[5]   ; 10.014 ;        ;        ; 10.014 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 10.256 ;        ;        ; 10.256 ;
; LPT_D[6]     ; DATA[6]       ; 9.006  ;        ;        ; 9.006  ;
; LPT_D[6]     ; DATA[14]      ; 10.251 ; 10.251 ; 10.251 ; 10.251 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 10.582 ;        ;        ; 10.582 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 10.339 ; 10.339 ; 10.339 ; 10.339 ;
; LPT_D[7]     ; DATA[7]       ; 9.165  ;        ;        ; 9.165  ;
; LPT_D[7]     ; DATA[15]      ; 10.014 ; 10.014 ; 10.014 ; 10.014 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.901 ;        ;        ; 10.901 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; MIDI_IN      ; MIDI_TLR      ; 4.716  ;        ;        ; 4.716  ;
; RAM_DATA[0]  ; DATA[0]       ; 9.865  ;        ;        ; 9.865  ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.813 ;        ;        ; 10.813 ;
; RAM_DATA[1]  ; DATA[1]       ; 10.692 ;        ;        ; 10.692 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 11.405 ;        ;        ; 11.405 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.678 ;        ;        ; 10.678 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 11.807 ;        ;        ; 11.807 ;
; RAM_DATA[3]  ; DATA[3]       ; 9.963  ;        ;        ; 9.963  ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.895 ;        ;        ; 10.895 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.697  ;        ;        ; 9.697  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[5]  ; DATA[5]       ; 10.385 ;        ;        ; 10.385 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 11.325 ;        ;        ; 11.325 ;
; RAM_DATA[6]  ; DATA[6]       ; 9.820  ;        ;        ; 9.820  ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.396 ;        ;        ; 11.396 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.099 ;        ;        ; 10.099 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 11.835 ;        ;        ; 11.835 ;
; RAM_DATA[8]  ; DATA[8]       ; 11.045 ;        ;        ; 11.045 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 12.090 ;        ;        ; 12.090 ;
; RAM_DATA[9]  ; DATA[9]       ; 10.424 ;        ;        ; 10.424 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 11.308 ;        ;        ; 11.308 ;
; RAM_DATA[10] ; DATA[10]      ; 10.932 ;        ;        ; 10.932 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 11.211 ;        ;        ; 11.211 ;
; RAM_DATA[11] ; DATA[11]      ; 10.739 ;        ;        ; 10.739 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 11.239 ;        ;        ; 11.239 ;
; RAM_DATA[12] ; DATA[12]      ; 10.066 ;        ;        ; 10.066 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 10.727 ;        ;        ; 10.727 ;
; RAM_DATA[13] ; DATA[13]      ; 10.635 ;        ;        ; 10.635 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 11.089 ;        ;        ; 11.089 ;
; RAM_DATA[14] ; DATA[14]      ; 10.811 ; 10.811 ; 10.811 ; 10.811 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.899 ; 10.899 ; 10.899 ; 10.899 ;
; RAM_DATA[15] ; DATA[15]      ; 11.044 ; 11.044 ; 11.044 ; 11.044 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 11.295 ; 11.295 ; 11.295 ; 11.295 ;
; RWn          ; ACSI_RDn      ; 8.039  ; 7.063  ; 7.063  ; 8.039  ;
; RWn          ; ACSI_WRn      ; 7.692  ; 8.668  ; 8.668  ; 7.692  ;
; RWn          ; BUTTONn       ;        ; 7.486  ; 7.486  ;        ;
; RWn          ; CA1_OUT       ;        ; 8.592  ; 8.592  ;        ;
; RWn          ; CD[0]         ; 7.780  ; 7.780  ; 7.780  ; 7.780  ;
; RWn          ; CD[1]         ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; RWn          ; CD[2]         ; 7.191  ; 7.149  ; 7.149  ; 7.191  ;
; RWn          ; CD[3]         ; 7.663  ; 7.663  ; 7.663  ; 7.663  ;
; RWn          ; CD[4]         ; 7.309  ; 7.309  ; 7.309  ; 7.309  ;
; RWn          ; CD[5]         ; 7.518  ; 7.518  ; 7.518  ; 7.518  ;
; RWn          ; CD[6]         ; 7.477  ; 7.477  ; 7.477  ; 7.477  ;
; RWn          ; CD[7]         ; 7.034  ; 7.034  ; 7.034  ; 7.034  ;
; RWn          ; DATA[0]       ; 7.969  ; 7.969  ; 7.969  ; 7.969  ;
; RWn          ; DATA[1]       ; 8.385  ; 8.338  ; 8.338  ; 8.385  ;
; RWn          ; DATA[2]       ; 7.653  ; 7.591  ; 7.591  ; 7.653  ;
; RWn          ; DATA[3]       ; 8.052  ; 7.693  ; 7.693  ; 8.052  ;
; RWn          ; DATA[4]       ; 7.899  ; 7.646  ; 7.646  ; 7.899  ;
; RWn          ; DATA[5]       ; 8.246  ; 7.975  ; 7.975  ; 8.246  ;
; RWn          ; DATA[6]       ; 7.934  ; 7.436  ; 7.436  ; 7.934  ;
; RWn          ; DATA[7]       ; 7.747  ; 7.539  ; 7.539  ; 7.747  ;
; RWn          ; DATA[8]       ; 8.706  ; 8.548  ; 8.548  ; 8.706  ;
; RWn          ; DATA[9]       ; 8.689  ; 8.310  ; 8.310  ; 8.689  ;
; RWn          ; DATA[10]      ; 8.719  ; 8.654  ; 8.654  ; 8.719  ;
; RWn          ; DATA[11]      ; 8.842  ; 8.347  ; 8.347  ; 8.842  ;
; RWn          ; DATA[12]      ; 8.625  ; 8.277  ; 8.277  ; 8.625  ;
; RWn          ; DATA[13]      ; 8.618  ; 8.393  ; 8.393  ; 8.618  ;
; RWn          ; DATA[14]      ; 8.477  ; 8.477  ; 8.477  ; 8.477  ;
; RWn          ; DATA[15]      ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; RWn          ; DTACKn        ; 7.480  ; 7.480  ; 7.480  ; 7.480  ;
; RWn          ; FLASH_CEn     ;        ; 7.094  ; 7.094  ;        ;
; RWn          ; FLASH_OEn     ;        ; 7.303  ; 7.303  ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 7.192  ; 7.192  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 6.436  ;        ;        ; 6.436  ;
; RWn          ; IDE_IORDn     ;        ; 6.489  ; 6.489  ;        ;
; RWn          ; IDE_IOWRn     ; 6.977  ;        ;        ; 6.977  ;
; RWn          ; JOY_RHn       ;        ; 7.159  ; 7.159  ;        ;
; RWn          ; JOY_RLn       ;        ; 7.674  ; 7.674  ;        ;
; RWn          ; JOY_WEn       ; 7.756  ;        ;        ; 7.756  ;
; RWn          ; JOY_WL        ; 7.424  ; 6.804  ; 6.804  ; 7.424  ;
; RWn          ; RAM_DATA[0]   ; 7.672  ; 7.672  ; 7.672  ; 7.672  ;
; RWn          ; RAM_DATA[1]   ; 7.060  ; 7.060  ; 7.060  ; 7.060  ;
; RWn          ; RAM_DATA[2]   ; 7.507  ; 7.507  ; 7.507  ; 7.507  ;
; RWn          ; RAM_DATA[3]   ; 7.326  ; 7.326  ; 7.326  ; 7.326  ;
; RWn          ; RAM_DATA[4]   ; 7.420  ; 7.420  ; 7.420  ; 7.420  ;
; RWn          ; RAM_DATA[5]   ; 7.537  ; 7.537  ; 7.537  ; 7.537  ;
; RWn          ; RAM_DATA[6]   ; 7.585  ; 7.585  ; 7.585  ; 7.585  ;
; RWn          ; RAM_DATA[7]   ; 7.572  ; 7.572  ; 7.572  ; 7.572  ;
; RWn          ; RAM_DATA[8]   ; 7.495  ; 7.495  ; 7.495  ; 7.495  ;
; RWn          ; RAM_DATA[9]   ; 7.541  ; 7.541  ; 7.541  ; 7.541  ;
; RWn          ; RAM_DATA[10]  ; 7.111  ; 7.187  ; 7.187  ; 7.111  ;
; RWn          ; RAM_DATA[11]  ; 7.015  ; 7.087  ; 7.087  ; 7.015  ;
; RWn          ; RAM_DATA[12]  ; 7.312  ; 7.312  ; 7.312  ; 7.312  ;
; RWn          ; RAM_DATA[13]  ; 6.967  ; 6.967  ; 6.967  ; 6.967  ;
; RWn          ; RAM_DATA[14]  ; 6.992  ; 6.992  ; 6.992  ; 6.992  ;
; RWn          ; RAM_DATA[15]  ; 7.118  ; 7.118  ; 7.118  ; 7.118  ;
; RWn          ; RAM_WEn       ; 7.215  ;        ;        ; 7.215  ;
; RWn          ; ROM0n         ;        ; 7.133  ; 7.133  ;        ;
; RWn          ; ROM1n         ;        ; 6.758  ; 6.758  ;        ;
; RWn          ; ROM2n         ;        ; 6.813  ; 6.813  ;        ;
; RWn          ; ROM3n         ;        ; 6.733  ; 6.733  ;        ;
; RWn          ; ROM4n         ;        ; 6.627  ; 6.627  ;        ;
; RWn          ; ROM5n         ;        ; 7.441  ; 7.441  ;        ;
; RWn          ; ROM6n         ;        ; 6.441  ; 6.441  ;        ;
; SCSI_ACKn    ; CD[0]         ; 7.502  ; 7.502  ; 7.502  ; 7.502  ;
; SCSI_ATNn    ; CD[1]         ; 8.338  ; 8.338  ; 8.338  ; 8.338  ;
; SCSI_BSYn    ; CD[6]         ; 10.200 ; 10.200 ; 10.200 ; 10.200 ;
; SCSI_D[0]    ; CD[0]         ; 7.818  ; 7.818  ; 7.818  ; 7.818  ;
; SCSI_D[1]    ; CD[1]         ; 7.467  ; 7.467  ; 7.467  ; 7.467  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.645  ; 7.645  ;        ;
; SCSI_D[3]    ; CD[3]         ; 7.458  ; 7.458  ; 7.458  ; 7.458  ;
; SCSI_D[4]    ; CD[4]         ; 10.375 ; 10.375 ; 10.375 ; 10.375 ;
; SCSI_D[5]    ; CD[5]         ; 10.138 ; 10.138 ; 10.138 ; 10.138 ;
; SCSI_D[6]    ; CD[6]         ; 10.212 ; 10.212 ; 10.212 ; 10.212 ;
; SCSI_D[7]    ; CD[7]         ; 8.008  ; 8.008  ; 8.008  ; 8.008  ;
; SCSI_DCn     ; CD[3]         ; 7.703  ; 7.703  ; 7.703  ; 7.703  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.758  ; 7.758  ; 7.758  ; 7.758  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.204  ; 7.204  ; 7.204  ; 7.204  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.003  ; 7.003  ; 7.003  ; 7.003  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.123  ; 7.123  ; 7.123  ; 7.123  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.227  ; 7.227  ; 7.227  ; 7.227  ;
; SCSI_DCn     ; SCSI_DP       ; 7.214  ; 7.214  ; 7.214  ; 7.214  ;
; SCSI_DP      ; CD[0]         ; 7.345  ; 7.345  ; 7.345  ; 7.345  ;
; SCSI_IDn[1]  ; SCSI_D[0]     ;        ; 6.002  ; 6.002  ;        ;
; SCSI_IDn[1]  ; SCSI_D[1]     ; 6.217  ;        ;        ; 6.217  ;
; SCSI_IDn[1]  ; SCSI_D[2]     ;        ; 6.034  ; 6.034  ;        ;
; SCSI_IDn[1]  ; SCSI_D[3]     ; 6.118  ;        ;        ; 6.118  ;
; SCSI_IDn[1]  ; SCSI_D[4]     ;        ; 6.290  ; 6.290  ;        ;
; SCSI_IDn[1]  ; SCSI_D[5]     ; 6.098  ;        ;        ; 6.098  ;
; SCSI_IDn[1]  ; SCSI_D[6]     ;        ; 6.578  ; 6.578  ;        ;
; SCSI_IDn[1]  ; SCSI_D[7]     ; 6.278  ;        ;        ; 6.278  ;
; SCSI_IDn[1]  ; SCSI_DP       ; 6.282  ; 6.282  ; 6.282  ; 6.282  ;
; SCSI_IDn[2]  ; SCSI_D[0]     ;        ; 5.746  ; 5.746  ;        ;
; SCSI_IDn[2]  ; SCSI_D[1]     ;        ; 5.996  ; 5.996  ;        ;
; SCSI_IDn[2]  ; SCSI_D[2]     ; 5.776  ;        ;        ; 5.776  ;
; SCSI_IDn[2]  ; SCSI_D[3]     ; 5.885  ;        ;        ; 5.885  ;
; SCSI_IDn[2]  ; SCSI_D[4]     ;        ; 6.036  ; 6.036  ;        ;
; SCSI_IDn[2]  ; SCSI_D[5]     ;        ; 5.880  ; 5.880  ;        ;
; SCSI_IDn[2]  ; SCSI_D[6]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[2]  ; SCSI_D[7]     ; 6.044  ;        ;        ; 6.044  ;
; SCSI_IDn[2]  ; SCSI_DP       ; 6.061  ; 6.061  ; 6.061  ; 6.061  ;
; SCSI_IDn[3]  ; SCSI_D[0]     ;        ; 6.042  ; 6.042  ;        ;
; SCSI_IDn[3]  ; SCSI_D[1]     ;        ; 6.291  ; 6.291  ;        ;
; SCSI_IDn[3]  ; SCSI_D[2]     ;        ; 6.069  ; 6.069  ;        ;
; SCSI_IDn[3]  ; SCSI_D[3]     ;        ; 6.179  ; 6.179  ;        ;
; SCSI_IDn[3]  ; SCSI_D[4]     ; 6.326  ;        ;        ; 6.326  ;
; SCSI_IDn[3]  ; SCSI_D[5]     ; 6.170  ;        ;        ; 6.170  ;
; SCSI_IDn[3]  ; SCSI_D[6]     ; 6.623  ;        ;        ; 6.623  ;
; SCSI_IDn[3]  ; SCSI_D[7]     ; 6.340  ;        ;        ; 6.340  ;
; SCSI_IDn[3]  ; SCSI_DP       ; 6.356  ; 6.356  ; 6.356  ; 6.356  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.849  ; 7.849  ;        ;
; SCSI_IOn     ; CD[3]         ; 7.914  ; 7.914  ; 7.914  ; 7.914  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.577  ; 7.460  ; 7.460  ; 6.577  ;
; SCSI_IOn     ; SCSI_D[0]     ; 6.023  ; 6.023  ; 6.023  ; 6.023  ;
; SCSI_IOn     ; SCSI_D[1]     ; 6.023  ; 6.023  ; 6.023  ; 6.023  ;
; SCSI_IOn     ; SCSI_D[2]     ; 5.822  ; 5.822  ; 5.822  ; 5.822  ;
; SCSI_IOn     ; SCSI_D[3]     ; 5.822  ; 5.822  ; 5.822  ; 5.822  ;
; SCSI_IOn     ; SCSI_D[4]     ; 5.942  ; 5.942  ; 5.942  ; 5.942  ;
; SCSI_IOn     ; SCSI_D[5]     ; 5.942  ; 5.942  ; 5.942  ; 5.942  ;
; SCSI_IOn     ; SCSI_D[6]     ; 6.046  ; 6.046  ; 6.046  ; 6.046  ;
; SCSI_IOn     ; SCSI_D[7]     ; 6.046  ; 6.046  ; 6.046  ; 6.046  ;
; SCSI_IOn     ; SCSI_DP       ; 6.033  ; 6.033  ; 6.033  ; 6.033  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.523  ;        ;        ; 6.523  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.463  ; 6.463  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.066  ; 8.066  ; 8.066  ; 8.066  ;
; SCSI_MSGn    ; CD[4]         ; 9.988  ; 9.988  ; 9.988  ; 9.988  ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.612  ; 7.612  ; 7.612  ; 7.612  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.058  ; 7.058  ; 7.058  ; 7.058  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 6.857  ; 6.857  ; 6.857  ; 6.857  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 6.977  ; 6.977  ; 6.977  ; 6.977  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.081  ; 7.081  ; 7.081  ; 7.081  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.068  ; 7.068  ; 7.068  ; 7.068  ;
; SCSI_REQn    ; CD[3]         ; 8.082  ; 8.082  ; 8.082  ; 8.082  ;
; SCSI_REQn    ; CD[5]         ; 9.873  ; 9.873  ; 9.873  ; 9.873  ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.628  ;        ;        ; 7.628  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.074  ; 7.074  ; 7.074  ; 7.074  ;
; SCSI_REQn    ; SCSI_D[2]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[3]     ; 6.873  ; 6.873  ; 6.873  ; 6.873  ;
; SCSI_REQn    ; SCSI_D[4]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[5]     ; 6.993  ; 6.993  ; 6.993  ; 6.993  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.097  ; 7.097  ; 7.097  ; 7.097  ;
; SCSI_REQn    ; SCSI_DP       ; 7.084  ; 7.084  ; 7.084  ; 7.084  ;
; SCSI_RSTn    ; CD[7]         ;        ; 8.248  ; 8.248  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.409  ; 7.409  ; 7.409  ; 7.409  ;
; SD_AVR_ENn   ; RESETn        ;        ; 8.539  ; 8.539  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 6.467  ; 6.467  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 5.432  ; 5.432  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.457  ;        ;        ; 6.457  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.305  ;        ;        ; 6.305  ;
; SD_RESETn    ; ACSI_RDn      ; 9.176  ; 9.176  ; 9.176  ; 9.176  ;
; SD_RESETn    ; ACSI_WRn      ; 9.805  ; 9.805  ; 9.805  ; 9.805  ;
; SD_RESETn    ; CA1_OUT       ; 9.729  ;        ;        ; 9.729  ;
; SD_RESETn    ; CD[0]         ; 10.054 ; 10.054 ; 10.054 ; 10.054 ;
; SD_RESETn    ; CD[1]         ; 9.937  ; 9.937  ; 9.937  ; 9.937  ;
; SD_RESETn    ; CD[2]         ; 9.579  ; 9.537  ; 9.537  ; 9.579  ;
; SD_RESETn    ; CD[3]         ; 9.937  ; 9.937  ; 9.937  ; 9.937  ;
; SD_RESETn    ; CD[4]         ; 9.697  ; 9.697  ; 9.697  ; 9.697  ;
; SD_RESETn    ; CD[5]         ; 9.906  ; 9.906  ; 9.906  ; 9.906  ;
; SD_RESETn    ; CD[6]         ; 9.865  ; 9.865  ; 9.865  ; 9.865  ;
; SD_RESETn    ; CD[7]         ; 9.385  ; 9.385  ; 9.385  ; 9.385  ;
; SD_RESETn    ; COM_TxD       ; 8.602  ; 8.602  ; 8.602  ; 8.602  ;
; SD_RESETn    ; DATA[0]       ; 9.699  ; 9.741  ; 9.741  ; 9.699  ;
; SD_RESETn    ; DATA[1]       ; 10.019 ; 10.019 ; 10.019 ; 10.019 ;
; SD_RESETn    ; DATA[2]       ; 9.573  ; 9.450  ; 9.450  ; 9.573  ;
; SD_RESETn    ; DATA[3]       ; 10.117 ; 9.952  ; 9.952  ; 10.117 ;
; SD_RESETn    ; DATA[4]       ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; SD_RESETn    ; DATA[5]       ; 9.708  ; 9.708  ; 9.708  ; 9.708  ;
; SD_RESETn    ; DATA[6]       ; 9.419  ; 9.419  ; 9.419  ; 9.419  ;
; SD_RESETn    ; DATA[7]       ; 9.839  ; 9.630  ; 9.630  ; 9.839  ;
; SD_RESETn    ; DATA[8]       ; 10.272 ; 10.623 ; 10.623 ; 10.272 ;
; SD_RESETn    ; DATA[9]       ; 10.232 ; 10.261 ; 10.261 ; 10.232 ;
; SD_RESETn    ; DATA[10]      ; 10.522 ; 10.522 ; 10.522 ; 10.522 ;
; SD_RESETn    ; DATA[11]      ; 10.487 ; 10.487 ; 10.487 ; 10.487 ;
; SD_RESETn    ; DATA[12]      ; 9.985  ; 9.985  ; 9.985  ; 9.985  ;
; SD_RESETn    ; DATA[13]      ; 10.105 ; 10.105 ; 10.105 ; 10.105 ;
; SD_RESETn    ; DATA[14]      ; 10.641 ; 10.641 ; 10.641 ; 10.641 ;
; SD_RESETn    ; DATA[15]      ; 10.307 ; 10.307 ; 10.307 ; 10.307 ;
; SD_RESETn    ; DTACKn        ; 8.740  ; 8.740  ; 8.740  ; 8.740  ;
; SD_RESETn    ; RAM_DATA[0]   ; 10.647 ; 10.689 ; 10.689 ; 10.647 ;
; SD_RESETn    ; RAM_DATA[1]   ; 10.732 ; 10.732 ; 10.732 ; 10.732 ;
; SD_RESETn    ; RAM_DATA[2]   ; 10.702 ; 10.579 ; 10.579 ; 10.702 ;
; SD_RESETn    ; RAM_DATA[3]   ; 11.049 ; 10.884 ; 10.884 ; 11.049 ;
; SD_RESETn    ; RAM_DATA[4]   ; 10.839 ; 10.839 ; 10.839 ; 10.839 ;
; SD_RESETn    ; RAM_DATA[5]   ; 10.648 ; 10.648 ; 10.648 ; 10.648 ;
; SD_RESETn    ; RAM_DATA[6]   ; 10.995 ; 10.995 ; 10.995 ; 10.995 ;
; SD_RESETn    ; RAM_DATA[7]   ; 11.575 ; 11.366 ; 11.366 ; 11.575 ;
; SD_RESETn    ; RAM_DATA[8]   ; 11.317 ; 11.668 ; 11.668 ; 11.317 ;
; SD_RESETn    ; RAM_DATA[9]   ; 11.116 ; 11.145 ; 11.145 ; 11.116 ;
; SD_RESETn    ; RAM_DATA[10]  ; 10.801 ; 10.801 ; 10.801 ; 10.801 ;
; SD_RESETn    ; RAM_DATA[11]  ; 10.987 ; 10.987 ; 10.987 ; 10.987 ;
; SD_RESETn    ; RAM_DATA[12]  ; 10.646 ; 10.646 ; 10.646 ; 10.646 ;
; SD_RESETn    ; RAM_DATA[13]  ; 10.559 ; 10.559 ; 10.559 ; 10.559 ;
; SD_RESETn    ; RAM_DATA[14]  ; 10.729 ; 10.729 ; 10.729 ; 10.729 ;
; SD_RESETn    ; RAM_DATA[15]  ; 10.558 ; 10.558 ; 10.558 ; 10.558 ;
; UDSn         ; ACSI_RDn      ; 8.810  ; 8.810  ; 8.810  ; 8.810  ;
; UDSn         ; ACSI_WRn      ; 9.439  ; 9.439  ; 9.439  ; 9.439  ;
; UDSn         ; CA1_OUT       ; 9.363  ;        ;        ; 9.363  ;
; UDSn         ; CD[0]         ; 9.688  ; 9.688  ; 9.688  ; 9.688  ;
; UDSn         ; CD[1]         ; 9.571  ; 9.571  ; 9.571  ; 9.571  ;
; UDSn         ; CD[2]         ; 9.213  ; 9.171  ; 9.171  ; 9.213  ;
; UDSn         ; CD[3]         ; 9.571  ; 9.571  ; 9.571  ; 9.571  ;
; UDSn         ; CD[4]         ; 9.331  ; 9.331  ; 9.331  ; 9.331  ;
; UDSn         ; CD[5]         ; 9.540  ; 9.540  ; 9.540  ; 9.540  ;
; UDSn         ; CD[6]         ; 9.499  ; 9.499  ; 9.499  ; 9.499  ;
; UDSn         ; CD[7]         ; 9.019  ; 9.019  ; 9.019  ; 9.019  ;
; UDSn         ; DATA[0]       ; 8.734  ; 8.734  ; 8.734  ; 8.734  ;
; UDSn         ; DATA[1]       ; 8.722  ; 8.734  ; 8.734  ; 8.722  ;
; UDSn         ; DATA[2]       ; 8.568  ; 8.596  ; 8.596  ; 8.568  ;
; UDSn         ; DATA[3]       ; 8.596  ; 8.555  ; 8.555  ; 8.596  ;
; UDSn         ; DATA[4]       ; 8.528  ; 8.588  ; 8.588  ; 8.528  ;
; UDSn         ; DATA[5]       ; 8.588  ; 8.588  ; 8.588  ; 8.588  ;
; UDSn         ; DATA[6]       ; 8.380  ; 8.443  ; 8.443  ; 8.380  ;
; UDSn         ; DATA[7]       ; 8.433  ; 8.433  ; 8.433  ; 8.433  ;
; UDSn         ; DATA[8]       ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; UDSn         ; DATA[9]       ; 8.596  ; 8.596  ; 8.596  ; 8.596  ;
; UDSn         ; DATA[10]      ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; UDSn         ; DATA[11]      ; 8.732  ; 8.732  ; 8.732  ; 8.732  ;
; UDSn         ; DATA[12]      ; 8.774  ; 8.774  ; 8.774  ; 8.774  ;
; UDSn         ; DATA[13]      ; 8.774  ; 8.774  ; 8.774  ; 8.774  ;
; UDSn         ; DATA[14]      ; 8.780  ; 8.780  ; 8.780  ; 8.780  ;
; UDSn         ; DATA[15]      ; 8.770  ; 8.770  ; 8.770  ; 8.770  ;
; UDSn         ; DTACKn        ; 7.904  ; 7.904  ; 7.904  ; 7.904  ;
; UDSn         ; JOY_RHn       ; 7.055  ;        ;        ; 7.055  ;
; UDSn         ; RAM_CAS0n     ; 7.564  ;        ;        ; 7.564  ;
; UDSn         ; RAM_CAS1n     ; 6.976  ;        ;        ; 6.976  ;
; UDSn         ; RAM_DATA[0]   ; 9.975  ; 9.933  ; 9.933  ; 9.975  ;
; UDSn         ; RAM_DATA[1]   ; 9.435  ; 9.580  ; 9.580  ; 9.435  ;
; UDSn         ; RAM_DATA[2]   ; 9.697  ; 9.974  ; 9.974  ; 9.697  ;
; UDSn         ; RAM_DATA[3]   ; 9.617  ; 9.487  ; 9.487  ; 9.617  ;
; UDSn         ; RAM_DATA[4]   ; 9.763  ; 9.869  ; 9.869  ; 9.763  ;
; UDSn         ; RAM_DATA[5]   ; 9.853  ; 9.872  ; 9.872  ; 9.853  ;
; UDSn         ; RAM_DATA[6]   ; 9.956  ; 10.049 ; 10.049 ; 9.956  ;
; UDSn         ; RAM_DATA[7]   ; 10.220 ; 10.310 ; 10.310 ; 10.220 ;
; UDSn         ; RAM_DATA[8]   ; 10.502 ; 10.555 ; 10.555 ; 10.502 ;
; UDSn         ; RAM_DATA[9]   ; 10.404 ; 10.432 ; 10.432 ; 10.404 ;
; UDSn         ; RAM_DATA[10]  ; 9.663  ; 9.663  ; 9.663  ; 9.663  ;
; UDSn         ; RAM_DATA[11]  ; 9.509  ; 9.509  ; 9.509  ; 9.509  ;
; UDSn         ; RAM_DATA[12]  ; 9.886  ; 9.922  ; 9.922  ; 9.886  ;
; UDSn         ; RAM_DATA[13]  ; 9.713  ; 9.642  ; 9.642  ; 9.713  ;
; UDSn         ; RAM_DATA[14]  ; 9.226  ; 9.226  ; 9.226  ; 9.226  ;
; UDSn         ; RAM_DATA[15]  ; 9.296  ; 9.296  ; 9.296  ; 9.296  ;
; UDSn         ; RAM_DQM0H     ; 6.854  ;        ;        ; 6.854  ;
; UDSn         ; RAM_DQM1H     ; 6.925  ;        ;        ; 6.925  ;
+--------------+---------------+--------+--------+--------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                 ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths   ; RF Paths     ; FF Paths   ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122       ; 94           ; 487        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 236          ; 236        ; 32           ; 32         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 236          ; 236        ; 32           ; 32         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 68           ; 68         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 68           ; 68         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 3            ; 3          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2232722      ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 3            ; 3          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0          ; 0            ; 0          ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                  ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths   ; RF Paths     ; FF Paths   ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 102503       ; 9122       ; 94           ; 487        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path   ; 0          ; false path   ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 236          ; 236        ; 32           ; 32         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; false path ; false path   ; false path ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 236          ; 236        ; 32           ; 32         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 13580071   ; > 2147483647 ; 2217268    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1031640      ; 0          ; 165064       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 830267       ; 0          ; 133501       ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 129          ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 68           ; 68         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0          ; false path   ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 68           ; 68         ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 1192263    ; 568068532    ; 1108       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 166160       ; 0          ; 432          ; 2          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60794        ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 11           ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 3            ; 3          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; 2232722      ; 0          ; 0            ; 0          ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; 0          ; 0            ; 0          ;
; CODEC_SCLK                                                 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; false path   ; false path ; 0            ; 0          ;
; CRT_PIN4_CLK1                                              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 3            ; 3          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; > 2147483647 ; 219309     ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 15737        ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 ; 2232722      ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 3            ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10           ; 0          ; 0            ; 0          ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 18           ; 0          ; 0            ; 0          ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+--------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23160      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23160      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23160      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23160      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                       ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CODEC_SCLK                                                 ; CODEC_SCLK                                                 ; 0          ; 0        ; 0          ; 1        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; CODEC_SCLK                                                 ; false path ; 0        ; false path ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23160      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 23160      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 17736      ; 5        ; 612        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23160      ; 0        ; 816        ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 23160      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 9192       ; 0        ; 0          ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 6909       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 9192       ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+-------------------------------------------------+
; Unconstrained Paths                             ;
+---------------------------------+-------+-------+
; Property                        ; Setup ; Hold  ;
+---------------------------------+-------+-------+
; Illegal Clocks                  ; 0     ; 0     ;
; Unconstrained Clocks            ; 0     ; 0     ;
; Unconstrained Input Ports       ; 135   ; 135   ;
; Unconstrained Input Port Paths  ; 29697 ; 29697 ;
; Unconstrained Output Ports      ; 234   ; 234   ;
; Unconstrained Output Port Paths ; 32403 ; 32403 ;
+---------------------------------+-------+-------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Dec 07 11:46:17 2021
Info: Command: quartus_sta SUSKA-III-C -c SUSKA-III-C
Info: qsta_default_script.tcl version: #1
Warning: Parallel compilation is not licensed and has been disabled
Info: Reading SDC File: '../../../rtl/vhdl/SUSKA-III-C/suska_cycloneII_core_ste.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2} {I_SYSCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0} {I_AUXCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 13 -multiply_by 32 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1} {I_AUXCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2} {I_AUXCLOCKS|altpll_component|pll|clk[2]}
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -18.401
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:   -18.401     -7932.130 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:   -18.401     -7932.130 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:   -15.544     -2130.320 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:   -15.544     -2130.320 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:   -13.239      -397.650 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:   -13.239      -397.650 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    23.014         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    30.595         0.000 CODEC_SCLK 
    Info:    38.203         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    55.840         0.000 CLK_PLL1 
    Info:    60.574         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is 0.278
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.278         0.000 CODEC_SCLK 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.445         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.620         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 21.278
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    21.278         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    21.278         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    21.278         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    21.278         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    78.638         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 2.274
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     2.274         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     2.274         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     2.472         0.000 CODEC_SCLK 
    Info:     2.858         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     2.858         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 7.852
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     7.852         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.584         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.420         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.139         0.000 CLK_PLL1 
    Info:    30.139         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.136         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -0.296
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.296        -0.571 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    -0.296        -0.571 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.788         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.788         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     2.514         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     2.514         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    24.520         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    36.825         0.000 CODEC_SCLK 
    Info:    38.707         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    59.706         0.000 CLK_PLL1 
    Info:    61.754         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is 0.093
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.093         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.093         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.110         0.000 CODEC_SCLK 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.215         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.240         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 27.015
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    27.015         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    27.015         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    27.018         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    27.018         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    80.111         0.000 CODEC_SCLK 
Info: Worst-case removal slack is 0.981
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.981         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.981         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     1.150         0.000 CODEC_SCLK 
    Info:     1.171         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     1.171         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 8.289
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2 
    Info:     8.289         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk2~1 
    Info:    11.695         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.531         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.250         0.000 CLK_PLL1 
    Info:    30.250         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    38.573         0.000 CODEC_SCLK 
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 546 megabytes
    Info: Processing ended: Tue Dec 07 11:46:47 2021
    Info: Elapsed time: 00:00:30
    Info: Total CPU time (on all processors): 00:00:30


