This is version 2K21A of the Suska IP core collection.
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Content:
1. Introduction
2. Distribution
3. Compiler notes
4. What's new
5. What's ahead
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1. Introduction:
  Suska is a collection of configware modules for the implementation of digital logic in FPGAs or CPLDs,
  which features the functionality of Atari Falcon-, ST-, STE-, Stacy-, STBook- and TT- computers. There
  is also Firmware for the microcontrollers on the different Suska hardware. And Suska includes Software 
  Tools for Developers. The configware includes many custom chips like GLUE, MMU (MCU), SHIFTER, DMA, 
  BLITTER, Stacy- and STBook-Shadow, and also cores for the LSI chips originally used in these machines 
  like the 68000 CPU (68K00), the multi function port MFP, the WD1772 floppy controller and the Yamaha 
  sound chip YM2149. There are several add ons like SD card interface, IDE interface, real time clock, 
  sound with a CODEC, SCSI/ ACSI bridge and a Bootloader prepared for the Suska-III-C and Suska-III-B 
  hardware for loading the operating system into the flash memory. There are also some hardware exten-
  sions on the Suska-III-C like USB and Ethernet. With the 2K14B version there are Atari Falcon custom 
  chips COMBEL, VIDEL and Falcon-DMA available. See below for more information.
  With the 2K15A version there are cores for the MC68030 in a light version and for the MC68010 and the
  MC68012. For a detailed description refer to the top level files headers of the respective processor.
  The 68K10 features the full bus width of the MC68012 and it has a downward compatibility mode for the
  MC68000. It can be clocked about five times higher than the 68K00. The 68K30L is instruction compatible
  to the MC68030 but has noc MMU, Caches and coprocessor interface.

2. Distribution:
    With release 2K13B the file structure of the distribution has changed in the following manner:
     - For the Suska-III-C machine all required source code is available to build this machine.
     - For the Suska-III-B machine all required source code except the SD drives module is available to 
       build this machine. Use an empty wrapper for the SD drives module where required.
     - We provide support for the Suska-III-C hardware and for the Suska-III-B platform in the 
       backend/Altera section.
     - We do not provide implementation support for other hardware platforms like Lattice, Microsemi 
       (formerly Actel) or Xilinx.
     - There is some top level file support for the Xilinx platform in the rtl/vhdl/suska-c directory.

3. Compiler notes:
    The core is compiled (and tested) with following integrated development environments:
     Altera: All Quartus II versions up to V18.1. Be aware, that the Suska hardware is equipped with
             different FPGAs. Altera has dropped support for some FPGAs in newer versions of Quartus.
             Refer to the respective documentation on Altera's website.
     Xilinx: Although this release is prepared for Xilinx we dropped since version 2K10A testing the system
             on Xilinx development tools or Xilinx hardware. Feel free to contribute.
     Lattice / Microsemi / others: Testers are welcome.

4. Whats's new:
    This year the 2K21A release is a major update. All CPUs are intensively debugged and tested with CPUTESTER. 
    There were several issues and all known bugs could be fixed. Further debugging were related to the Falcon 
    custom chips. All of the work results now in several enhancements like the Falcon for the Suska-III-C board 
    or the 68K30L processor for Suska-III-B. Behind this we worked on the Suska-III-BF hardware featuring a 
    68K30 CPU with MMU, Cache and coprocessor used in a Falcon hardware with 32 bit data and address bus. The 
    32 bit address and data bus is no available in the respective IP-cores featuring 68K10 or 68K30L or 68K30 
    processors (the latter one is no open source). There are limitations due to limited hardware resources e.g. 
    the Falcon core on Suska-III-C. For more information refer to the respective top level file headers (.vhdl).
    Since the Suska hardware is equipped with SD-RAM with more than 16MB, the IP-cores now feature ALT-RAM where
    possible (this is not possible with the 68K00 due to limitation of address lines). In this way the Suska-III-C
    comes with 48MB ALT-RAM and Suska-III-B with 16MB. To use these resources it is a good practice to switch to an 
    actual emuTos version.
    There have be done numerous fixes and changes in many ip cores. Refer to the respective top level file headers 
    for more information.

5. What's ahead:
    Expectedly this will be the last version of the Suska IP-core on experiment-S. But be confident. We have now
    several developers and participants and we think that it makes sense to switch to github. experiment-S will
    not be shut down but go on to interact as the info page for this project.

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20211224 Enjoy

Merry Christmas!

Wolfgang